MTP12P10

MTP12P10 Preferred Device Power MOSFET 12 Amps, 100 Volts P−Channel TO−220 This Power MOSFET is designed for medium voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. Features http://onsemi.com • Silicon Gate for Fast Switching Speeds − Switching Times Specified • • • • at 100°C Designer’s Data − IDSS, VDS(on), VGS(th) and SOA Specified at Elevated Temperature Rugged − SOA is Power Dissipation Limited Source−to−Drain Diode Characterized for Use With Inductive Loads Pb−Free Package is Available* 12 AMPERES, 100 VOLTS RDS(on) = 300 mW P−Channel D G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain−Source Voltage Drain−Gate Voltage (RGS = 1.0 MW) Gate−Source Voltage − Continuous − Non−repetitive (tp ≤ 50 ms) Drain Current − Continuous Drain Current − Pulsed Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Thermal Resistance − Junction−to−Case − Junction−to−Ambient° Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID IDM PD TJ, Tstg RqJC RqJA TL Value 100 100 ± 20 ± 40 12 28 75 0.6 −65 to 150 1.67 62.5 260 °C MTP12P10 A Y WW G Unit Vdc Vdc 4 Vdc Vpk Adc W W/°C °C °C/W 1 2 3 TO−220AB CASE 221A STYLE 5 MARKING DIAGRAM AND PIN ASSIGNMENT 4 Drain MTP12P10G AYWW 1 Gate 2 Drain 3 Source Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. = Device Code = Location Code = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device MTP12P10 MTP12P10G Package TO−220AB TO−220AB (Pb−Free) Shipping 50 Units/Rail 50 Units/Rail *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 1 June, 2006 − Rev. 4 Publication Order Number: MTP12P10/D MTP12P10 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = Rated VDSS, VGS = 0, TJ = 125°C) Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1) Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100°C Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 6.0 Adc) Drain−Source On−Voltage (VGS = 10 V) (ID = 12 Adc) (ID = 6.0 Adc, TJ = 100°C) Forward Transconductance (VDS = 15 V, ID = 6.0 A) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 1) (TJ = 100°C) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge SOURCE−DRAIN DIODE CHARACTERISTICS (Note 1) Forward On−Voltage Forward Turn−On Time Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE (TO−204) Internal Drain Inductance, (Measured from the contact screw on the header closer to the source pin and the center of the die) Internal Source Inductance (Measured from the source pin, 0.25″ from the package to the source bond pad) INTERNAL PACKAGE INDUCTANCE (TO−220) Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) 1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. Ld 3.5 (Typ) 4.5 (Typ) Ls 7.5 (Typ) − − − nH Ld Ls 5.0 (Typ) 12.5 (Typ) − − nH (IS = Rated ID, VGS = 0) VSD ton trr 4.0 (Typ) 5.5 Vdc (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) See Figure 11 (VDD = 25 V, ID = 0.5 Rated ID, RG = 50 W) See Figures 12 and 13 td(on) tr td(off) tf Qg Qgs Qgd − − − − 33 (Typ) 16 (Typ) 17 (Typ) 50 150 150 150 50 − − nC ns (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 10 Ciss Coss Crss − − − 920 575 200 pF VGS(th) RDS(on) VDS(on) − − gFS 2.0 4.2 3.8 − mhos 2.0 1.5 − 4.5 4.0 0.3 Vdc W Vdc V(BR)DSS IDSS − − IGSSF IGSSR − − 10 100 100 100 nAdc nAdc 100 − Vdc mAdc Symbol Min Max Unit Limited by stray inductance 300 (Typ) − ns http://onsemi.com 2 MTP12P10 TYPICAL ELECTRICAL CHARACTERISTICS VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 20 18 −I D, DRAIN CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0 1 VGS = −20 V TJ = 25°C 10 V 1.2 VDS = VGS ID = 1 mA 1.1 8V 7V 1 0.9 6V 5V 0.8 2 3 4 5 6 7 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 9 10 −50 −25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 Figure 1. On−Region Characteristics VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 2. Gate−Threshold Voltage Variation With Temperature 2 VGS = 0 ID = 0.25 mA 20 25°C TJ = −55°C 100°C I D, DRAIN CURRENT (AMPS) 16 1.6 12 1.2 8 VDS = 20 V 0.8 4 0.4 0 0 4 8 12 16 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 20 0 −50 −75 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Transfer Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 4. Normalized Breakdown Voltage versus Temperature RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.5 VGS = 15 V 0.4 TJ = 100°C 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −50 −25 0 25 50 75 100 125 150 VGS = 10 V ID = 6 A 0.3 25°C −55°C 0.2 0.1 0 0 4 8 12 16 20 24 28 32 36 40 ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance versus Drain Current Figure 6. On−Resistance Variation With Temperature http://onsemi.com 3 MTP12P10 SAFE OPERATING AREA INFORMATION 50 10 ms I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 1 ms 10 ms VGS = 20 V SINGLE PULSE TC = 25°C 1 dc 0.1 ms 40 10 30 20 MTM/MTP12P06 MTM/MTP12P06 RDS(on) LIMIT PACKAGE LIMIT THERMAL LIMIT MTM/MTP12P10 10 1 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 10 0 0 10 MTM/MTP12P10 30 50 70 20 40 60 80 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 90 100 Figure 7. Maximum Rated Forward Biased Safe Operating Area FORWARD BIASED SAFE OPERATING AREA Figure 8. Maximum Rated Switching Safe Operating Area SWITCHING SAFE OPERATING AREA The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, “Transient Thermal Resistance−General Data and Its Use” provides detailed instructions. The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn−on and turn−off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: TJ(max) − TC RqJC 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.5 0.3 0.2 0.1 0.1 0.05 0.05 0.03 0.02 SINGLE PULSE 0.01 0.01 0.02 0.05 0.1 0.2 0.5 1 0.01 0.02 t1 t2 DUTY CYCLE, D = t1/t2 2 5 t, TIME (ms) 10 20 P(pk) RqJC(t) = r(t) RqJC RqJC = 1.67°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 50 100 200 500 1000 D = 0.5 0.2 Figure 9. Thermal Response http://onsemi.com 4 MTP12P10 1600 VGS, GATE SOURCE VOLTAGE (VOLTS) TC = 25°C VGS = 0 f = 1 MHz Ciss 800 Coss 400 Crss 0 0 10 30 20 VDS, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 40 0 −2 −4 −6 −8 −10 −12 −14 −16 80 V 0 5 10 15 20 25 30 35 40 45 50 Qg, TOTAL GATE CHARGE (nC) VDS = 30 V 50 V TJ = 25°C ID = 12 A C, CAPACITANCE (pF) 1200 Figure 10. Capacitance Variation Figure 11. Gate Charge versus Gate−To−Source Voltage RESISTIVE SWITCHING VDD ton RL Vout Vin PULSE GENERATOR Rgen 50 W z = 50 W 50 W INPUT, Vin 50% 10% PULSE WIDTH DUT OUTPUT, Vout 10% 90% 50% td(on) tr 90% td(off) toff tf 90% INVERTED Figure 12. Switching Test Circuit Figure 13. Switching Waveforms http://onsemi.com 5 MTP12P10 PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AB −T− B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.020 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 0.508 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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