NB2308AI5HDTG

NB2308A 3.3 V Zero Delay Clock Buffer The NB2308A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It is available in a 16 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input−to−output propagation delay is guaranteed to be less than 250 ps, and the output−to−output skew is guaranteed to be less than 200 ps. The NB2308A has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three−stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple NB2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. The NB2308A is available in five different configurations (Refer to NB2308A Configurations Table). The NB2308Ax1* is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The NB2308Ax1H is the high−drive version of the −1 and the rise and fall times on this device are much faster. The NB2308Ax2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The NB2308Ax3 allows the user to obtain 4X and 2X frequencies on the outputs. The NB2308Ax4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The NB2308Ax5H is a high−drive version with REF/2 on both banks. Features http://onsemi.com MARKING DIAGRAMS* 16 1 SOIC−16 D SUFFIX CASE 751B 1 XXXXXXXXXG AWLYWW 16 16 16 1 TSSOP−16 DT SUFFIX CASE 948F 1 XXXX XXXX ALYWG G XXXX = Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • Zero Input − Output Propagation Delay, Adjustable by Capacitive • • • • • • • • • • • Load on FBK Input Multiple Configurations − Refer to NB2308A Configurations Table Input Frequency Range: 15 MHz to 133 MHz Multiple Low−Skew Outputs Output−Output Skew Less than 200 ps Device−Device Skew Less than 700 ps Two banks of four outputs, three−stateable by two select inputs Less than 200 ps Cycle−to−Cycle Jitter Available in 16−pin SOIC and TSSOP Packages 3.3V operation Advanced 0.35 m CMOS Technology These are Pb−Free Devices** ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. *x = C for Commercial; I for Industrial. **For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 3 1 Publication Order Number: NB2308A/D NB2308A FBK PLL B2 Extra Divider (−3, −4) MUX Extra Divider (−5H) CLKA2 CLKA1 B2 REF CLKA3 S2 SELECT INPUT DECODING S1 B2 CLKA4 CLKB1 Extra Divider (−2, −3) CLKB2 CLKB3 CLKB4 Figure 1. Block Diagram (see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams) Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial) Device NB2308Ax1 NB2308Ax1H NB2308Ax2 NB2308Ax2 NB2308Ax3 NB2308Ax3 NB2308Ax4 NB2308Ax5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference B2 Reference Reference Reference B2 Reference Reference or Reference (Note 1) 2 X Reference 2 X Reference Reference B2 Bank B Frequency 1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the NB2308Ax2. Table 2. SELECT INPUT DECODING S2 0 0 1 1 S1 0 1 0 1 Clock A1 − A4 Three−state Driven Driven (Note 2) Driven Clock B1 − B4 Three−state Three−state Driven Driven Output Source PLL PLL Reference PLL PLL ShutDown Y N Y N 2. Outputs inverted on 2308−2 and 2308−3 in bypass mode, S2 = 1 and S1 = 0. http://onsemi.com 2 NB2308A REF CLKA1 CLKA2 1 2 3 4 16 15 14 13 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 VDD GND NB2308A 5 6 7 8 12 11 10 9 CLKB1 CLKB2 S2 Figure 2. Pin Configuration Table 3. PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF (Note 3) CLKA1 (Note 4) CLKA2 (Note 4) VDD GND CLKB1 (Note 4) CLKB2 (Note 4) S2 (Note 5) S1 (Note 5) CLKB3 (Note 4) CLKB4 (Note 4) GND VDD CLKA3 (Note 4) CLKA4 (Note 4) FBK Description Input reference frequency, 5 V tolerant input. Buffered clock output, Bank A. Buffered clock output, Bank A. 3.3 V supply. Ground. Buffered clock output, Bank B. Buffered clock output, Bank B. Select input, bit 2. Select input, bit 1. Buffered clock output, Bank B. Buffered clock output, Bank B. Ground. 3.3 V supply. Buffered clock output, Bank A. Buffered clock output, Bank A. PLL feedback input. 3. Weak pulldown. 4. Weak pulldown on all outputs. 5. Weak pullup on these inputs. http://onsemi.com 3 NB2308A Table 4. MAXIMUM RATINGS Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Maximum Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL−STD−883, Method 3015) Min −0.5 −0.5 −0.5 −65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 Unit V V V °C °C °C V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Table 5. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance (Note 6) Commercial Industrial Description Min 3.0 0 −40 Max 3.6 70 85 30 15 7 Unit V °C pF pF pF 6. Applies to both REF Clock and FBK. Table 6. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current (Note 7) VIN = 0 V VIN = VDD IOL = 8 mA (−1, −2, −3, −4) IOL = 12 mA (−1H, −5H) IOH = −8 mA (−1, −2, −3, −4) IOH = −12 mA (−1H, −5H) Unloaded outputs 100 MHz REF Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (−1, −2, −3, −4) Unloaded outputs, 33 MHz REF (−1, −2, −3, −4) 7. Supply currents are measured for PLL−Bypass Mode (S2 = 1, S1 = 0). −2, −3, −4 −1H, −5H 2.4 49 60 34 18 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V mA mA V V mA mA mA mA http://onsemi.com 4 NB2308A Table 7. SWITCHING CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter t1 Description Output Frequency Test Conditions 30 pF load (all devices) 15 pF load (−1H, −5H) 15 pF load (−1, −2, −3, −4) Measured at 1.4 V, FOUT = < 66.66 MHz 30 pF load Measured at 1.4 V, FOUT = < 50 MHz 15 pF load t3 Output Rise Time (−1, −2, −3, −4) Measured between 0.8 V and 2.0 V 30 pF load Measured between 0.8 V and 2.0 V 15 pF load Output Rise Time (−1H, −5H) t4 Output Fall Time (−1, −2, −3, −4) Measured between 0.8 V and 2.0 V 30 pF load Measured between 2.0 V and 0.8 V 30 pF load Measured between 0.8 V and 2.0 V 15 pF load Output Fall Time (−1H, −5H) t5 Output−to−Output Skew on same Bank (−1, −2, −3, −4) Output−to−Output Skew (−1H, −5H) Output Bank A−to−Output Bank B Skew (−1, −4, −5H) Output Bank A−to−Output Bank B Skew (−2, −3) t6 t7 tJ Delay, REF Rising Edge to FBK Rising Edge Device−to−Device Skew Cycle−to−Cycle Jitter (−1, −1H, −4, −5H) Measured between 2.0 V and 0.8 V 30 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of the device Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs 15 pF load Cycle−to−Cycle Jitter (−2, −3) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load tLOCK PLL Lock Time Stable power supply, valid clock presented on REF and FBK pins 0 0 Min 15 15 15 40.0 45.0 50.0 50.0 Typ Max 100 133.3 133.3 60.0 55.0 2.20 1.50 1.50 2.20 1.50 1.25 200 200 200 400 ±250 700 200 200 100 400 400 1.0 ms ps ps ps ps ns ns Unit MHz t1 Duty Cycle = (t2 / t1) * 100 (all devices) % http://onsemi.com 5 NB2308A Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. 1500 REF INPUT TO CLKA/CLKB DELAY (ps) 1000 500 0 −500 −1000 −1500 −30 −25 −20 −15 −10 To close the feedback loop of the NB2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input−output delay. This is shown in Figure 3. For applications requiring zero input−output delay, all outputs including the one providing feedback should be equally loaded. If input−output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output−output skew, be sure to load outputs equally. −5 0 5 10 15 20 25 30 OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF) Figure 3. REF Input to CLKA/CLKB Delay vs. Difference in Loading between FBK Pin and CLKA/CLKB Pins SWITCHING WAVEFORMS t1 t2 1.4 V 1.4 V 1.4 V OUTPUT 2.0 V 0.8 V t3 2.0 V 0.8 V t4 0V 3.3 V Figure 4. Duty Cycle Timing Figure 5. All Outputs Rise/Fall Time OUTPUT OUTPUT 1.4 V 1.4 V t5 INPUT OUTPUT t6 V DD 2 V DD 2 Figure 6. Output − Output Skew Figure 7. Input − Output Propagation Delay FBK_Device 1 FBK_Device 2 t7 V DD 2 V DD 2 Figure 8. Device − Device Skew http://onsemi.com 6 NB2308A TEST CIRCUITS VDD VDD 0.1 mF VDD 0.1 mF 1 kW OUTPUTS 1 kW VDD GND 0.1 mF GND GND 10 pF OUTPUTS CLKOUT CLOAD VDD 0.1 mF GND Figure 9. Test Circuit #1 Figure 10. Test Circuit #2 For parameter t8 (output slew rate) on −1H devices BLOCK DIAGRAMS FBK FBK CLKA1 CLKA1 CLKA2 CLKA2 REF PLL MUX CLKA3 S2 SELECT INPUT DECODING S1 CLKB1 CLKB1 CLKB2 CLKB2 CLKB3 CLKB3 CLKB4 CLKB4 B2 CLKA4 REF PLL MUX CLKA3 S2 SELECT INPUT DECODING S1 CLKA4 Figure 11. NB2308Ax1 and NB2308Ax1H Figure 12. NB2308Ax2 http://onsemi.com 7 NB2308A BLOCK DIAGRAMS FBK FBK B2 CLKA1 B2 CLKA1 CLKA2 REF PLL MUX CLKA3 REF PLL MUX CLKA3 S2 SELECT INPUT DECODING S1 B2 S1 CLKB1 CLKB2 CLKB2 CLKB3 CLKB3 CLKB4 CLKB4 CLKA4 S2 SELECT INPUT DECODING CLKB1 CLKA4 CLKA2 Figure 13. NB2308Ax3 Figure 14. NB2308Ax4 FBK CLKA1 CLKA2 REF B2 PLL MUX CLKA3 S2 SELECT INPUT DECODING S1 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Figure 15. NB2308Ax5H http://onsemi.com 8 NB2308A ORDERING INFORMATION Device NB2308AC1DG NB2308AC1DR2G NB2308AI1DG NB2308AI1DR2G NB2308AC1HDG NB2308AC1HDR2G NB2308AI1HDG NB2308AI1HDR2G NB2308AC1DTG NB2308AC1DTR2G NB2308AI1DTG NB2308AI1DTR2G NB2308AC1HDTG NB2308AC1HDTR2G NB2308AI1HDTG NB2308AI1HDTR2G NB2308AC2DG NB2308AC2DR2G NB2308AI2DG NB2308AI2DR2G NB2308AC2DTG NB2308AC2DTR2G NB2308AI2DTG NB2308AI2DTR2G Marking 2308AC1G 2308AC1G 2308AI1G 2308AI1G 2308AC1HG 2308AC1HG 2308AI1HG 2308AI1HG 2308AC1 2308AC1 2308AI1 2308AI1 2308AI1H 2308AI1H 2308AI1H 2308AI1H 2308AC2G 2308AC2G 2308AI2G 2308AI2G 2308AC2 2308AC2 2308AI2 2308AI2 Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) Shipping† 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel Availability Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB2308A ORDERING INFORMATION Device NB2308AC3DG NB2308AC3DR2G NB2308AI3DG NB2308AI3DR2G NB2308AC3DTG NB2308AC3DTR2G NB2308AI3DTG NB2308AI3DTR2G NB2308AC4DG NB2308AC4DR2G NB2308AI4DG NB2308AI4DR2G NB2308AC4DTG NB2308AC4DTR2G NB2308AI4DTG NB2308AI4DTR2G NB2308AC5HDG NB2308AC5HDR2G NB2308AI5HDG NB2308AI5HDR2G NB2308AC5HDTG NB2308AC5HDTR2G NB2308AI5HDTG NB2308AI5HDTR2G Marking 2308AC3G 2308AC3G 2308AI3G 2308AI3G 2308AC3 2308AC3 2308AI3 2308AI3 2308AC4G 2308AC4G 2308AI4G 2308AI4G 2308AC4 2308AC4 2308AI4 2308AI4 2308AC5HG 2308AC5HG 2308AI5HG 2308AI5HG 2308AC5H 2308AC5H 2308AI5H 2308AI5H Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) Shipping† 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel Availability Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NB2308A PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K 16 9 2X L/2 J1 B − U− L PIN 1 IDENT. 1 8 SECTION N−N J N 0.15 (0.006) T U S 0.25 (0.010) M A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E http://onsemi.com 11 ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −W− NB2308A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE J − A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 − B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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