NB3N4666CDTR2G

NB3N4666C 3.3 V Quad LVCMOS Differential Line Receiver Translator Description The NB3N4666C is a quad−channel LVDS line receiver/translator offering data rates up to 400 Mbps (200 MHz) and low power consumption. The NB3N4666C receiver incorporates input fail−safe protection circuit that provides a known output voltage under input open−circuit and terminated (100 W) conditions. The four independent inputs accept differential signals such as: M−LVDS, LVDS, LVPECL and HCSL and translates them to a single−ended, 3.3 V LVCMOS. The NB3N4666C also offers active high and active low enable/disable inputs (EN and EN) that allow users to control outputs of all four receivers. These inputs enable or disable the receivers and switch the outputs to an active or high impedance state respectively (see Table 2). The high impedance mode feature helps to reduce the quiescent power consumption to less than 10 mW typical, when the outputs of one or more NB3N4666C devices are multiplexed together. www.onsemi.com MARKING DIAGRAMS 16 NB3N 4666 ALYWG G 1 TSSOP−16 DT SUFFIX CASE 948F A L Y W G 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Features • Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input • • • • • • • • • • Signal Levels Maximum Data Rate of 400 Mbps Maximum Clock Frequency of 200 MHz 25 ps Typical Channel−to−Channel Skew 3.3 ns Maximum Propagation Delay 3.3 V ±10% Power Supply High Impedance Outputs When Disabled ♦ Low Quiescent Power < 10 mW Typical Supports Open and Terminated Input Fail−safe −40°C to +85°C Ambient Operating Temperature 16−Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm These are Pb−Free Devices NB3N4666C IN1 IN1 R1 • • • • R4 OUT4 OUT1 EN EN OUT2 OUT3 R2 R3 IN3 IN3 IN2 IN2 GND Applications Point−to−point Data Transmission Backplane Receivers Clock Distribution Networks Multidrop Buses VCC IN4 IN4 Figure 1. Functional Block Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2016 July, 2017 − Rev. 1 1 Publication Order Number: NB3N4666C/D NB3N4666C Table 1. PIN DESCRIPTION Pin TSSOP Name I/O Description 1 IN1 Input Receiver Channel 1 Inverted Input. 2 IN1 Input Receiver Channel 1 Non−inverted Input. 3 OUT1 LVCMOS Output Receiver Channel 1 Output. 4 EN Input Enable 5 OUT2 LVCMOS Output Active High Enable. See Table 2 for output enable function. 6 IN2 Input Receiver Channel 2 Non−inverted Input. 7 IN2 Input Receiver Channel 2 Inverted Input. 8 GND Power 9 IN3 Input Receiver Channel 3 Inverted Input. Receiver Channel 3 Non−inverted Input. Receiver Channel 2 Output. Power Supply Ground (Note 1) 10 IN3 Input 11 OUT3 LVCMOS Output 12 EN Inverted Input Enable 13 OUT4 LVCMOS Output 14 IN4 Input Receiver Channel 4 Non−inverted Input. 15 IN4 Input Receiver Channel 4 Inverted Input. 16 VCC Power Receiver Channel 3 Output. Active Low Enable. Defaults Low when left open; internal pull−down resistor. See Table 2 for output enable function. Receiver Channel 4 Output. 3.3 V ±10% Positive Supply Voltage (Note 1) 1. All VCC and GND pins must be externally connected to a power supply for proper operation. Bypass each supply pin with 0.01 mF to GND. IN1 1 16 VCC IN1 2 15 IN4 OUT1 3 14 IN4 EN 4 13 OUT4 OUT2 5 12 EN IN2 6 11 OUT3 IN2 7 10 IN3 GND 8 9 IN3 Figure 2. TSSOP−16 Pinout (Top View) www.onsemi.com 2 NB3N4666C Table 2. OUTPUT ENABLE FUNCTION INPUTS OUTPUT EN ENABLES EN IN, IN OUT L H X Z VID ≥ 100 mV H VID ≤ −100 mV L Full Fail−safe OPEN or Terminated H All other combinations of ENABLE inputs Fail−Safe Feature Terminated Input. If the driver to the input is disconnected, in a TRI−STATE or power−off condition, the output will again be in a HIGH state, even with a 100−W termination resistor across the input pins. Do not connect unused receiver inputs to ground or any other voltages. VID, DIFFERENTIAL INPUT VOLTAGE (mV) The multi−level receiver’s internal fail−safe circuitry is designed to provide fail−safe protection for floating/open or terminated receiver inputs, and will output a stable High−level voltage state. Open Input Pins. The NB3N4666C is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. The internal input circuitry will ensure a HIGH stable output state for open inputs. 200 mV High 100 mV Transition Region 0 mV −100 mV Low −200 mV Figure 3. Receiver Differential Input Voltage Showing Transition Region Table 3. ATTRIBUTES (Note 2) Characteristics ESD Protection Value Human Body Model Charged Device Model CIN − Input Capacitance 6 kV 500 V 4 pF typical RIN − Input Impedance > 10 kW RPD − Inverted Input Enable Pull−down Resistor 800 kW Moisture Sensitivity Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 621 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. www.onsemi.com 3 NB3N4666C Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Supply Voltage Range VIN Input Voltage Range TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) qJC Thermal Resistance (Junction−to−Case) Tsol Wave Solder (Pb−Free) Condition 2 Rating Unit GND = 0 V 4.6 V GND = 0 V −0.5 to VCC +0.5 V −40 to +85 °C −65 to +150 °C 0 lfpm TSSOP−16 138 °C/W 500 lfpm TSSOP−16 108 2S2P TSSOP−16 33−36 °C/W 265 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. DC CHARACTERISTICS (VCC = 3.3 V ± 10%; TA = −40°C to +85°C) Symbol Characteristic Min Typ Max Unit 2.97 3.30 3.63 V POWER SUPPLY VCC Power Supply Voltage ICC No Load Supply, All Receivers Enabled (EN = VCC, EN = GND, inputs open) 10 15 mA ICCZ No Load Supply, All Receivers Disabled (EN = GND and EN = VCC, inputs open) 3 5.5 mA 300 mW PD Power Dissipation (Note 6) LVCMOS OUTPUTS VOH Output High Voltage IOH = −0.4 mA, VID = +200 mV IOH = −0.4 mA, Input Terminated (100 W Across Differential Inputs) IOH = −0.4 mA, Input Shorted 2.7 2.7 2.7 3.0 3.0 3.0 VOL Output Low Voltage IOS Output Short Circuit Current (Note 4) IOZ Output Off State Current V IOL = 2 mA, VID = −200 mV GND 0.1 0.25 V Outputs enabled, VOUT = 0 V −15 −48 −120 mA Outputs disabled, VOUT = 0 V or VCC −10 ±1 +10 mA CONTROL INPUTS (EN, EN) VIH Input HIGH Voltage VCC = 3.3 V 2.0 VCC V VIL Input LOW Voltage VCC = 3.3 V GND 0.8 V VIN = 0 V or VCC, other input = VCC or 0 V −10 ±1 +10 mA ICL = −18 mA −1.5 −0.9 II VCL Input Current Input Clamp Voltage V DIFFERENTIAL INPUTS (IN, IN) VCMR IIN Input Common Mode Range VID = 200 mV peak to peak; Differential Input Voltage (VID) (Notes 3 and 5) (Figures 6 and 7) 0.1 Input Current −25 −30 −30 VIN = +2.8 V, VCC = 3.6 V or 0 V VIN = 0 V, VCC = 3.6 V or 0 V VIN = +3.63 V, VCC = 0 V ±1 ±1 2.3 V +25 +30 +30 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by design and characterization. Not tested in production. 4. Output short−circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Note that only one output should be shorted at a time; do not exceed the maximum junction temperature specification (150°C). 5. The VCMR range is reduced for larger VID. Example: if VID = 400 mV, the VCMR is 0.2 V to 2.2 V. A VID up to VCC may be applied to the IN/IN inputs with the Common−Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common−mode range. 6. Tested with 100 MHz input frequency on all channels, EN = VCC, EN = GND. www.onsemi.com 4 NB3N4666C Table 6. AC CHARACTERISTICS (VCC = 3.3 V ± 10%; TA = −40°C to +85°C) (Note 7) Characteristic Min Typ Maximum Input Clock Frequency (Note 8) All Channels Switching 200 250 Maximum Data Rate 400 Propagation Delay (Note 9) (Figures 5 and 8) 1.8 Symbol fMAX fDATAMAX tplh/tphl tSKEW(o−o) Channel−to−channel Skew (Note 10) 0 tSKEW(pp) Part−to−part Skew (Note 11) tSKEW(p) Pulse Skew ⎢tPHL−tPLH⏐, VCM = VCC/2 (Note 12) (Figures 5 and 8) Unit MHz Mbps 3.3 ns 25 250 ps 50 500 ps 50 300 ps Output Rise/Fall Time, 20% − 80% (Figures 5 and 8) 600 1200 ps Tjit (f) Additive RMS Phase Jitter Integration Range: 12 kHz − 20 MHz, fc = 100 MHz, 25°C, VCC = 3.3 V 161 tplz/tphz Output Disable Time (Figures 9 and 10) RL = 2 kW 10 14 ns tpzl/tpzh Output Enable Time (Figures 9 and 10) RL = 2 kW 2 5 ns tr/tf 0 Max fs Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Generator waveform for all tests, unless otherwise specified: f = 50 MHz, CL = 10 pF (includes jig capacitance), tr and tf (10% to 90%) ≤ 2 ns for INx/INx. 8. fMAX generator input conditions: tr = tf < 1ns (10% to 90%), 50% duty cycle, differential (1.05 V to 1.35 V peak to peak). Output Criteria: 40% − 60% duty cycle, VOL (max 0.4 V), VOH (min 2.7 V), CL = 10 pF (stray plus probes) 9. Measured from the differential crosspoint of the input to VCC/2 of the output. 10. tSKEW(O−O) is defined as skew between outputs of the same device at the same supply voltage and with equal load conditions. 11. tSKEW(pp) is defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 12. tSKEW(p) is the magnitude difference in the differential propagation delay time between the positive−going edge and the negative−going edge of the same channel. www.onsemi.com 5 NB3N4666C The above phase noise data was captured using Agilent E5052A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The additive RMS phase jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 161 fs. The additive RMS phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. To obtain the most precise additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is greater than the noise floor of the device under test, the source noise will dominate the additive phase jitter calculation and lead to an incorrect negative result for the additive phase noise within the integration range. The Figure above is a good example of the NB3N4666C source generator phase noise having a significantly lower floor than the DUT and results in an additive phase jitter of 161 fs. NB3N4666C Additive RMS Phase Jitter @ 100 MHz 12 kHz to 20 MHz = 161 fs Additive RMS Phase Jitter + Ǹ(Source ) DUT) * (Source) 2 + Ǹ(278.49) * (227.25) 2 2 2 + 161 fs Figure 4. Typical Phase Noise Plot at fcarrier = 100 MHz at an Operating Voltage of 3.3 V, Room Temperature www.onsemi.com 6 NB3N4666C VCC IN SIGNAL GENERATOR OUT IN CL 50 W 50 W RECEIVER IS ENABLED Note: CL = Load and test jig capacitance (10 pF typical) Figure 5. AC Reference Measurement VCC VIHDmax VCMR MAX VILDmax IN IN IN VID = |VIHD(IN) − VILD(IN)| VCMR VIHDtyp VID = VIHD − VILD IN VIHD VILDtyp VILD VIHDmin VCMR MIN VILDmin GND Figure 6. Differential Inputs Driven Differentially Figure 7. VCMR Diagram IN 1.3 V 0 V (Differential) VID = 200 mVp−p 1.2 V IN 1.1 V tPHL tPLH 80% 80% VCC/2 VCC/2 20% 20% OUT VOL tf tr Figure 8. Receiver Propagation Delay, Rise and Fall Time www.onsemi.com 7 NB3N4666C VCC S1 RL IN OUT CL IN EN SIGNAL GENERATOR 50 W EN GND Notes: 1. CL = Load and test jig capacitance (10 pF typical). 2. S1 connected to VCC for TPZL and TPLZ measurements. 3. S1 connected to GND for TPZH and TPHZ measurements. Figure 9. Test Circuit for Receiver Enable/Disable Delay EN when EN = VCC OR Open Circuit VCC VCC/2 VCC/2 0V VCC VCC/2 VCC/2 0V EN when EN = GND tPHZ tPZH OUT with VID ≥ 100 mV VOH 0.5 V VCC/2 GND VCC tPLZ VCC/2 0.5 V OUT with VID ≤ −100 mV tPZL VOL Figure 10. Receiver Enable/Disable Delay Waveform ORDERING INFORMATION Device NB3N4666CDTR2G Package Shipping† TSSOP−16 5.0 x 4.4 mm (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. 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