NB3U1548CDG

NB3U1548C 3.3V/2.5V/1.8V/1.5V 160 MHz 1:4 LVCMOS/LVTTL Low Skew Over Voltage Tolerant Fanout Buffer www.onsemi.com Description The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout buffer targeted for clock generation in high performance telecommunication, networking and computing applications. The device is optimized for low skew clock distribution in low voltage applications. The input overvoltage tolerance enables using this device in mixed mode voltage applications. An output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output skew characteristics make the NB3U1548C ideal for those applications demanding well defined performance and repeatability. The NB3U1548C is packaged in a small SOIC−8 and in an TSSOP−8 package. Features • • • • • • • • • • Low skew 1:4 Fanout Buffer Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies LVCMOS Input and Output Levels 3.6 V Overvoltage Tolerance at the Clock and Control Inputs Supports Clock Frequencies up to 160 MHz LVCMOS Compatible Control Input for Output Disable Output Disabled to a High Impedance State −40°C to 85°C Ambient Operating Temperature Available in Pb−Free RoHS Compliant Packages (SOIC−8, TSSOP−8) These Devices are Pb−Free and are RoHS Compliant MARKING DIAGRAMS 8 8 1 SOIC−8 D SUFFIX CASE 751 1548C ALYWG G 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948S A L Y W, WW G 154 YWW AG 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2017 January, 2017 − Rev. 4 1 Publication Order Number: NB3U1548C/D NB3U1548C CLK_IN 1 8 OE Q1 2 7 VDD Q2 3 6 GND Q3 4 5 Q4 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTIONS Number Name 1 CLK_IN Input 2 Q1 Output Single−ended clock output. LVCMOS interface levels. 3 Q2 Output Single−ended clock output. LVCMOS interface levels. 4 Q3 Output Single−ended clock output. LVCMOS interface levels. 5 Q4 Output Single−ended clock output. LVCMOS interface levels. 6 GND Power Power supply ground. 7 VDD Power Power supply pin. 8 OE Input NOTE: Type Description Pulldown Pullup Single−ended clock input. LVCMOS interface levels. Output enable pin. See Table 3. LVCMOS interface levels. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance Test Conditions Min Typ Max Units 4 pF VDD = 3.465 V 14 pF VDD = 2.375 V 13 pF VDD = 1.95 V 13 pF VDD = 1.6 V 12 pF RPULLUP Input Pullup Resistor 51 kW RPULLDOWN Input Pulldown Resistor 51 kW ROUT Output Impedance VDD = 3.3 V ± 5% 9 W VDD = 2.5 V ± 5% 10 W VDD = 1.8 V ± 0.15 V 12 W VDD = 1.5 ± 0.1 V 15 W Function Table Table 3. OE CONFIGURATION TABLE Input OE Operation 0 Q[4:1] disabled (high−impedance) 1 (default) Q[4:1] enabled NOTE: OE is an asynchronous control. www.onsemi.com 2 NB3U1548C Table 4. ABSOLUTE MAXIMUM RATINGS Item Rating Supply Voltage, VDD 4.6 V Inputs, VI 3.6 V Outputs, VO −0.5 V to VDD + 0.5 V Package Thermal Impedance, θJA 8 Lead SOIC 8 Lead TSSOP 102.5°C/W (0 mps) 151.2°C/W (0 mps) Storage Temperature, TSTG −65°C to 150°C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 6 cm2 copper area. 2. For additional information, see Application Note AND8003/D. Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units 3.135 3.3 3.465 V 1 mA 2.625 V 1 mA 1.95 V 1 mA 1.6 V 1 mA POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3 V + 5%, TA = −405C to 855C VDD Power Supply Voltage IDDQ Quiescent Power Supply Current Inputs Open, Outputs Unloaded POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C VDD Power Supply Voltage 2.375 IDDQ Quiescent Power Supply Current 2.5 Inputs Open, Outputs Unloaded POWER SUPPLY DC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C VDD Power Supply Voltage 1.65 IDDQ Quiescent Power Supply Current 1.8 Inputs Open, Outputs Unloaded POWER SUPPLY DC CHARACTERISTICS, VDD = 1.5 V + 0.1 V, TA = −405C to 855C VDD Power Supply Voltage 1.4 IDDQ Quiescent Power Supply Current Inputs Open, Outputs Unloaded 1.5 LVCMOS DC CHARACTERISTICS, VDD = 3.3 V + 5%, TA = −405C to 855C VIH Input High Voltage 0.65 * VDD 3.6 V VIL Input Low Voltage −0.3 0.35 * VDD V 165 mA 5 mA IIH Input High Current CLK_IN OE VDD = VIN = 3.465 V IIL Input Low Current CLK_IN VDD = 3.465 V, VIN = 0 V −5 mA OE VDD = 3.465 V, VIN = 0 V −150 mA 2.6 V VDD = VIN = 3.465 V VOH Output High Voltage Q[4:1] IOH = −12 mA VOL Output Low Voltage Q[4:1] IOL = 12 mA 0.5 V LVCMOS DC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C VIH Input High Voltage 0.65 * VDD 3.6 V VIL Input Low Voltage −0.3 0.35 * VDD V IIH IIL Input High Current Input Low Current CLK_IN VDD = VIN = 2.625 V 165 mA OE VDD = VIN = 2.625 V 5 mA CLK_IN VDD = 2.625 V, VIN = 0 V −5 mA OE VDD = 2.625 V, VIN = 0 V −150 mA www.onsemi.com 3 NB3U1548C Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units LVCMOS DC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C VOH Output High Voltage Q[4:1] IOH = −12 mA VOL Output Low Voltage Q[4:1] IOL = 12 mA 1.8 V 0.5 V LVCMOS DC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C VIH Input High Voltage 0.65 * VDD 3.6 V VIL Input Low Voltage −0.3 0.35 * VDD V 165 mA 5 mA IIH Input High Current CLK_IN VDD = VIN = 1.95 V OE IIL Input Low Current CLK_IN VDD = 1.95 V, VIN = 0 V −5 mA OE VDD = 1.95 V, VIN = 0 V −150 mA VDD – 0.45 VOH Output High Voltage Q[4:1] IOH = −6 mA VOL Output Low Voltage Q[4:1] IOL = 6 mA V 0.45 V LVCMOS DC CHARACTERISTICS, VDD = 1.5 V + 0.1 V, TA = −405C to 855C VIH Input High Voltage 0.65 * VDD 3.6 V VIL Input Low Voltage −0.3 0.35 * VDD V 165 mA 5 mA IIH Input High Current CLK_IN OE VDD = VIN = 1.6 V IIL Input Low Current CLK_IN VDD = 1.6 V, VIN = 0 V −5 mA OE VDD = 1.6 V, VIN = 0 V −150 mA 0.75 * VDD V VDD = VIN = 1.6 V VOH Output High Voltage Q[4:1] IOH = −4 mA VOL Output Low Voltage Q[4:1] IOL = 4 mA 0.25 * VDD V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 4 NB3U1548C Table 6. AC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units 160 MHz AC CHARACTERISTICS, VDD = 3.3 V + 5%, TA = −405C to 855C fOUT Output Frequency tpLH Propagation Delay (low to high transition); (Notes 4, 8) 0.7 2.1 ns tpHL Propagation Delay (high to low transition); (Notes 4, 8) 0.7 2.1 ns tPLZ, tPHZ Disable Time, (active to high−impedance) 10 ns tPZL, tPZH Enable Time, (high−impedance to active) 10 ns tsk(o) Output Skew; (Notes 5, 6) 250 ps tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range: 12 kHz − 5 MHz tR / tF Output Rise/Fall Time 10% to 90% odc Output Duty Cycle 0.094 ps 0.33 1.2 ns 48 53 % AC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C fOUT Output Frequency 160 MHz tpLH Propagation Delay (low to high transition); (Notes 4, 8) 0.8 2.0 ns tpHL Propagation Delay (high to low transition); (Notes 4, 8) 0.8 2.0 ns tPLZ, tPHZ Disable Time (active to high−impedance) 10 ns tPZL, tPZH Enable Time (high−impedance to active) 10 ns tsk(o) Output Skew; (Notes 5, 6) 250 ps tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range: 12 kHz − 5 MHz tR / tF Output Rise/Fall Time 10% to 90% odc Output Duty Cycle 0.076 ps 0.33 1.2 ns 45 53 % 160 MHz AC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C fOUT Output Frequency tpLH Propagation Delay (low to high transition); (Notes 4, 8) 1.1 2.8 ns tpHL Propagation Delay (high to low transition); (Notes 4, 8) 1.1 2.8 ns tPLZ, tPHZ Disable Time (active to high−impedance) 10 ns tPZL, tPZH Enable Time (high−impedance to active) 10 ns tsk(o) Output Skew; (Notes 5, 6) 250 ps tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range: 12 kHz − 5MHz 0.193 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Characterized up to FOUT ≤ 150 MHz. 4. Measured from the VDD/2 of the input to VDD/2 of the output. 5. This parameter is defined in accordance with JEDEC Standard 65. 6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. 8. With rail to rail input clock. www.onsemi.com 5 NB3U1548C Table 6. AC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units 0.11 0.6 ns 47 53 % 160 MHz AC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C tR / tF Output Rise/Fall Time odc Output Duty Cycle 0.63 V to 1.17 V AC CHARACTERISTICS, VDD = 1.5 V + 0.1 V, TA = −405C to 855C fOUT Output Frequency tpLH Propagation Delay (low to high transition); (Notes 4, 8) 1.5 3.5 ns tpHL Propagation Delay (high to low transition); (Notes 4, 8) 1.5 3.5 ns tPLZ, tPHZ Disable Time (active to high−impedance) 10 ns tPZL, tPZH Enable Time (high−impedance to active) 10 ns tsk(o) Output Skew; (Notes 5, 6) 250 ps tsk(pp) Part−to−Part Skew; (Notes 5, 7) 800 ps tjit Buffer Additive Phase Jitter, RMS 25 MHz, Integration Range: 12 kHz − 5 MHz tR / tF Output Rise/Fall Time 0.525 V to 0.975 V odc Output Duty Cycle 0.266 ps 0.11 0.6 ns 47 53 % NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Characterized up to FOUT ≤ 150 MHz. 4. Measured from the VDD/2 of the input to VDD/2 of the output. 5. This parameter is defined in accordance with JEDEC Standard 65. 6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. 7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. 8. With rail to rail input clock. www.onsemi.com 6 NB3U1548C Parameter Measurement Information 1.65 V ± 5% 1.25 V ± 5% SCOPE SCOPE VDD VDD Z = 50 W LVCMOS Z = 50 W Qx LVCMOS Qx 50 W 50 W GND GND −1.65 V ± 5% −1.25 V ± 5% Figure 3. 3.3 V Output Load AC Test Circuit Figure 4. 2.5 V Output Load AC Test Circuit 0.9 V ± 0.075 V 0.75 V ± 0.05 V SCOPE SCOPE VDD VDD Z = 50 W LVCMOS Z = 50 W Qx LVCMOS Qx 50 W 50 W GND GND −0.75 V ± 0.05 V −0.9 V ± 0.075 V Figure 5. 1.8 V Output Load AC Test Circuit Figure 6. 1.5 V Output Load AC Test Circuit Part 1 Qx V DD 2 Qx V DD 2 Part 2 Qy V DD 2 Qy tsk(o) Figure 7. Output Skew V DD 2 tsk(pp) Figure 8. Part−to−Part Skew www.onsemi.com 7 NB3U1548C Parameter Measurement Information, (continued) OE (High−level enabling) VDD VDD/2 V DD 2 VDD/2 0V Q1:Q4 V DD 2 tPW tPERIOD tDIS tEN Output Qx (See Note) VOH VDD/2 odc = VDD/2 Figure 9. Output Enable/Disable Time 0.975 V 1.17 V 0.525 V tR Q1:Q4 90% 10% tR tF tR Figure 12. 1.8 V Output Rise/Fall Time CLK_IN Q1:Q4 0.63 V Q1:Q4 tF 10% 1.17 V 0.63 V Figure 11. 1.5 V Output Rise/Fall Time 90% x 100% Figure 10. Output Duty Cycle/Pulse Width/Period 0.975 V 0.525 V tPW tPERIOD Q1:Q4 tF Figure 13. 2.5 V and 3.3 V Output Rise/Fall Time V DD 2 V DD 2 tpLH V DD 2 V DD 2 tpHL Figure 14. Propagation Delay www.onsemi.com 8 NB3U1548C Table 7. THERMAL RESISTANCE qJA qJA by Velocity FOR 8 LEAD SOIC, FORCED CONVECTION 0 1 2.5 102.5°C/W 93.5°C/W 88.6°C/W 0 1 2.5 151.2°C/W 145.9°C/W 143.3°C/W Meters per Second Multi−Layer PCB, JEDEC Standard Test Boards FOR 8 LEAD TSSOP, FORCED CONVECTION Meters per Second Multi−Layer PCB, JEDEC Standard Test Boards qJA by Velocity Table 8. ORDERING INFORMATION Device Package Shipping† NB3U1548CDG SOIC−8 (Pb−Free) 96 Units / Tube NB3U1548CDR2G SOIC−8 (Pb−Free) 3000 / Tape & Reel NB3U1548CDTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE C DATE 20 JUN 2008 SCALE 2:1 K REF 8x 0.20 (0.008) T U 0.10 (0.004) S 2X L/2 8 0.20 (0.008) T U T U B −U− 1 J J1 4 V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ K1 K A −V− S S 5 L PIN 1 IDENT M SECTION N−N −W− C 0.076 (0.003) D −T− SEATING DETAIL E G PLANE 0.25 (0.010) N M DIM A B C D F G J J1 K K1 L M N F MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* XXX YWW AG G DETAIL E XXX A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: STATUS: 98AON00697D ON SEMICONDUCTOR STANDARD NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 October, DESCRIPTION: 2002 − Rev. 0 TSSOP−8 http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. Case Outline Number: PAGE 1 OFXXX 2 DOCUMENT NUMBER: 98AON00697D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. 18 APR 2000 A ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS. 13 JAN 2006 B CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C. REBELLO. 13 MAR 2006 C REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED MARKING INFORMATION. REQ. BY C. REBELLO. 20 JUN 2008 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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