NB6L11MMNG

NB6L11M 2.5V / 3.3V 1:2 Differential CML Fanout Buffer Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 16 1 QFN−16 MN SUFFIX CASE 485G NB6L 11M ALYWG G The NB6L11M is a differential 1:2 CML fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pins and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single−ended PECL or NECL inputs. For all single−ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor−coupled inputs. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L11M is a member of the ECLinPS MAXt family of high performance clock products. Features A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • • • • • • • • • • • • Maximum Input Clock Frequency > 4 GHz, Typical 225 ps Typical Propagation Delay 70 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter Differential CML Outputs, 380 mV peak−to−peak, typical LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices Q0 VTD D D VTD VREFAC Q0 Q1 Q1 Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2007 1 March, 2007 − Rev. 1 Publication Order Number: NB6L11M/D NB6L11M VCC 16 VTD D D VTD VEE VEE 15 14 VCC 13 Q0 Q0 Q1 Q1 Exposed Pad (EP) 1 2 NB6L11M 3 4 12 11 10 9 5 6 7 8 VCC VCC VREFAC VEE Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin 1 2 Name VTD D I/O − ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input − − Internal 50 W Termination Pin for D input. Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. Description 3 D Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. 4 5 6 7 8 9 10 11 12 13 14 15 16 − VTD VCC VREFAC VEE VCC Q1 Q1 Q0 Q0 VCC VEE VEE VCC EP Internal 50 W Termination Pin for D input. Positive Supply Voltage Output Reference Voltage for direct or capacitor coupled inputs − − CML Output CML Output CML Output CML Output − − − − − Negative Supply Voltage Positive Supply Voltage Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Positive Supply Voltage Negative Supply Voltage Negative Supply Voltage Positive Supply Voltage The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation. 2. All VCC and VEE pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB6L11M Table 2. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Human Body Model Machine Model 16−QFN Oxygen Index: 28 to 34 Value > 2 kV > 200V Level 1 UL 94 V−0 @ 0.125 in Table 3. MAXIMUM RATINGS Symbol VCC VEE VIO VINPP IIN IOUT IVREFAC TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input/Output Voltage Negative Input/Output Voltage Differential Input Voltage |D − D| Input Current Through RT (50 W Resistor) Output Current (CML Output) VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 3) Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free 0 lfmp 500 lfmp (Note 3) QFN−16 QFN−16 QFN−16 16 QFN Static Surge Continuous Surge Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V −0.5 v VIo v VCC + 0.5 +0.5 v VIo v VEE − 0.5 Condition 2 Rating 4.0 −4.0 4.0 −4.0 VCC − VEE 45 80 25 50 $0.5 −40 to +85 −65 to +150 42 35 4 265 Unit V V V V V mA mA mA mA mA _C _C _C/W _C/W _C/W _C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L11M Table 4. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) 45 60 75 mA Characteristic Min Typ Max Unit CML OUTPUTS (Notes 4 and 5) VOH Output HIGH Voltage VCC = 3.3 V VCC = 2.5 V VOL Output LOW Voltage VCC = 3.3V VCC = 2.5V DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 4 and 5) (Note 6) Vth VIH VIL VISE VREFAC VREFAC Output Reference Voltage VCC – 1525 VCC – 1425 VCC – 1325 mV Input Threshold Reference Voltage Range (Note 7) Single−ended Input HIGH Voltage Single−ended Input LOW Voltage Single−ended Input Voltage Amplitude (VIH − VIL) 1125 Vth + 75 VEE 150 VCC − 75 VCC Vth − 75 2800 mV mV mV mV VCC − 40 3260 2460 VCC − 500 2800 2000 VCC − 10 3290 2490 VCC − 400 2900 2100 VCC 3300 2500 VCC − 300 3000 2200 mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8) VIHD VILD VID VCMR IIH IIL Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input Common Mode Range (Differential Configuration) (Note9) Input HIGH Current D / D, (VTD/VTD Open) Input LOW Current D / D, (VTD/VTD Open) VEE + 1200 VEE VEE + 100 VEE + 1150 −10 −50 VCC VCC − 100 VCC − VEE VCC − 50 50 10 mV mV mV mV uA uA TERMINATION RESISTORS RTIN RTOUT Internal Input Termination Resistor Internal Output Termination Resistor 40 40 50 50 60 60 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs loaded with 50 W to VCC for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR min varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L11M Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C; (Note 10) Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPP(MIN) (Note 15) (See Figure 9) Propagation Delay Duty Cycle Skew (Note 11) Within Device Skew Device to Device Skew (Note 12) Output Clock Duty Cycle (Reference Duty Cycle = 50%) RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14) VINPP tr tf Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) Output Rise/Fall Times @ 0.5 GHz (20% − 80%) Q, Q fin ≤ 4.0GHz fin ≤ 4GHz fin ≤ 4Gb/s 150 70 40 fin ≤ 3.0GHz fin ≤ 3.5 GHz fin ≤ 4.0 GHz D to Q Min 230 190 150 175 Typ 380 320 270 225 5.0 3.0 50 0.2 40 2800 120 mV ps 325 15 15 80 60 0.5 Max Unit mV tPD tSKEW ps ps tDC tJITTER % ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. http://onsemi.com 5 NB6L11M VTD 50 W D VCC RC RC I D 50 W VTD Figure 3. Input Structure VIH Vth VIL D VCC Vthmax VIHmax VILmax Vth D Vth Vthmin VEE VIH Vth VIL VIHmin VILmin Figure 4. Differential Input Driven Single−Ended Figure 5. Vth Diagram D D D D VID = |VIHD(D) − VILD(D)| VIHD VILD Figure 6. Differential Inputs Driven Differentially Figure 7. Differential Inputs Driven Differentially VCC VIHD(MAX) D VILD(MAX) D VIHD VID = VIHD − VILD VILD Q VIHD(MIN) VINPP = VIH(D) − VIL(D) VCMR Q VOUTPP = VOH(Q) − VOL(Q) tPD tPD GND VIL(MIN) Figure 8. VCMR Diagram Figure 9. AC Reference Measurement http://onsemi.com 6 NB6L11M VCC VCC VCC VCC ZO = 50 W D VTD NB6L11M 50 W ZO = 50 W IN NB6L11M 50 W* 50 W* LVPECL Driver ZO = 50 W LVDS Driver 50 W D VT ZO = 50 W VT VTD VT = VT = VCC − 2 V VEE VEE GND VT = VT IN GND Figure 10. LVPECL Interface Figure 11. LVDS Interface VCC VCC ZO = 50 W IN NB6L11M 50 W* 50 W* CML Driver VCC ZO = 50 W VT = VT = VCC VT VT IN GND GND Figure 12. Standard 50 W Load CML Interface VCC VCC VCC VCC ZO = 50 W IN NB6L11M 50 W* Single−Ended Driver 50 W* ZO = 50 W IN NB6L11M 50 W* 50 W* Differential Driver VCC ZO = 50 W VT VT VCC VT VT IN VT = VT = External VREFAC GND GND GND IN VT = VT = External VREFAC GND Figure 13. Capacitor−Coupled Differential Interface (VT/VT Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) *VREFAC bypassed to ground with a 0.01 mF capacitor Figure 14. Capacitor−Coupled Single−Ended Interface (VT/VT Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) http://onsemi.com 7 NB6L11M VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) VCC 800 700 600 500 400 300 200 100 0 0 1 2 3 4 16 mA VEE 50 W 50 W Q Q fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) Figure 16. CML Output Structure VCC 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 17. Typical CML Termination for Output Driver and Device Evaluation ORDERING INFORMATION Device NB6L11MMNG NB6L11MMNR2G Package QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping † 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB6L11M PACKAGE DIMENSIONS D A B 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 PIN 1 LOCATION 0.15 C 0.15 C 0.10 C TOP VIEW 16 X 0.08 C SIDE VIEW A1 C 16X L 5 NOTE 5 4 16X K 1 12 16X b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. ÇÇ ÇÇ (A3) D2 e 8 9 16 13 E A SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L SOLDERING FOOTPRINT* EXPOSED PAD 0.575 0.022 E2 e 3.25 0.128 0.30 0.012 EXPOSED PAD 3.25 0.128 1.50 0.059 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 NB6L11M/D