NB6L611MNR2G

NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer Multi−Level Inputs with Internal Termination http://onsemi.com Description The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. T h e V R E FA C r e f e r e n c e o u t p u t c a n b e u s e d t o r e b i a s capacitor−coupled differential or single−ended input signals. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L611 is a member of the ECLinPS MAX™ family of high performance clock and data management products. Features • • • • • • • • • • • • Input Clock Frequency > 4.0 GHz 280 ps Typical Propagation Delay 100 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter Differential LVPECL Outputs, 780 mV Amplitude, typical LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Voltage Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 4 1 MARKING DIAGRAM* 1 QFN−16 MN SUFFIX CASE 485G 1 16 NB6L 611 ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 VTD Q0 D D Q1 VTD VREFAC Q1 Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Publication Order Number: NB6L611/D NB6L611 VCC 16 VTD 1 D 2 VEE VEE VCC 15 13 14 Exposed Pad (EP) 12 Q0 11 Q0 NB6L611 D 3 10 Q1 VTD 4 9 Q1 5 6 7 VCC VREFAC VEE 8 VCC Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 VTD − Description 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Note1. Internal 50 W Resistor to Termination Pin, VTD. 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. 4 VTD − Internal 50 W Termination Pin for D input. 5 VCC − Positive Supply Voltage 6 VREFAC Internal 50 W Termination Pin for D input. Output Reference Voltage for direct or capacitor coupled inputs 7 VEE − Negative Supply Voltage 8 VCC − Positive Supply Voltage 9 Q1 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V. 10 Q1 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V. 11 Q0 LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V. 12 Q0 LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC − 2.0 V. 13 VCC − Positive Supply Voltage 14 VEE − Negative Supply Voltage 15 VEE − Negative Supply Voltage 16 VCC − Positive Supply Voltage − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation. 2. All VCC and VEE pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB6L611 Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity 16−QFN Flammability Rating Oxygen Index: 28 to 34 > 2 kV > 200V Level 1 UL 94 V−0 @ 0.125 in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol Positive Power Supply Parameter VEE = 0 V Condition 1 Condition 2 4.0 V VEE Negative Power Supply VCC = 0 V −4.0 V VIO Positive Input/Output Voltage Negative Input/Output Voltage VEE = 0 V VCC = 0 V 4.5 −4.5 V V VINPP Differential Input Voltage |D − D| VCC−VEE V IIN Input Current Through RT (50 W Resistor) Static Surge 45 80 mA mA IOUT Output Current (LVPECL Output) Continuous Surge 50 100 mA mA IVREFAC VREFAC Sink/Source Current 2.0 mA TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) (Note 3) Tsol Wave Solder Pb−Free −0.5  VIo  VCC + 0.5 +0.5  VIo  VEE − 0.5 16 QFN −40 to +85 °C −65 to +150 °C QFN−16 QFN−16 42 35 °C/W °C/W QFN−16 4 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L611 Table 4. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C Characteristic Symbol Min Typ Max Unit 30 45 60 mA VCC = 3.3 V VCC = 2.5 V VCC − 1075 2225 1425 VCC − 950 2350 1550 VCC − 825 2475 1675 mV VCC = 3.3V VCC = 2.5V VCC − 1875 1475 675 VCC − 1725 1575 775 VCC − 1625 1675 875 mV VEE + 1050 VCC − 150 mV POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) LVPECL OUTPUTS (Notes 4 and 5) VOH Output HIGH Voltage VOL Output LOW Voltage DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 9 and 10) (Note 6) Vth Input Threshold Reference Voltage Range (Note 7) VIH Single−ended Input HIGH Voltage Vth + 150 VCC mV VIL Single−ended Input LOW Voltage VEE Vth − 150 mV VISE Single−ended Input Voltage Amplitude (VIH − VIL) 300 VCC−VEE mV VCC – 1.325 mV VREFAC VREFAC Output Reference Voltage (VCC  25 V) VCC – 1.525 VCC – 1.425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 11, 12 and 13) (Note 8) VIHD Differential Input HIGH Voltage VEE + 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC − 150 mV VID Differential Input Voltage (VIHD − VILD) VEE + 150 VCC−VEE mV VCMR Input Common Mode Range (Differential Configuration) (Note9) VEE + 950 VCC − 75 mV IIH Input HIGH Current D/D, (VTD/VTD Open) −150 150 mA IIL Input LOW Current D/D, (VTD/VTD Open) −150 150 mA 60 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor (Measured from D to VTD) 40 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with 50 W to VCC − 2.0 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L611 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C; (Note 10) Characteristic Symbol VOUTPP Output Voltage Amplitude (@ VINPP) (Note 14) (See Figure 3) Min Typ fin ≤ 1.5 GHz fin = 2.0 GHz fin = 3.0 GHz fin = 4.0 GHz 725 520 320 170 780 680 500 400 D to Q 225 280 375 ps 3 15 15 80 ps 50 60 ps 0.2 0.5 ps VCC − VEE mV 170 ps tPD Propagation Delay tSKEW Duty Cycle Skew (Note 11) Within Device Skew Device to Device Skew (Note 12) tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin ≤ 4.0 GHz tJITTER RMS Random Clock Jitter (Note 13) fin ≤ 4.0 GHz VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) tr,tf Output Rise/Fall Times @ 0.5 GHz (20% − 80%) 40 150 Q, Q 100 Max Unit mV VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC − 2.0 V. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Input and output voltage swing is a single−ended measurement operating in differential mode. 800 700 600 500 400 300 200 100 0 0 1 2 3 4 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 3. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) http://onsemi.com 5 NB6L611 Figure 4. Typical Phase Noise Plot at fcarrier = 311.04 MHz Figure 5. Typical Phase Noise Plot at fcarrier = 622.08 MHz Figure 6. Typical Phase Noise Plot at fcarrier = 1 GHz Figure 7. Typical Phase Noise Plot at fcarrier = 2 GHz device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 44 fs, 11 fs, 8 fs and 6 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6L611 device at frequencies 311.04 MHz, 622.08 MHz, 1 GHz and 2 GHz respectively at an operating voltage of 3.3 V in room temperature. The RMS Phase Jitter contributed by the http://onsemi.com 6 NB6L611 VTD VCC 50 W RC RC D I D 50 W VTD Figure 8. Input Structure VCC Vthmax D VIH VIHmax VILmax Vth VIH Vth VIL Vth VIL Vthmin D Vth Figure 10. Vth Diagram D D D D VIHD(MAX) VIHD VILD D VILD(MAX) VINPP = VIH(D) − VIL(D) D VIHD VID = VIHD − VILD Q VILD VOUTPP = VOH(Q) − VOL(Q) Q VIHD(MIN) GND VID = |VIHD(D) − VILD(D)| Figure 12. Differential Inputs Driven Differentially Figure 11. Differential Inputs Driven Differentially VCMR VILmin VEE Figure 9. Differential Input Driven Single−Ended VCC VIHmin tPD tPD VILD(MIN) Figure 13. VCMR Diagram Figure 14. AC Reference Measurement http://onsemi.com 7 NB6L611 VCC VCC VCC NB6L611 ZO = 50 W LVPECL Driver VCC ZO = 50 W D 50 W VT = VCC − 2 V ZO = 50 W LVDS Driver 50 W NB6L611 D 50 W VT = Open ZO = 50 W D 50 W D VEE VEE VEE VEE Figure 15. LVPECL Interface Figure 16. LVDS Interface VCC VCC NB6L611 ZO = 50 W CML Driver D 50 W VT = VCC ZO = 50 W 50 W D VEE VEE Figure 17. Standard 50 W Load CML Interface VCC VCC VCC ZO = 50 W Differential Driver NB6L611 ZO = 50 W D 50 W VT = VREFAC* ZO = 50 W Single−Ended Driver 50 W D VEE VCC Figure 18. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) NB6L611 D 50 W VT = VREFAC* 50 W D VEE VEE *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 8 Figure 19. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) (Open) VEE NB6L611 Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 20. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NB6L611MNG QFN−16 (Pb−free) 123 Units / Rail NB6L611MNR2G QFN−16 (Pb−free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. The products described herein (NB6L611), may be covered by U.S. patents including 6,362,644. There may be other patents pending. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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