NB7L32M

NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Descriptions The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M’s in a system. The differential 16 mA CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated 50 W to VCC (See Figure 16). The device is housed in a small 3x3 mm 16 pin QFN package. Features http://onsemi.com MARKING DIAGRAM* 16 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7L 32M ALYWG • • • • • • • • • Maximum Input Clock Frequency 14 GHz Typical 200 ps Max Propagation Delay 30 ps Typical Rise and Fall Times < 0.5 ps Maximum (RMS) Random Clock Jitter Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak−to−Peak Output), Differential Output Only 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb−Free Devices = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. FUNCTIONAL BLOCK DIAGRAM R VCC VEE R1 VTCLK 50 W CLK CLK 50 W VTCLK Divide by 2 Reset Q Q TRUTH TABLE CLK x Z CLK x W R H L Q L ÷2 Q H ÷2 Z = LOW to HIGH Transition W = HIGH to LOW Transition x = Don’t Care ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2005 November, 2005 − Rev. 0 1 Publication Order Number: NB7L32M/D NB7L32M VCC 16 VTCLK CLK CLK VTCLK 1 2 NB7L32M 3 4 5 NC 6 VEE 7 VEE 8 VEE 10 9 Q VCC R 15 VCC VCC 14 13 12 11 VCC Q Exposed Pad (EP) Figure 1. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin 1 Name VTCLK I/O − Description Internal 50 W termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input then the device will be susceptible to self−oscillation. Noninverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Inverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Internal 50 W termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. No connect. NC pin must be left open. Negative supply voltage. Positive supply voltage. Inverted differential output. Typically terminated with 50 W resistor to VCC. Noninverted differential output. Typically terminated with 50 W resistor to VCC. Reset Input. Internal pulldown to 75 kW to VEE. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. EP is electrically isolated from VCC and VEE. 2 CLK ECL, CML, LVDS Input 3 CLK ECL, CML, LVDS Input 4 VTCLK − 5 6, 7, 8 9, 12, 13, 14, 16 10 11 15 − NC VEE VCC Q Q R EP − − − CML Output CML Output LVTTL/LVCMOS − http://onsemi.com 2 NB7L32M Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. R1 Human Body Model Machine Model QFN−16 Oxygen Index: 28 to 34 Value 75 kW > 500 V > 30 V Level 1 UL 94 V−0 @ 0.125 in 349 Table 3. MAXIMUM RATINGS Symbol VCC VEE VI VINPP IIN Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 2) Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free 0 lfpm 500 lfpm 1S2P VIL VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHDmin VILDmin Vth D Vthmin GND Figure 12. Vth Diagram Figure 13. VCMR Diagram VCC 50 W 50 W Q Q 16 mA VEE Figure 14. CML Output Structure http://onsemi.com 8 NB7L32M APPLICATION INFORMATION All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D. Table 5. INTERFACING OPTIONS Interfacing Options CML LVDS AC−COUPLED RSECL, PECL, NECL Connections Connect VTD and VTD to VCC (See Figure 15) Connect VTD and VTD Together (See Figure 17) Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 16) Standard ECL Termination Techniques (See Figure 9) VCC VCC 50 W 50 W Q Z = 50 W VCC Z = 50 W VCC D VTD VTD D VEE 50 W 50 W NB7L32M CML Driver Q VEE Figure 15. CML to NB7L32M Interface VCC VCC Z = 50 W C D VTD VTD D 50 W NB7L32M 50 W PECL Driver Recommended RT Values VCC RT RT VEE VEE RT 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W Z = 50 W VBias* VBias* C VEE *VBias must be within common mode range limits (VCMR) Figure 16. PECL to NB7L32M Interface http://onsemi.com 9 NB7L32M APPLICATION INFORMATION VCC VCC Z = 50 W LVDS Driver Z = 50 W D VTD VTD D 50 W NB7L32M 50 W VEE VEE Figure 17. LVDS to NB7L32M Interface ORDERING INFORMATION Device NB7L32MMNG NB7L32MMNR2G Package QFN−16 (Pb−Free) QFN−16 (Pb−Free) Shipping † 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NB7L32M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G−01 ISSUE B D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50 PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW (A3) SIDE VIEW D2 5 E A A1 C e 8 EXPOSED PAD 9 E2 12 e b BOTTOM VIEW http://onsemi.com 11 NB7L32M/D