NB7NPQ701MMTTBG

NB7NPQ701M 3.3 V USB 3.1 Single Channel Re-driver Description The NB7NPQ701M is a 3.3 V single channel re−driver for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications that supports both 5 Gbps and 10 Gbps data rates. Signal integrity degrades from PCB traces, transmission cables, and inter−symbol interference (ISI). The NB7NPQ701M compensates for these losses by engaging varying levels of equalization at the input receiver and de−emphasis on output driver. The output transmitter circuitry provides user selectable de−emphasis and output amplitude settings to create the best eye openings for the outgoing data signals. The NB7NPQ701M features an intelligent LFPS circuit. This circuit senses the low frequency signals and automatically disables driver de−emphasis for full USB 3.1 Gen 1 and USB 3.1 Gen 2 compliances. After power up, the NB7NPQ701M periodically checks both of the TX output pairs for a receiver connection. When the receiver is detected the RX termination becomes enabled and the NB7NPQ701M is set to perform the re−driver function. The NB7NPQ701M comes in a small, 2 x 2 mm WDFN8 package and is specified to operate across the entire industrial temperature range, –40°C to 85°C. Features • • • • • • • • • • • 3.3 V ± 5% Power Supply Device Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates Automatic LFPS De−Emphasis Control Automatic Receiver Termination Detection Integrated Input and Output Termination Selectable Equalization, De−Emphasis, and Output Swing Hot−Plug Capable ESD Protection ±4 kV HBM Operating Temperature Range: –40°C to 85°C Small 2 x 2 x 0.8 mm WDFN8 Package This is a Pb−Free Device www.onsemi.com MARKING DIAGRAM 1 1 NP MG G WDFN8, 2x2 CASE 511BE NP = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NB7NPQ701MMTTBG WDFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Typical Applications • • • • • Computer and Laptop Docking Station and Dongle Active Cable, Back Planes Gaming Console, Smart T.V. Servers and Storage © Semiconductor Components Industries, LLC, 2017 March, 2017 − Rev. 0 1 Publication Order Number: NB7NPQ701M/D NB7NPQ701M Figure 1. Logic Diagram of NB7NPQ701M Figure 2. WDFN8 Package Pinout (Top View) Table 1. PIN DESCRIPTION Pin Number Pin Name Type 1 VCC Power 2 RX+ DIFF IN 3 RX- 4 OS LVCMOS IN Sets output swing on the TX. The 3−state input with integrated 250 kW pull−up and pull−down resistors. 5 EQ LVCMOS IN Sets the receiver equalizer gain. The 3−state input with integrated 250 kW pull−up and pull−down resistors. 6 TX- 7 TX+ 8 DE EP GND DIFF OUT Description 3.3 V power supply Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled. Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled. LVCMOS IN Sets the output de−emphasis gain. The 3−state input with integrated 250 kW pull−up and pull−down resistors. GND Exposed Pad (EP) on the package bottom is thermally and electronically connected to the die. The exposed pad must electrically connected to GND. www.onsemi.com 2 NB7NPQ701M DEVICE CONFIGURATION Table 2. CONTROL PIN EFFECTS (Typical Values) Pin Description Logic State Equalization Gain EQ Equalization Amount Low 3 dB Mid 6 dB High 9 dB De−emphasis Ratio (Note 1) Pin Description Logic State OS = LOW OS = Float OS = High DE De−Emphasis Amount Low 0 dB −4.5 dB −6.5 dB Mid −4 dB −6 dB −7.5 dB High −6 dB −7.5 dB −8 dB Pin Description Logic State Output Swing OS Output Swing with DE Pin Low (0 dB) Low 850 mVPP Mid 1050 mVPP High 1200 mVPP 1. dB Decrease = 20 log * (VTX−DE / VTX−DIFF−PP) Table 3. ATTRIBUTES Parameter ESD Protection > 4 kV > 1.5 kV Human Body Model Charged Device Model Level 1 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Flammability Rating Oxygen Index: 28 to 34 UL 94 V−O @ 0.125 in 703 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted) Description Parameter Min Max Unit Supply Voltage (Note 3) VCC −0.5 4.6 V Voltage range at any input or output terminal Differential I/O −0.5 1.89 V LVCMOS inputs −0.5 VCC + 0.5 V −65 150 °C 125 °C 85 °C Junction−to−Ambient Thermal Resistance @ 500 lfm, qJA (Note 4) 62 °C/W Wave Solder, Pb−Free, TSOL 265 °C Storage Temperature Range, TSG Maximum Junction Temperature, TJ Operating Ambient Temperature Range, TA −40 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. All voltage values are with respect to the GND terminals. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). www.onsemi.com 3 NB7NPQ701M Table 5. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted) Description Parameter Main power supply VCC TA CAC Min Nom Max Unit 3.135 3.3 3.465 V +85 °C 265 nF Operating free−air temperature −40 AC coupling capacitor 75 100 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 6. POWER SUPPLY CHARACTERISTICS Parameter Test Conditions Min Typ (Note 5) Max Unit Active Link in U0 with SS data transmission DE = low 0 dB, EQ = low 3 dB, OS = low 70 mA Idle State Link has some activity, not in U0 DE = mid −4 dB, EQ = mid 6dB OS = low 50 mA U2/U3 Link in U2 or U3 power saving state DE = mid −4 dB, EQ = mid 6 dB, OS = low 6.7 mA No USB Connection No connection state, termination disabled DE = mid −4 dB, EQ = mid 6 dB, OS = low 6.7 mA ICC 5. TYP values use VCC = 3.3 V, TA = 25°C. Table 7. LVCMOS CONTROL PIN CHARACTERISTICS Parameter Test Conditions Min Typ Max Unit VCC V 3−State LVCMOS Inputs (EQ, DE, OS) VIH High−level input voltage 0.8 * VCC VIM Mid−level input voltage 0.4 * VCC VCC / 2 0.6 * VCC V VIL Low−level input voltage 0.2 * VCC V VF Floating voltage GND VIN = High impedance VCC / 2 V RPU Internal pull−up resistance 250 kW RPD Internal pull−down resistance 250 kW IIH High−level input current VIN = 1.89 V IIL Low−level input current VIN = GND, VCC = 3.3 V www.onsemi.com 4 20 −20 mA mA NB7NPQ701M Table 8. RECEIVER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted) Parameter VRX−DIFF−pp VRX−CM Input differential voltage swing Test Conditions AC−coupled, peak−to−peak Min Typ 250 Max Unit 1200 mVPP VCC− 0.25 Common−mode voltage bias in the receiver (DC) V Differential input impedance (DC) Present after an USB device is detected on TX+/TX− 80 100 120 W Common−mode input impedance (DC) Present after an USB device is detected on TX+/TX− 20 25 30 W ZRX−HIGH−IMP Common−mode input impedance with termination disabled (DC) Present when no USB device is detected on TX+ 25 35 VTH−LFPS−pp Low Frequency Periodic Signaling (LFPS) Detect Threshold Output voltage is considered squelched below this threshold voltage. ZRX−DIFF ZRX−CM kW 300 mVPP Table 9. TRANSMITTER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted) Parameter Test Conditions Min Typ OS = Low, 50 W to VCC 850 OS = Mid, 50 W to VCC 1050 OS = High, 50 W to VCC 1200 TX input capacitance to GND At 2.5 GHz 1.25 Differential output impedance (DC) Present after an USB device is detected on TX+/TX− 80 ZTX−CM Common−mode output impedance (DC) Present after an USB device is detected on TX+/TX− 20 ITX−SC TX short circuit current VTX−CM Common−mode voltage bias in the transmitter (DC) VTX−DIFF−PP CTX ZTX−DIFF VTX−CM−ACpp Output differential voltage swing at 5 Gbps, 10 Gbps with DE low VCC−0.5 AC common−mode peak−to−peak volt- Within U0 and within LFPS age swing in active mode Differential voltage swing during electrical idle Tested with a high−pass filter VTX−RXDET Voltage change to allow receiver detect Positive voltage to sense receiver termination Output rise, fall time 20% − 80% of differential voltage measured 1 inch from the output pin Output rise, Fall time mismatch 20% − 80% of differential voltage measured 1 inch from the output pin Differential propagation delay De−emphasis = −4 dB, OS = Low propagation delay between 50% level at input and output tRF−MM tdiff−LH, tdiff−HL tidleEntry, tidleExit Idle entry and exit times www.onsemi.com 5 0 Unit mVPP pF 120 W 30 W 60 TX+ or TX− shorted to GND VTX−IDLE−DIFF− ACpp tR, tF 100 Max mA VCC V 100 mVPP 10 mVPP 600 mV 45 ps 5 ps 150 ps 30 ns NB7NPQ701M Table 10. TIMING AND JITTER CHARACTERISTICS Parameter Test Conditions Min Typ Max Unit TIMING tREADY Time from power applied until RX termi- Apply 0 V to VCC, connect USB termination to TX±, apply 3.3 V to nation is enabled VCC, and measure when ZRX−DIFF is enabled 10 ms 0.076 UI (Note 8) 0.046 UI (Note 8) 0.004 UI (Note 8) 0.053 UI (Note 8) 0.008 UI (Note 8) 0.001 UI (Note 8) JITTER FOR 5 Gbps TJTX−EYE Total jitter (Notes 6, 7) DJTX Deterministic jitter (Note 7) RJTX Random jitter (Note 7) EQ = Mid 6 dB, DE = High −6 dB, OS = Low JITTER FOR 10 Gbps TJTX−EYE Total jitter (Notes 6, 7) DJTX Deterministic jitter (Note 7) RJTX Random jitter (Note 7) EQ = Mid 6dB, DE = High −6 dB, OS = Low 6. Includes RJ at 10−12. 7. Measured at the ends of reference channel with a K28.5 pattern, VID = 1000 mVpp, −3.5 dB de−emphasis from source. 8. 5 Gbps, UI = 200 ps for 10 Gbps, UI = 100 ps. www.onsemi.com 6 NB7NPQ701M Pattern Gen. Oscilloscope TP1 50 W X” FR−4 RX TX DUT Soldered TP2 Figure 3. Equalization Measurement Setup Figure 4. 5 Gbps Signal with 24 inches of FR4 Before Input (Figure 3 TP1) to NB7NPQ701M and After (Figure 3 TP2) Using High EQ Setting Figure 5. 10 Gbps Signal with 12 inches of FR4 Before Input (Figure 3 TP1) to NB7NPQ701M and After (Figure 3 TP2) with EQ Floating (Mid) www.onsemi.com 7 NB7NPQ701M Pattern Gen. Oscilloscope 50 W TX RX X” FR−4 DUT Soldered TP3 Figure 6. De−Emphasis Measurement Setup Figure 7. 5 Gbps Signal After 24 inches of FR4 (No DUT) Figure 8. 5 Gbps Signal After 24 inches of FR4 at Output (Figure 6 TP3) with Mid DE Setting to NB7NPQ701M Figure 9. 10 Gbps Signal After 12 inches of FR4 (No DUT) Figure 10. 10 Gbps Signal After 12 inches of FR4 at Output (Figure 6 TP3) with Low DE Setting to NB7NPQ701M www.onsemi.com 8 NB7NPQ701M PARAMETER MEASUREMENT DIAGRAMS Rx− Rx+ Tx− Tx+ Figure 11. Transmitter Differential Voltage dB Decrease = 20 log * (VTX−DE / VTX−DIFF−PP) Figure 12. Propagation Delay VOH VOL Figure 13. Output Rise and Fall Times APPLICATION GUIDELINES LFPS Compliance Testing between host and peripheral devices. LFPS signaling consists of bursts of frequencies ranging between 10 to 50 MHz and can have specific burst lengths or repeat rates. As part of USB 3.1 compliance test, the host or peripheral must transmit a LFPS signal that adheres to the spec parameters. When using a real−time oscilloscope to capture this data, the scope’s trigger must be below 0 V when making single−ended measurements. Although the differential signal is identical to that which is expected by the USB 3.1 system, the AC common mode voltage for LFPS may fall below 0 V during short bursts of switching signal, which is still within the spec’s limit. Ping.LFPS for TX Compliance During the transmitter compliance, the system under test must transmit certain compliance patterns as defined by the USB−IF. In order to toggle through these patterns for various tests, the receiver must receive a ping. LFPS signal from either the test suite or a separate pattern generator. The standard signal comprises of a single burst period of 100ns at 20 MHz. In order to pass this signal through NB7NPQ701M, the duration of the burst must be extended to at least 200 ns. LFPS Functionality USB 3.1 links use Low Frequency Periodic Signaling (LFPS) to implement functions like exiting low−power modes, performing warm resets and providing link training www.onsemi.com 9 NB7NPQ701M PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511BE ISSUE A A D 0.10 C 2X 0.10 C 2X L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 ÇÇ ÇÇ PIN ONE REFERENCE L B E DETAIL A ALTERNATE CONSTRUCTIONS TOP VIEW ÇÇ ÇÇ ÉÉ EXPOSED Cu DETAIL B A 0.10 C A3 ÉÉ ÉÉ ÇÇ DIM A A1 A3 b D D2 E E2 e K L L1 A3 MOLD CMPD A1 DETAIL B ALTERNATE CONSTRUCTIONS 0.08 C A1 SIDE VIEW NOTE 4 C SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* D2 DETAIL A 8X 1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.50 1.70 2.00 BSC 0.80 1.00 0.50 BSC 0.25 REF 0.20 0.40 −−− 0.15 L 4 8X 1.70 PACKAGE OUTLINE 0.50 E2 K 8 5 e BOTTOM VIEW 8X 2.30 1.00 b 0.10 C A B 0.05 C NOTE 3 1 0.50 PITCH 8X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and solderin details, please download the ON Semiconductor Soldering an Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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