NB7VPQ16M

NB7VPQ16M 1.8V/2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver Multi−Level Inputs w/ Internal Termination Description http://onsemi.com MARKING DIAGRAM* 16 1 The NB7VPQ16M is a h igh performance s ingle channel programmable Pre−Emphasis CML Driver with a selectable Equalizer Receiver that operates up to 14 Gbps typical with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, the NB7VPQ16M inputs will compensate the degraded signal transmitted across a FR4 PCB backplane or cable interconnect. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The Pre−Emphasis buffer is controlled using a serial bus via the Serial Data In (SDIN) and Serial Clock In (SCLKIN) control inputs and contains circuitry which provides sixteen programmable Pre−Emphasis settings to select the optimal output compensation level. These selectable output levels will handle various backplane lengths and cable lines. The first four SDIN bits (D3:D0) will digitally select 0 dB through 12 dB typical of de−emphasis (see Table 1). For cascaded applications, the shifted SDIN and SCLKIN signals are presented at the SDOUT and SCLKOUT pins. The 5th−bit (LSB) of the serial data bits allows for enabling the equalization function of the receiver. The differential Data / Clock inputs incorporate a pair of internal 50 W termination resistors, in a 100 W center−tapped configuration, via the VT pin and will accept LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on−chip, at the receiver end, eliminating external components. The NB7VPQ16M is a member of the GigaComm™ Family of high performance Data/Clock products with Pre−Emphasis/Equalization (PEEQ). Features 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7V PQ16M ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SDOUT SDI SCLKOUT DAC Q IN EQ PE Q IN VT SDIN SCLKIN SLOAD Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. • • • • • • Maximum Input Data Rate > 12.5 Gbps Maximum Input Clock Frequency > 8 GHz Drives Up To 18−inches of FR4 (16) Programmable Output De−emphasis Levels; 0 dB through 12 dB 200 ps Typical Propagation Delay Differential CML Outputs, 400 mV Peak−to−Peak, Typical (PE = 0 dB) • • • • • Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V Internal Output Termination Resistors, 50 W QFN−16 Package, 3 mm x 3 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 0 1 Publication Order Number: NB7VPQ16M/D NB7VPQ16M (15) SDIN (14) SCLKIN VCCD VCC GND Multi−Level Inputs LVPECL, LVDS, CML (2) IN (1) VT (3) IN 5−Bit Shift Register EQEN D0 D1 D2 D3 SDOUT (6) SCLKOUT (7) (13) SLOAD D/A Latch EQEN (EQualizer ENable) 4−Bit DAC Q (11) Q (10) CML Output 50W 50W EQ 0 2:1 MUX 1 Pre−Emphasis Control Figure 2. Detailed Block Diagram of NB7VPQ16M Q Low Q High Bit n −1 Q High Q Low Bit n Q High Q Low Bit n+1 Q Low Q High Bit n+2 PE = 0dB PE = −12dB Q 20% 80% 0V VOD0dB VODPE Q tPE X130ps PE = 20log(VODPE/VOD0dB) VOD0dB − Differential Output Voltage without Pre−Emphasis VODPE − Differential Output Voltage with Pre−Emphasis Figure 3. Illustration of Output Waveform Definition http://onsemi.com 2 NB7VPQ16M Table 1. TYPICAL PRE−EMPHASIS CONTROL TABLE, EQ = 0, 255C, VCC = 1.8 V 4−bit PE MSB Decimal 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PE Output Compensation in dB Approximate @ 1 GHz 0 dB (Default) −1.0 dB −1.5 dB −2.0 dB −2.5 dB −3.0 dB −3.5 dB −4.0 dB −4.5 dB −5.0 dB −6.0 dB −7.0 dB −8.0 dB −9.0 dB −10.0 dB −12.0 dB VODPE Typ (mV) 435 390 365 345 325 310 290 275 260 245 220 195 175 155 135 110 Table 2. EQUALIZER ENABLE FUNCTION EQEN 0 1 Function IN/IN Inputs By−pass the Equalizer section Inputs flow through the Equalizer http://onsemi.com 3 NB7VPQ16M SCLKIN SLOAD SDIN VCC Exposed Pad (EP) 16 VT IN IN GND 1 2 15 14 13 12 VCC 11 Q 10 Q 9 VCC NB7VPQ16M 3 4 5 VCCD 6 SDOUT 7 SCLKOUT 8 GND Figure 4. Pin Configuration (Top View) Table 3. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Name VT IN IN GND VCCD SDOUT SCLKOUT GND VCC Q Q VCC SLOAD LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − LVCMOS Output LVCMOS Output − − CML CML − LVCMOS Input I/O Description Internal 50−W Termination Pin for IN and IN Non−inverted Differential Clock/Data Input. (Note 1) Inverted Differential Clock/Data Input. (Note 1) Negative Supply Voltage; (Note 2) Positive Supply Voltage for Serial Bus Logic and 5−Bit DAC; (Note 2) Serial Data Out Serial Clock Out Negative Supply Voltage; (Note 2) Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2) Inverted Differential Output. (Note 1) Non−inverted Differential Output. (Note 1) Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2) When the SLOAD pin is LOW or left open (has internal pulldown resistor), the output of the shift register will input the 4−bit DAC and set the EQEN bit. When HIGH, the input to the 4−bit DAC is locked to the state prior to when SLOAD went HIGH. Serial Clock In; pin will default LOW when left open (has internal pulldown resistor) Serial Data In; pin will default LOW when left open (has internal pulldown resistor) Positive Supply Voltage for the analog circuitry and CML Output buffer; (Note 2) The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is also electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 14 15 16 SCLKIN SDIN VCC EP LVCMOS Input LVCMOS Input − 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no input signal is applied on IN/IN input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source termination resistor. 2. All VCC, VCCD and GND pins must be externally connected to a power supply voltage to guarantee proper device operation. http://onsemi.com 4 NB7VPQ16M Table 4. ATTRIBUTES Characteristics ESD Protection Internal Input Pulldown Resistor Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 4 kV > 200 V 75 kW Level 1 UL 94 V−0 @ 0.125 in 416 Table 5. MAXIMUM RATINGS Symbol VCC, VCCD VIN VINPP Iout IIN TA Tstg qJA qJC Tsol Positive Power Supply Positive Input Voltage Differential Input Voltage |IN − IN| Output Current Input Current Through RT (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free 0 lfpm 500 lfpm Standard Board QFN−16 QFN−16 QFN−16 Continuous Surge Parameter Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 3.0 −0.5 to VCC +0.5 1.89 34 40 $40 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA mA °C °C °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 5 NB7VPQ16M Table 6. DC CHARACTERISTICS POSITIVE CML OUTPUT VCC = VCCD = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C Symbol POWER SUPPLY CURRENT ICC ICCD Power Supply Current, (Inputs and Outputs Open) PE = 0dB Power Supply Current for Serial Bus and DAC (Inputs and Outputs Open) VCC = 2.5 V VCC = 1.8 V PE = 0000 = 0dB PE = 1111 = Max 95 80 0 10 120 100 20 mA mA Characteristic Min Typ Max Unit (Note 5) CML OUTPUTS PE = 0dB (Note 6, Figure 22) VOH Output HIGH Voltage VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC – 30 2470 1770 VCC – 600 1900 VCC – 550 1250 VCC – 10 2490 1790 VCC – 500 2000 VCC – 450 1350 VCC 2500 1800 VCC – 400 2100 VCC – 350 1450 mV VOL Output LOW Voltage mV VCC = 1.8 V DATA/CLOCK INPUTS (IN, IN) (Note 7) (Figure 6) VIHD VILD VID IIH IIL VIH VIL IIH IIL VOH VOL RTIN RTOUT Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input HIGH Current Input LOW Current 1100 GND 100 −150 −150 20 5 VCC VCC − 100 1200 150 150 mV mV mV mA mA CONTROL INPUTS (SDIN, SCLKIN, SLOAD) Input HIGH Voltage for Control Pins Input LOW Voltage for Control Pins Input HIGH Current Input LOW Current VCCD x 0.65 GND −150 −150 20 5 VCCD VCCD x 0.35 150 150 mV mV mA mA CONTROL OUTPUTS (SDOUT, SCLKOUT) Output HIGH Voltage Output LOW Voltage VCC − 200 GND VCC 200 mV mV TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 45 45 50 50 55 55 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 6 NB7VPQ16M Table 7. AC CHARACTERISTICS VCC = VCCD = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 8) Symbol fDATAMAX fMAX fSCLKIN VOD0dB Maximum Input Data Rate Maximum Input Clock Frequency (Note 9) Serial Clock Input Frequency Output Voltage Amplitude (see Table 1) (@ VINPPmin) (See Figure 3, Note 9) Pre−Emphasis Width, tested at −12dB Pre−Emphasis Input Common Mode Range (Differential Configuration, Note 10) (Figure 8) Propagation Delay to Differential Outputs, 1 GHz, measured at differential cross−point IN/IN to Q/Q SCLKIN to SCLKOUT fin v 5.0 GHz 1050 150 45 5 5 10 1 2 6 0.1 0.8 10 10 100 35 1200 50 200 5 50 fin v 6.0 GHz fin v 8.0 GHz 300 200 400 300 130 VCC 250 10 55 VOUTPP w 200 mV Characteristic Min 12.5 8 20 Typ 14 Max Unit Gbps GHz MHz mV tPE VCMR tPLH, tPHL tDC ts1 ts2 ts3 th1 th2 th3 tPW_SLOAD tJITTER ps mV ps ns % ns Output Clock Duty Cycle (Reference Duty Cycle = 50%) Setup Time @ 50 MHz (Figures 9 and 10) SDIN to SCLKIN SCLKIN to SLOAD SLOAD to IN/IN SDIN to SCLKIN SCLKIN to SLOAD Hold Time @ 50 MHz (Figures 9 and 10) ns SLOAD Minimum Pulse Width (Figure 10) RJ – Output Random Jitter (Note 11) fin v 8.0 GHz DJ − Residual Output Deterministic Jitter (Note 12) (EQ = 0, PE = 0 dB) FR4 v 3”, f v 12.5 Gbps (Figures 15 and 16) FR4 = 12”, f v 6.5 Gbps Input Voltage Swing (Differential Configuration) (Note 9) Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q ns ps rms ps pk−pk mV ps VINPP tr, tf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 400 mV source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps. (20% − 80%); PE = 0 dB, EQEN = 0 9. Input / Output voltage swing is a single−ended measurement operating in differential mode. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 11. Additive RMS jitter with 50% duty cycle Clock signal. 12. Peak−to−Peak jitter with input NRZ data at PRBS23. VCC IN 50 W VT 50 W IN Figure 5. Input Structure http://onsemi.com 7 NB7VPQ16M IN IN Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL VINPP = VIH(IN) − VIL(IN) IN IN VID = |VIHD(IN) − VILD(IN)| VIHD VILD Figure 6. Differential Inputs Driven Differentially Figure 7. AC Reference Measurement VCC VCMmax IN VCMR IN VCMmin GND VIHDmax VILDmax VINPP VIHDtyp VILDtyp VIHDmin VILDmin Figure 8. VCMR Diagram SDIN tS1 SCLKIN tH1 SCLKIN tS2 SLOAD tPWmin tH2 Figure 9. SDIN/SCLKIN Setup and Hold Time Figure 10. SLOAD Set−Up and Hold and tPWmin http://onsemi.com 8 NB7VPQ16M APPLICATION INFORMATION Data Inputs SDIN / SCLKIN The differential IN/IN inputs of the NB7VPQ16M can accept LVPECL, CML, and LVDS signal levels. The limitations for a differential input signal (LVDS, LVPECL, or CML) is a minimum input swing of 100 mV (single−ended measurement). Within this condition, the input HIGH voltage, VIH, can range from VCC down to 1.1 V. Example interfaces are illustrated in Figure 17. Serial Data Interface SDIN is the Serial Data input pin; SCLKIN is the Serial Clock input pin. SLOAD The Serial Data Interface (SDI) logic is implemented with a 5−bit shift register scheme. The register shifts once per rising edge of the SCLKIN input. The serial data input SDIN must meet setup and hold timing as specified in the AC table. The configuration latches will capture the value of the shift register on the Low−to−High edge of the SLOAD input. The most significant bit (MSB) is loaded first. See the programming timing diagram for more information. The SLOAD pin performs the DAC latch function. When LOW or left open, the DAC latch will pass the shift register outputs to the input of the DAC and the EQualizer ENable bit (EQEN). On the Low−to−HIGH transition of SLOAD, the input to the 4−bit DAC is locked to the state prior to when SLOAD went HIGH, and will set the EQualizer ENable bit. The DAC does not get programmed until SLOAD goes HIGH. The SLOAD pin must remain in a HIGH state to maintain the DAC Pre−Emphasis and the EQEN settings. A LOW or open state resets the DAC to 0 db Pre−Emphasis setting and disables the EQEN bit, regardless of SDIN and SCLKIN values. The SLOAD function is asynchronous. SDIN D3 D2 D1 D0 EQEN ///// ///// ///// ///// ///// ///// ///// SCLKIN SLOAD 1 2 3 4 tPWMIN 5 6 7 8 9 10 11 12 5 Clock SDOUT ///// 1 ///// 2 ///// 3 ///// 4 D3 SCLKIN to SDOUT D2 5 6 D1 7 D0 8 EQEN 9 ///// 10 ///// 11 ///// SCLKOUT Figure 11. Timing Diagram for Single Channel Pre−Emphasis Selection Q/Q Outputs The Pre−Emphasis buffer is controlled using a serial bus via the SDIN (Serial Data In) and SCLKIN (Serial Clock In) control inputs and contains circuitry which provides sixteen programmable pre−emphasis levels to control the output compensation. The 4−bits (D3:D0) digitally select 0 dB through 12 dB of Pre−Emphasis compensation (see Table 1). The default state at start−up is PE = 0 dB. EQualization ENable (EQEN) The differential outputs of the NB7VPQ16M, Q and Q, utilize Common Mode Logic (CML) architecture. The outputs are designed to drive differential transmission lines with nominal 50 W characteristic impedance. External termination with a 50 W resistor to VCC is recommended. See Figures 22 and 23 for output termination scheme. Alternatively, 100 W line−to−line termination is also acceptable. Power Supply Bypass information The EQualizer ENable (EQEN) allows for enabling the Equalizer function. The control of the Equalizer function is realized by setting the 5th bit, EQEN, of the 5−bit serial data. When EQEN is set Low (or open), the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at start−up is EQEN = LOW. A clean power supply will optimize the performance of the NB7VPQ16M. The device provides separate VCCD and VCC power supply pins for the digital circuitry and CML outputs. Placing a 0.01 mF to 0.1 mF bypass capacitor on each VCC and VCCD Pin to ground will help ensure a noise free power supply. The purpose of this design technique is to isolate the CMOS digital switching noise from the high speed input/output path. http://onsemi.com 9 NB7VPQ16M CASCADE APPLICATION SDOUT/SCLKOUT SDOUT is the Serial Data output pin; SCLKOUT is the Serial Clock output pin. These pins are the outputs of the 5−bit SDI shift register and will produce the SDIN/SCLKIN signals after five serial clock cycles, see Figure 12. The purpose of SDOUT and SCLKOUT is for use in cascade applications, described below. D3 D2 D1 D0 EQEN SDIN DUTA SDOUT D3 D2 D1 D0 EQEN DUTB SDIN SDOUT 1 2 3 4 5 SCLKIN SCLKOUT 5 6 7 8 9 SCLKIN SCLKOUT 5 Clocks Figure 12. Simplified Cascaded Serial Data/Clock Timing Diagram Cascaded Applications The NB7VPQ16M can be cascaded with multiple NB7VPQ16Ms in series for various Equalizer/Pre−Emphasis applications, as shown in Figure 13. Serial Data In, SDINA, is clocked with SCLKINA into the cascaded chain of the Pre−Emphasis and equalizer shift registers, (DUTA, DUTB and DUTC), 5−bits per register. Upon the rising edge of the 5th clock of SCLKINA, the first valid data bit (D3) and 5th clock will exit DUTA from SDOUTA and SCLKOUTA and will be present at SDINB and SCLKINB of DUTB and so on. When SLOAD is brought LOW, the PE shift registers of all devices are enabled and data is written into the NB7VPQ16Ms with the contents of the PE shift registers. When the data transfer is complete, SLOAD is brought HIGH and all NB7VPQ16Ms are updated simultaneously. After the PE control bits are clocked into their appropriate registers, the Low−to−High transition of SLOAD will latch the data bits for the Pre−Emphasis DACs. http://onsemi.com 10 NB7VPQ16M DUTA INA DUTB INB DUTC INC EQA SLOAD Serial Data In Serial Clock In SCLKINA CML SDINA PEA SCLKINB SCLKOUTA SDOUTA SLOAD SDINB EQB SDOUTB PEB SCLKINC SCLKOUTB CML SLOAD SDINC EQC SDOUTC PEC SCLKOUTC CML QA QB QC Figure 13. Simplified Cascaded Logic Diagram DUTC SDIN D3C D2C D1C D0C EQC D3B DUTB D2B D1B D0B EQB D3A DUTA D2A D1A D0A EQA SCLKIN 1 2 3 5 Clocks 4 5 6 7 8 5 Clocks 9 10 11 12 13 5 Clocks 14 15 tPD SCLKIN to SDOUT SDOUT XXXXXXXXXXXXXXXXX D3C D2C DUTC D1C D0C EQC D3B D2B DUTB D1B D0B EQB D3A D2A DUTA D1A D0A EQA SCLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tPD SCLKIN to SCLKOUT XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX SLOAD tPWMin IN IN tS3 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Figure 14. Simplified Cascaded Serial Data/Clock Timing Diagram http://onsemi.com 11 NB7VPQ16M Digital Oscilloscope FR4 = 12” Backplane Signal Generator NB7VPQ16M Equalizer Receiver EQ = 0 and 1 Q 50W Q 50W Signal Generator Output NB7VPQ16M After 12−Inches of FR−4 NB7VPQ16M Output EQ= 0 20 mV/div 28 ps/div 20 mV/div 28 ps/div 65 mV/div 28 ps/div Signal Generator Output NB7VPQ16M After 12−Inches of FR−4 NB7VPQ16M Output EQ = 1 20 mV/div 28 ps/div 20 mV/div 28 ps/div 65 mV/div 28 ps/div Figure 15. Typical NB7VPQ16M Equalizer Application and Interconnect; Eye Diagrams with PRBS23 Pattern at 6 Gbps http://onsemi.com 12 NB7VPQ16M Digital Oscilloscope NB7VPQ16M Pre−emphasis Driver Q Signal Generator FR4 = 12” Backplane 50W Q 50W Signal Generator Output NB7VPQ16M Output After 0−Inches of FR−4 PE = 0 dB NB7VPQ16M Output After 12−Inches of FR−4 PE = 0 dB 20 mV/div 28 ps/div 20 mV/div 28 ps/div 65 mV/div 28 ps/div Signal Generator Output NB7VPQ16M Output After 0−Inches of FR−4 PE = 6 dB NB7VPQ16M Output After 12−Inches of FR−4 PE = 6 dB 20 mV/div 28 ps/div 20 mV/div 28 ps/div 65 mV/div 28 ps/div Figure 16. Typical NB7VPQ16M Pre−Emphasis Application Interconnect; Eye Diagrams with PRBS23 Pattern at 6 Gbps Without and With Pre−Emphasis http://onsemi.com 13 NB7VPQ16M VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W NB7VPQ16M IN 50 W 50 W IN LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB7VPQ16M IN 50 W 50 W IN GND GND GND GND Figure 17. LVPECL Interface Figure 18. LVDS Interface VCC VCC VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB7VPQ16M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W NB7VPQ16M IN 50 W 50 W IN GND GND GND Figure 19. Standard 50 W Load CML Interface Figure 20. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) GND *VREFAC bypassed to ground with a 0.01 mF capacitor VCC VCC ZO = 50 W Single− Ended Driver VT = VREFAC* NB7VPQ16M IN 50 W 50 W IN (open) GND Figure 21. Capacitor−Coupled Single−Ended Interface (VT Connected to External VREFAC) GND http://onsemi.com 14 NB7VPQ16M NB7VPQ16M VCCO Receiver VCC (Receiver) 50 W NB7VPQ16M VCCO 50 W Receiver 50 W 50 W Q Q 50 W 50 W Q 100 W Q 16 mA GND 16 mA GND Figure 22. Typical CML Output Structure and Termination VCC Figure 23. Alternative Output Termination 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W IN Receiver Device IN Figure 24. Typical Termination for CML Output Driver and Device Evaluation ORDERING INFORMATION Device NB7VPQ16MMNG NB7VPQ16MMNTXG Package QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping† 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 15 NB7VPQ16M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D A B L L1 DETAIL A L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG PIN 1 LOCATION 0.15 C 0.15 C TOP VIEW A1 0.10 C DETAIL B (A3) A DETAIL B ALTERNATE CONSTRUCTIONS 16 X 0.08 C SIDE VIEW A1 C SEATING PLANE 16X L DETAIL A 5 4 D2 8 e EXPOSED PAD 9 NOTE 5 0.575 0.022 16X K 1 16 16X 13 E2 12 e 3.25 0.128 b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches 0.10 C A B 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 16 ÇÇ ÉÉ ÉÉ ÉÉ ÉÉ ÇÇÇ ÇÇÇ ÇÇÇ E EXPOSED Cu ALTERNATE TERMINAL CONSTRUCTIONS MOLD CMPD A3 DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 1.50 0.059 NB7VPQ16M/D