NBC12429AFNG

3.3 V/5 V Programmable PLL Synthesized Clock Generator 25 MHz to 400 MHz NBC12429, NBC12429A www.onsemi.com Description The NBC12429 and NBC12429A are general purpose, Phase−Lock−Loop (PLL) based synthesized clock sources. The VCO will operate over a frequency range of 200 MHz to 400 MHz. The VCO frequency is sent to the N−output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 125 kHz, 250 kHz, 500 kHz, or 1.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers. The PLL loop filter is fully integrated and does not require any external components. • • • • • • 1 PLCC−28 FN SUFFIX CASE 776 32 QFN32 MN SUFFIX CASE 488AM LQFP−32 FA SUFFIX CASE 561AB MARKING DIAGRAMS 1 28 Features • • • • 281 Best−in−Class Output Jitter Performance, ±20 ps Peak−to−Peak 25 MHz to 400 MHz Programmable Differential PECL Outputs Fully Integrated Phase−Lock−Loop with Internal Loop Filter Parallel Interface for Programming Counter and Output Dividers During Powerup Minimal Frequency Overshoot Serial 3−Wire Programming Interface Crystal Oscillator Interface Operating Range: VCC = 3.135 V to 5.25 V CMOS and TTL Compatible Control Inputs Pin and Function Compatible with Motorola MC12429 and MPC9229 0°C to 70°C Ambient Operating Temperature (NBC12429) • • −40°C to 85°C Ambient Operating Temperature (NBC12429A) • These Devices are Pb−Free and are RoHS Compliant NBC12429xG AWLYYWW NBC12 429x AWLYYWWG 1 NBC12 429x AWLYYWWG G x = Blank or A A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NBC12429FAG LQFP−32 (Pb−Free) LQFP−32 (Pb−Free) 250 Units / Tube NBC12429FNR2G PLCC−28 (Pb−Free) 500 Units / Tube NBC12429AFNG PLCC−28 (Pb−Free) 37 Units / Tube NBC12429AFNR2G PLCC−28 (Pb−Free) 500 Units / Tube NBC12429AMNR4G QFN−32 (Pb−Free) 1000 / Tape & Reel NBC12429FAR2G 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2009 May, 2021 − Rev. 14 1 Publication Order Number: NBC12429/D NBC12429, NBC12429A B 16 4 10−20 MHz +3.3 or 5.0 V 1 PLL_VCC 1 MHz FREF with 16 MHz Crystal PHASE DETECTOR VCO VCC XTAL1 9−BIT B M COUNTER OSC 5 +3.3 or 5.0 V XTAL2 200−400 MHz 21, 25 24 23 BN (1, 2, 4, 8) FOUT FOUT 20 6 OE LATCH TEST LATCH 28 S_LOAD LATCH 7 P_LOAD 0 27 S_DATA 1 0 1 2−BIT SR 9−BIT SR 3−BIT SR 26 S_CLOCK 17, 18 8 → 16 22, 19 9 2 M[8:0] N[1:0] Figure 1. Block Diagram (PLCC−28) Table 1. OUT DIVISION Table 2. XTAL_SEL and OE N[1:0] Output Division Input 0 1 00 01 10 11 1 2 4 8 OE Outputs Disabled Outputs Enabled www.onsemi.com 2 VCC FOUT FOUT GND VCC TEST GND NBC12429, NBC12429A 25 24 23 22 21 20 19 17 N[0] S_LOAD 28 16 M[8] PLL_VCC 1 15 M[7] NC 2 14 M[6] NC 3 13 M[5] XTAL1 4 12 M[4] 6 7 8 9 10 11 M[3] 5 M[2] 27 M[1] S_DATA M[0] N[1] P_LOAD 18 OE 26 XTAL2 S_CLOCK 32 31 30 29 28 27 26 25 VCC FOUT FOUT GND VCC VCC TEST GND GND TEST VCC VCC GND FOUT FOUT VCC Figure 2. PLCC−28 (Top View) 32 31 30 29 28 27 26 25 S_CLOCK 1 24 N/C S_DATA 2 23 N[1] S_LOAD 3 22 N[0] N[0] PLL_VCC 4 21 M[8] PLL_VCC 4 21 M[8] PLL_VCC 5 20 M[7] PLL_VCC 5 20 M[7] N/C 6 19 M[6] N/C 6 19 M[6] N/C 7 18 M[5] XTAL1 8 17 M[4] N/C 7 18 M[5] XTAL1 8 17 M[4] 15 16 N/C 14 M[3] 13 M[2] 12 M[1] 11 M[0] OE 10 P_LOAD XTAL2 9 9 10 11 12 13 14 15 16 N/C 22 M[3] 3 M[2] S_LOAD M[1] N[1] M[0] N/C 23 P_LOAD 24 2 OE 1 S_DATA XTAL2 S_CLOCK Figure 4. 32−Lead QFN (Top View) Figure 3. LQFP−32 (Top View) www.onsemi.com 3 Exposed Pad (EP) NBC12429, NBC12429A The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge. Table 3. PIN FUNCTION DESCRIPTION Pin Name Function Description INPUTS Crystal Inputs These pins form an oscillator when connected to an external series−resonant crystal. S_LOAD* CMOS/TTL Serial Latch Input (Internal Pulldown Resistor) This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH−to−LOW transition of S_LOAD for proper operation. S_DATA* CMOS/TTL Serial Data Input (Internal Pulldown Resistor) This pin acts as the data input to the serial configuration shift registers. S_CLOCK* CMOS/TTL Serial Clock Input (Internal Pulldown Resistor) This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge. P_LOAD** CMOS/TTL Parallel Latch Input (Internal Pullup Resistor) This pin loads the configuration latches with the contents of the parallel inputs. The latches will be transparent when this signal is LOW; therefore, the parallel data must be stable on the LOW−to−HIGH transition of P_LOAD for proper operation. M[8:0]** CMOS/TTL PLL Loop Divider Inputs (Internal Pullup Resistor) These pins are used to configure the PLL loop divider. They are sampled on the LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB. N[1:0]** CMOS/TTL Output Divider Inputs (Internal Pullup Resistor) These pins are used to configure the output divider modulus. They are sampled on the LOW−to−HIGH transition of P_LOAD. OE** CMOS/TTL Output Enable Input (Internal Pullup Resistor) Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output. PECL Differential Outputs These differential, positive−referenced ECL signals (PECL) are the outputs of the synthesizer. CMOS/TTL Output The function of this output is determined by the serial configuration bits T[2:0]. Positive Supply for the Logic The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V. Positive Supply for the PLL This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V. Negative Power Supply These pins are the negative supply for the chip and are normally all connected to ground. Exposed Pad for QFN−32 only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND. XTAL1, XTAL2 OUTPUTS FOUT, FOUT TEST POWER VCC PLL_VCC GND − * When left Open, these inputs will default LOW. ** When left Open, these inputs will default HIGH. www.onsemi.com 4 NBC12429, NBC12429A Table 4. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 37.5 kW ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 150 V > 1 kV Moisture Sensitivity (Note 1) Pb−Free Pkg PLCC LQFP QFN Level 3 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 2035 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol VCC Parameter Condition 1 Positive Supply GND = 0 V VI Input Voltage GND = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) qJA Condition 2 VI  VCC NBC12429 NBC12429A Rating Unit 6 V 6 V 50 100 mA mA 0 to 70 −40 to +85 °C −65 to +150 °C PLCC−28 PLCC−28 63.5 43.5 °C/W °C/W Standard Board PLCC−28 22 to 26 °C/W Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board LQFP−32 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder (Pb−Free) 2, fractional values of FOUT can be realized. The size of the programmable frequency steps (and thus, the indicator of the fractional output frequencies achievable) will be equal to FXTAL ÷ 16 ÷ N. For input reference frequencies other than 16 MHz, see Table 11, which shows the usable VCO frequency and M divider range. The input frequency and the selection of the feedback divider M is limited by the VCO frequency range and FXTAL. M must be configured to match the VCO frequency range of 200 MHz to 400 MHz in order to achieve stable PLL operation. M min + fVCOmin B (fXTAL B 16) and (eq. 3) M max + fVCOmax B (fXTAL B 16) (eq. 4) The value for M falls within the constraints set for PLL stability. If the value for M fell outside of the valid range, a different N value would be selected to move M in the appropriate direction. The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW, the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port, the www.onsemi.com 9 2 + 262, soM[8 : 0] + 100000110. NBC12429, NBC12429A again through the serial interface. This approach allows the application to come up at one frequency and then change or fine−tune the clock as the ability to control the serial interface becomes available. The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. The T2, T1, and T0 control bits are preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT outputs are as jitter−free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final nine bits of the data stream on the S_DATA input. For each register, the most significant bit is loaded first (T2, N1, and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figures 5 and 6 illustrate the timing diagram for both a parallel and a serial load of the device synthesizer. M[8:0] and N[1:0] are normally specified once at powerup through the parallel interface, and then possibly www.onsemi.com 10 NBC12429, NBC12429A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 11. FREQUENCY OPERATING RANGE Output Frequency for FXTAL = 16 MHz and for N = VCO Frequency Range for a Crystal Frequency of: M M[8:0] 10 12 14 16 18 20 160 010100000 170 010101010 180 010110100 202.5 225 190 010111110 213.75 237.5 200 011001000 200 225 210 011010010 210 220 011011100 230 011100110 240 250 B1 B2 B4 B8 250 200 100 50 25 236.25 262.5 210 105 52.5 26.25 220 247.5 275 220 110 55 27.5 201.25 230 258.75 287.5 230 115 57.5 28.75 011110000 210 240 270 300 240 120 60 30 011111010 218.75 250 281.25 312.5 250 125 62.5 31.25 260 100000100 227.5 260 292.5 325 260 130 65 32.5 270 100001110 202.5 236.25 270 303.75 337.5 270 135 67.5 33.75 280 100011000 210 245 280 315 350 280 140 70 35 290 100100010 217.5 253.75 290 326.25 362.5 290 145 72.5 36.25 300 100101100 225 262.5 300 337.5 375 300 150 75 37.5 310 100110110 232.5 271.25 310 348.75 387.5 310 155 77.5 38.75 320 101000000 200 240 280 320 360 400 320 160 80 40 330 101001010 206.25 247.5 288.75 330 371.25 330 165 82.5 41.25 340 101010100 212.5 255 297.5 340 382.5 340 170 85 42.5 350 101011110 218.75 262.5 306.25 350 393.75 350 175 87.5 43.75 360 101101000 225 270 315 360 360 180 90 45 370 101110010 231.25 277.5 323.75 370 370 185 92.5 46.25 380 101111100 237.5 285 332.5 380 380 190 95 47.5 390 110000110 243.75 292.5 341.25 390 390 195 97.5 48.75 400 110010000 250 300 350 400 400 200 100 50 410 110011010 256.25 307.5 358.75 420 110100100 262.5 315 367.5 430 110101110 268.75 322.5 376.25 440 110111000 275 330 385 450 111000010 281.25 337.5 393.75 460 111001100 287.5 345 470 111010110 293.75 352.5 480 111100000 300 360 490 111101010 306.25 367.5 500 111110100 312.5 375 510 111111110 318.75 382.5 200 212.5 www.onsemi.com 11 NBC12429, NBC12429A Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110, the device is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Figure 7 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 250 MHz or less. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 250 MHz as the minimum divide ratio of the N counter is 1. Note that the M counter output on the TEST output will not be a 50% duty cycle due to the way the divider is implemented. TEST (Pin 20) T2 T1 T0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M[8:0] N[1:0] ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ SHIFT REGISTER OUT HIGH FREF M COUNTER OUT FOUT LOW PLL BYPASS FOUT B 4 VALID ts P_LOAD ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ th M, N to P_LOAD Figure 5. Parallel Interface Timing Diagram ÇÇÇÇ ÇÇÇÇ S_CLOCK S_DATA ts C1 C2 th T2 T1 C3 C4 C5 C6 C7 C8 M7 M6 C10 C11 C12 C13 C14 T0 N1 N0 M8 M5 M4 M3 M2 M1 M0 Last Bit First Bit ÇÇÇÇ ÇÇÇÇ S_LOAD th ts S_CLOCK to S_LOAD Figure 6. Serial Interface Timing Diagram FREF_EXT MCNT PLL 12430 VCO_CLK 0 1 SCLOCK M COUNTER DECODE SDATA C9 S_DATA to S_CLOCK SHIFT REG T0 14−BIT T1 T2 FOUT (VIA ENABLE GATE) NB (1, 2, 4, 8) FDIV4 MCNT LOW FOUT MCNT FREF HIGH 7 TEST MUX 0 LATCH Reset SLOAD • T2=T1=1, T0=0: Test Mode PLOAD • SCLOCK is selected, MCNT is on TEST output, SCLOCK B N is on FOUT pin. PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin. Figure 7. Serial Test Clock Block Diagram www.onsemi.com 12 TEST NBC12429, NBC12429A APPLICATIONS INFORMATION Using the On−Board Crystal Oscillator Table 12. Crystal Specifications The NBC12429 and NBC12429A feature a fully integrated on−board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large load capacitors per Figure 8 (do not use cyrstal load caps). The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the device as possible to avoid any board level parasitics. To facilitate co−location, surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the crystal terminals, loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance, it may be required to place a resistance, optional Rshunt, across the terminals to suppress the third harmonic. Although typically not required, it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 W and 1 kW. Parameter Value Crystal Cut Fundamental AT Cut Resonance Series Resonance* Frequency Tolerance ±75 ppm at 25°C Frequency/Temperature Stability ±150 ppm 0 to 70°C Operating Range 0 to 70°C Shunt Capacitance 5−7 pF Equivalent Series Resistance (ESR) 50 to 80 W Correlation Drive Level 100 mW Aging 5 ppm/Yr (First 3 Years) *See accompanying text for series versus parallel resonant discussion. Power Supply Filtering The NBC12429 and NBC12429A are mixed analog/digital products and as such, exhibit some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NBC12429 and NBC12429A provide separate power supplies for the digital circuitry (VCC) and the internal PLL (PLL_VCC) of the device. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog PLL. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the PLL_VCC pin for the NBC12429 and NBC12429A. Figure 9 illustrates a typical power supply filter scheme. The NBC12429 and NBC12429A are most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the PLL_VCC pin of the NBC12429 and NBC12429A. From the data sheet, the PLL_VCC current (the current sourced through the PLL_VCC pin) is typically 23 mA (27 mA maximum). Assuming that a minimum of 2.8 V must be maintained on the PLL_VCC pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 9 must have a resistance of 10 − 15 W to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, it’s overall Figure 8. Crystal Application The oscillator circuit is a series resonant circuit and thus, for optimum performance, a series resonant crystal should be used. Unfortunately, most crystals are characterized in a parallel resonant mode. Fortunately, there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result, a parallel resonant crystal can be used with the device with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified (a few hundred ppm translates to kHz inaccuracies). In a general computer application, this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the device. www.onsemi.com 13 NBC12429, NBC12429A ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. 3.3 V or 5.0 V 3.3 V or 5.0 V C1 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ C1 R1 RS = 10−15 W PLL_VCC L=1000 mH R=15 W 1 C3 C2 R1 = 10−15 W C1 = 0.01 mF C2 = 22 mF C3 = 0.1 mF 22 mF 0.01 mF NBC12429 NBC12429A VCC Xtal 0.01 mF Rshunt ÉÉ ÉÉ = VCC = GND Figure 9. Power Supply Filter A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. Figure 9 shows a 1000 mH choke. This value choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin, a low DC resistance inductor is required (less than 15 W). Generally, the resistor/capacitor filter will be cheaper, easier to implement, and provide an adequate level of supply filtering. The NBC12429 and NBC12429A provide sub−nanosecond output edge rates and therefore a good power supply bypassing scheme is a must. Figure 10 shows a representative board layout for the NBC12429 and NBC12429A. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 10 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NBC12429 and NBC12429A outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Opt. Rshunt = 500 −1 kW = Via Figure 10. PCB Board Layout (PLCC−28) Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on−board oscillator. Note the provisions for placing a resistor across the crystal oscillator terminals as discussed in the crystal oscillator section of this data sheet. Although the NBC12429 and NBC12429A have several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise−related problems in most designs. Jitter Performance Jitter is a common parameter associated with clock generation and distribution. Clock jitter can be defined as the deviation in a clock’s output transition from its ideal position. Cycle−to−Cycle Jitter is the period variation between two adjacent cycles over a defined number of observed cycles. The number of cycles observed is application www.onsemi.com 14 NBC12429, NBC12429A dependent but the JEDEC specification is 1000 cycles. Both Peak−to−Peak and RMS statistical values were measured. Period Jitter is the edge placement deviation observed over a long period of consecutive cycles compared to the position of the perfect reference clock’s edge and is specified by the number of cycles over which the jitter is measured. The number of cycles used to look for the maximum jitter varies by application but the JEDEC spec is 10,000 observed cycles. Both Peak−to−Peak and RMS value statistical values were measured. T0 Table 13 shows the typical Period and Cycle−to−Cycle jitter as a function of the output frequency for selected M and N values using a 16 MHz crystal. Typical jitter values for other M and N registers settings may be linearly interpolated. The general trend is that as the VCO output frequency is increased, primarily determined by the M register setting, the output jitter will decrease. Alternate combinations of M and N register values may produce the same output frequency but with significantly different jitter performance. T1 TJITTER(cycle−cycle) = T1 − T0 Figure 11. Cycle−to−Cycle Jitter www.onsemi.com 15 NBC12429, NBC12429A Table 13. TYPICAL JITTER PERFORMANCE, 3.3 V, 25°C with 16 MHz Crystal Input at Selected M and N Values M Value 200 200 200 200 300 300 300 300 400 400 400 400 N Value 1 2 4 8 1 2 4 8 1 2 4 8 JITTER FOUT in MHz Cycle−to−Cycle (psPP) 25 106 37.5 67 50 91 44 75 55 100 105 51 150 200 59 98 52 300 58 400 Cycle−to−Cycle (psRMS) 43 25 17 37.5 10 50 13 7 75 9 100 13 8 150 200 9 11 8 300 6 400 Period (psPP) 6 25 106 37.5 56 50 79 35 75 42 100 66 32 150 200 39 65 31 300 38 400 Period (psRMS) 33 25 14 37.5 7 50 10 75 6 100 4 150 200 5 7 5 6 4 300 4 400 4 www.onsemi.com 16 NBC12429, NBC12429A S_DATA S_CLOCK tHOLD tSETUP Figure 12. Setup and Hold S_DATA S_LOAD tHOLD tSETUP Figure 13. Setup and Hold M[8:0] N[1:0] P_LOAD tHOLD tSETUP Figure 14. Setup and Hold FOUT FOUT Pulse Width tPERIOD Figure 15. Output Duty Cycle www.onsemi.com 17 DCO + tpw tPERIOD NBC12429, NBC12429A FOUT Zo = 50 W D Receiver Device Driver Device FOUT D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 18 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LQFP−32, 7x7 CASE 561AB−01 ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON30893E 32 LEAD LQFP, 7X7 DATE 19 JUN 2008 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 28 LEAD PLCC CASE 776−02 ISSUE G DATE 06 APR 2021 281 SCALE 1:1 B Y BRK −N− 0.007 (0.180) U M T L-M 0.007 (0.180) M N S T L-M S S N S D Z −M− −L− W 28 D X V 1 G1 0.010 (0.250) T L-M S N S S VIEW D−D Z A 0.007 (0.180) R 0.007 (0.180) M M T L-M T L-M S S N N H S 0.007 (0.180) M T L-M N S S S K1 C E 0.004 (0.100) G S SEATING PLANE K F 0.007 (0.180) M T L-M S N S VIEW S G1 0.010 (0.250) −T− J T L-M S N NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DOCUMENT NUMBER: DESCRIPTION: VIEW S S GENERIC MARKING DIAGRAM* 1 28 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.021 0.050 BSC 0.026 0.032 0.020 --0.025 --0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10_ 0.410 0.430 0.040 --- 98ASB42596B 28 LEAD PLCC MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.53 1.27 BSC 0.66 0.81 0.51 --0.64 --11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10_ 10.42 10.92 1.02 --- XXXXXXXXXXXX XXXXXXXXXXXG AWLYYWW XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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