NBSG16MMNR2

NBSG16M 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer Description http://onsemi.com MARKING DIAGRAM* 16 1 The NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities. Inputs incorporate internal 50 W termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open. Features 1 QFN−16 MN SUFFIX CASE 485G SG 16M ALYW G G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • • • • • • • • • • • Maximum Input Clock Frequency > 10 GHz Typical Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V CML Output Level; 400 mV Peak−to−Peak Output with 50 W Receiver Resistor to VCC 50 W Internal Input and Output Termination Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices VBB Reference Voltage Output Pb−Free Packages are Available ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 5 1 Publication Order Number: NBSG16M/D NBSG16M VCC VBB 16 VTD D D VTD 1 2 NBSG16M 3 4 5 VCC 6 NC 7 VEE 8 VEE 10 9 Q VCC 15 VEE 14 VEE 13 12 11 Exposed Pad (EP) VCC Q Figure 1. QFN−16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name VTD D D I/O − Description LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input − − − − − − CML Output CML Output − − − − − − VTD VCC NC VEE VEE VCC Q Q VCC VEE VEE VBB VCC EP 1. The NC pins are electrically connected to the die and MUST be left open. 2. CML outputs require 50 W receiver termination resistor to VCC for proper operation. 3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Inverted Differential Input (Note 3) Noninverted Differential Input. (Note 3) Internal 50 W Termination Pin. See Table 2. (Note 3) Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. No Connect (Note 1) Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Noninverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) Inverted CML Differential Output with Internal 50 W Source Termination Resistor. (Note 2) Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation. Internally Generated ECL Reference Output Voltage Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Internal 50 W Termination Pin. See Table 2. (Note 3) ÁÁÁ Á Á Á ÁÁÁ Á Á Á http://onsemi.com 2 NBSG16M VCC VCC VTD 50 W D D 50 W VTD VBB 16 mA VEE VEE 50 W 50 W Q Q 50 W 50 W Q Q Figure 2. Logic Diagram Figure 3. CML Output Structure Table 2. Interfacing Options INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTD and VTD to VCC Connect VTD and VTD together Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Pb Pkg Level 1 Value > 1 kV > 100 V > 4 kV Pb−Free Pkg Level 1 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 4) QFN−16 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in 145 4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 3 NBSG16M Table 4. MAXIMUM RATINGS Symbol VCC VEE VI VINPP IIN Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D − D| Input Current Through RT (50 W Resistor) Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 5) Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm 1S2P (Note 5)