DATA SHEET
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Bluetooth) 5.2
System-in-Package (SiP)
RSL10 SIP
SIP51 8x6
CASE 127EY
Introduction
RSL10 System−In−Package (RSL10 SIP) is a complete solution
that provides the easiest way to integrate the industry’s lowest power
Bluetooth Low Energy technology into a wireless application.
The RSL10 SIP features an on−board antenna, RSL10 radio SoC,
and all necessary passive components in one package to help minimize
overall system size. Already fully qualified to FCC, CE, and other
regulatory standards; RSL10 SIP removes the need for additional
antenna design considerations or RF certifications.
Key Features
• Fully Certified:
Bluetooth 5.2
QDID
♦ Declaration ID
♦ FCC, CE, IC, MIC, KCC
Industry’s Lowest Power:
♦ Peak Rx Current = 5.6 mA (1.25 V VBAT)
♦ Peak Rx Current = 3.0 mA (3 V VBAT)
♦ Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT)
♦ Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT)
Deep Sleep Current Consumption (1.25 V VBAT):
♦ Deep Sleep, IO Wake−up: 50 nA
♦ Deep Sleep, 8 kB RAM Retention: 300 nA
Current Consumption (3 V VBAT):
♦ Deep Sleep, IO Wake−up: 25 nA
♦ Deep Sleep, 8 kB RAM Retention: 100 nA
EEMBC ULPMark Core Profile (3 V): 1090
EEMBC ULPMark Core Profile (2.1 V): 1360
Advanced Wireless:
♦ Bluetooth 5.2 Certified with LE 2−Mbit PHY (High Speed),
as well as Backwards Compatibility and Support for Earlier
Bluetooth Low Energy Specifications
♦ Supports FOTA (Firmware Over−The−Air) Updates
♦ Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −93 dB
♦ Transmitting Power: −17 to +6 dBm
♦ Range up to 100 Meters
♦
♦
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XXXXX
AWLYWW
(SIP51)
XXXXXX
A
WL
Y
WW
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCH−RSL10−
101S51−ACG
SIP51
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Other Key Features
•
•
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Arm® Cortex®−M3 Processor Clocked at up to 48 MHz
Supply Voltage Range: 1.1 − 3.3 V
384 kB of Flash Memory
76 kB of Program Memory
88 kB of Data Memory
© Semiconductor Components Industries, LLC, 2018
January, 2022 − Rev. 4
1
Publication Order Number:
RSL10SIP/D
RSL10 SIP
FEATURES
• Arm Cortex−M3 Processor: A 32−bit core for real−time
• Highly Configurable Interfaces: I2C, UART, two SPI
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applications, specifically developed to enable
high−performance low−cost platforms for a broad range
of low−power applications.
LPDSP32: A 32−bit Dual Harvard DSP core that
efficiently supports intensive signal processing
applications. Various codecs are available to customers
through libraries that are included in RSL10’s
development tools.
Radio Frequency Front−End: Based on a 2.4 GHz RF
transceiver, the RFFE implements the physical layer of
the Bluetooth Low Energy technology standard and other
proprietary or custom protocols.
Protocol Baseband Hardware: Bluetooth 5.2 certified
and includes support for a 2 Mbps RF link and custom
protocol options. The RSL10 baseband stack is
supplemented by support structures that enable
implementation of onsemi and customer designed
custom protocols.
Highly−Integrated SoC: The dual−core architecture is
complemented by high−efficiency power management
units, oscillators, flash and RAM memories, a DMA
controller, along with a full complement of peripherals
and interfaces.
Deep Sleep Mode: RSL10 can be put into a Deep Sleep
Mode when no operations are required. Various Deep
Sleep Mode configurations are available, including:
♦ “IO wake−up” configuration. The power consumption
in deep sleep mode is 50 nA (1.25 V VBAT).
♦ Embedded 32 kHz oscillator running with interrupts
from timer or external pin. The total current drain is
90 nA (1.25 V VBAT).
♦ As above with 8 kB RAM data retention. The total
current drain is 300 nA (1.25 V VBAT).
♦ The DC−DC converter can be used in buck mode or
LDO mode during Sleep Mode, depending on VBAT
voltage.
Standby Mode: Can be used to reduce the average power
consumption for off−duty cycle operation, ranging
typically from a few ms to a few hundreds of ms. The
typical chip power consumption is 30 mA in Standby
Mode.
Multi−Protocol Support: Using the flexibility provided
by LPDSP32, the Arm Cortex−M3 processor, and the RF
front−end; proprietary protocols and other custom
protocols are supported.
Flexible Supply Voltage: RSL10 integrates high−
efficiency power regulators and has a VBAT range of 1.1
to 3.3 V.
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interfaces, PCM interface, multiple GPIOs. It also
supports a digital microphone interface (DMIC) and an
output driver (OD).
Flexible Clocking Scheme: RSL10 must be clocked
from the XTAL/PLL of the radio front−end at 48 MHz
when transmitting or receiving RF traffic. When RSL10
is not transmitting/receiving RF traffic, it can run off the
48 MHz XTAL, the internal RC oscillators, the 32 kHz
oscillator, or an external clock. A low frequency RTC
clock at 32 kHz can also be used in Deep Sleep Mode. It
can be sourced from either the internal XTAL, the RC
oscillator, or a digital input pad.
Diverse Memory Architecture: 76 kB of SRAM
program memory (4 kB of which is PROM containing the
chip boot−up program, and is thus unavailable to the user)
and 88 kB of SRAM data memory are available. A total
of 384 kB of flash is available to store the Bluetooth stack
and other applications.
The Arm Cortex−M3 processor can execute from SRAM
and/or flash.
Security: AES128 encryption hardware block for custom
secure algorithms and code protection with authenticated
debug port access (JTAG ‘lock’)
Ultra−Low Power Consumption Application
Examples:
♦ Low Duty Cycle Advertising: IDD 1.1 mA for
advertising at all three channels at 5 second intervals
@ VBAT 3 V, DCDC converter enabled.
RoHS Compliant Device
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RSL10 SIP
Notice
inside the SiP. If an external antenna is used instead of the
antenna internal to the SiP, this external antenna needs to be
connected to PIN E1.
Additionally, an external PCB connection is required for
the VDDO pad to ensure that it is not left floating. For
example, it can be connected to VBAT so that the logic high
level for the digital I/O (DIO) pads is equal to VBAT.
Figures 1 and 2 show proposed layout patterns for the
RSL10 SIP. The specific layout pattern used in the
application may have to be adjusted to meet certain needs of
the PCB manufacturer or assembly house. PCB design files
for the RSL10 SIP are available at www.onsemi.com.
All specifications for the RSL10 System−in−Package are
based on the RSL10 radio SoC. The RSL10 SIP data sheet
only contains key parameters. For a full list of RSL10
parameters and specifications, refer to the RSL10 data sheet.
Application Board Connection
The RSL10 SIP is designed to be reflowed onto low−cost
printed circuit boards. The RSL10 SIP connects to the
application board via solder pads located on the bottom.
To properly operate the RSL10 SIP an external PCB
connection between the RF and ANT pads is required. This
connection connects the RF pin on RSL10 to the antenna
Notes:
1. Align component edge to PCB edge if possible.
2. Extend keepout area to PCB edge.
3. Keepout area− All layers.
4. Keepout area− Top layer only.
5. Units = mm.
Figure 1. RSL10 SIP Keepout Area Requirements
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3
RSL10 SIP
Notes:
1. When incorporating internal antenna, join landing pads using 0.40 x 1.10 shape.
2. Establish 50 W impedance to underlying reference plane.
3. Maintain minimum 300 mm distance from ground plane.
4. Area for several vias.
5. Refer to radiation efficiency data for applicable ground plane sizing.
6. Units = mm.
Figure 2. Minimum Top Layer Ground Structure
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RSL10 SIP
RSL10 SiP Schematic
The schematic for the RSL10 SIP is shown in Figure 3.
Figure 3. RSL10 SIP Schematic
Figure 4. Pin Connection Diagram
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5
RSL10 SIP
PAD FUNCTION DESCRIPTION
For detailed pad function information see the RSL10 data sheet.
Table 1. PAD LIST
Pad Identifier
Pad Name
I/O
A/D
Pull
A1
JTMS
I/O
D
U
A2
DOI12
I/O
D
U/D
Digital input output 12
A3
JTCK
I/O
D
U
CM3−JTAG Test Clock
A4
DOI10
I/O
D
U/D
Digital input output 10
A5
DOI6
I/O
D
U/D
Digital input output 6
A6
DOI3
I/O
A/D
U/D
Digital input output 3 / ADC 3
A7
DOI2
I/O
A/D
U/D
Digital input output 2 / ADC 2
A8
DOI5
I/O
D
U/D
Digital input output 5
B1
DOI13
I/O
D
U/D
Digital input output/CM3−JTAG Test Reset
B2
DOI14
I/O
D
U/D
Digital input output/CM3−JTAG Test Data In
B3
DOI11
I/O
D
U/D
Digital input output 11
B5
DOI8
I/O
D
U/D
Digital input output 8
B6
DOI1
I/O
A/D
U/D
Digital input output 1 / ADC 1
B7
DOI7
I/O
D
U/D
Digital input output 7
B8
DOI4
I/O
D
U/D
Digital input output 4
C1
DOI15
I/O
D
U/D
Digital input output/CM3−JTAG Test Data Out
C2
DOI9
I/O
D
U/D
Digital input output 9
C7
DOI0
I/O
A/D
U/D
Digital input output 0 / ADC 0
C8
EXT_CLK
I
D
U
D1
DGND
I/O
P
Ground
D2
DGND
I/O
P
Ground
D7
VDDO
I
P
Digital O/I voltage supply
D8
VBAT
I
P
Battery input voltage
E1
RF
I/O
A
RF signal input/output
E2
DGND
I/O
P
Ground
E7
NRESET
I
D
E8
AOUT
O
A
Analog test pin
F1
ANT
I/O
A
Antenna
F2
DGND
I/O
P
Ground
F3
DGND
I/O
P
Ground
F4
DGND
I/O
P
Ground
F5
DGND
I/O
P
Ground
F6
DGND
I/O
P
Ground
F7
RES
I
D
F8
WAKEUP
I
A
Wake−up pin for power modes
G1
DGND
I/O
P
Ground
G2
DGND
I/O
P
Ground
G3
DGND
I/O
P
Ground
G4
DGND
I/O
P
Ground
G5
DGND
I/O
P
Ground
U
D
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Description
CM3−JTAG Test Mode State
External clock input
Reset pin
RESERVED
RSL10 SIP
Table 1. PAD LIST (continued)
Pad Identifier
Pad Name
I/O
A/D
Pull
Description
G6
DGND
I/O
P
Ground
G7
DGND
I/O
P
Ground
G8
DGND
I/O
P
Ground
H1
DGND
I/O
P
Ground
H8
DGND
I/O
P
Ground
J1
DGND
I/O
P
Ground
J8
DGND
I/O
P
Ground
K1
DGND
I/O
P
Ground
K8
DGND
I/O
P
Ground
L1
DGND
I/O
P
Ground
L8
DGND
I/O
P
Ground
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Unit
VBAT
Power supply voltage
3.63
V
VDDO
I/O supply voltage (Note 1)
3.63
V
VSSRF
RF front−end ground
−0.3
V
VSSA
Analog ground
−0.3
V
VSSD
Digital core and I/O ground
Vin
T storage
−0.3
Voltage at any input pin
Storage temperature range
V
VSSD−0.3
VDDO+0.3
(Up to a maximum of 3.63 V)
V
−40
85
°C
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
The QFN package meets 450 V CDM level
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDDO voltage must not be applied before VBAT voltage on cold start.
Table 3. RECOMMENDED OPERATING CONDITIONS
Description
Supply voltage operating range
Functional temperature range
Symbol
Conditions
Min
Typ
Max
Unit
VBAT
Input supply voltage on VBAT pin (Note 2)
1.18
1.25
3.3
V
−40
−
85
°C
T functional
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed:
− Maximum Tx power 0 dBm.
− SYSCLK ≤ 24 MHz.
− Functional temperature range limited to 0−50 deg C
The following trimming parameters should be used:
− VCC = 1.10 V
− VDDC = 0.92 V
− VDDM = 1.05 V, will be limited by VCC at end of battery life
− VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled
RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT ≥ 1.10 V under
the restricted operating conditions described above.
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RSL10 SIP
Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or
VBAT = VDDO = 3 V in DC−DC (buck) mode.
Description
Symbol
Conditions
Min
Typ
Max
Unit
OVERALL
Current consumption RX,
VBAT = 1.25 V, low latency
IVBAT
1.8
mA
Current consumption TX,
VBAT = 1.25 V, low latency
IVBAT
1.8
mA
Current consumption RX,
VBAT = 1.25 V
IVBAT
1.15
mA
Deep sleep current,
example 1, VBAT = 1.25 V
Ids1
Wake up from wake up pin or DIO
wake up.
50
nA
Deep sleep current,
example 2, VBAT = 1.25 V
Ids2
Embedded 32 kHz oscillator running
with interrupts from timer or external pin.
90
nA
Deep sleep current,
example 3, VBAT = 1.25 V
Ids3
As Ids2 but with 8 kB RAM data
retention.
300
nA
Standby Mode current,
VBAT = 1.25 V
Istb
Digital blocks and memories are not
clocked and are powered at a reduced
voltage.
30
mA
Current consumption RX,
VBAT = 3 V
IVBAT
0.9
mA
Current consumption TX,
VBAT = 3 V
IVBAT
0.9
mA
Deep sleep current,
example 1, VBAT = 3 V
Ids1
Wake up from wake up pin or DIO
wake up.
25
nA
Deep sleep current,
example 2, VBAT = 3 V
Ids2
Embedded 32 kHz oscillator running
with interrupts from timer or external pin.
40
nA
Deep sleep current,
example 3, VBAT = 3 V
Ids3
As Ids2 but with 8 kB RAM data
retention.
100
nA
Standby Mode current,
VBAT = 3 V
Istb
Digital blocks and memories are not
clocked and are powered at a reduced
voltage.
17
mA
ULPMark CP 3.0 V
Arm Cortex−M3 processor running from
RAM, VBAT= 3.0 V, IAR C/C++
Compiler for ARM 8.20.1.14183
1090
ULP
Mark
ULPMark CP 2.1 V
Arm Cortex−M3 processor running from
RAM, VBAT= 2.1 V, IAR C/C++
Compiler for ARM 8.20.1.14183
1260
ULP
Mark
EEMBC ULPMark BENCHMARK, CORE PROFILE
EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP
Arm Cortex−M3 processor
running from RAM
At 48 MHz SYSCLK. Using the IAR
8.10.1 C compiler, certified
159
Core
Mark
LPDSP32 running from RAM
At 48 MHz SYSCLK
Using the 2020.03 release of
the Synopsys LPDSP32 C compiler
174
Core
Mark
Arm Cortex−M3 processor and
LPDSP32 running from RAM,
VBAT = 1.25 V
At 48 MHz SYSCLK
123
Core
Mark/
mA
Arm Cortex−M3 processor and
LPDSP32 running from RAM,
VBAT = 3 V
At 48 MHz SYSCLK
293
Core
Mark/
mA
Arm Cortex−M3 processor
running CoreMark from RAM,
VBAT = 1.25 V
At 48 MHz SYSCLK
(processor consumption only)
29.1
mA/MHz
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RSL10 SIP
Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or
VBAT = VDDO = 3 V in DC−DC (buck) mode.
Description
Symbol
Conditions
Min
Typ
Max
Unit
EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP
Arm Cortex−M3 processor
running CoreMark from RAM,
VBAT = 3 V
At 48 MHz SYSCLK
(processor consumption only)
12.3
mA/MHz
Arm Cortex−M3 processor
running CoreMark from Flash,
VBAT = 1.25 V
At 48 MHz SYSCLK
(processor consumption only)
34.3
mA/MHz
Arm Cortex−M3 processor
running CoreMark from Flash,
VBAT = 3 V
At 48 MHz SYSCLK
(processor consumption only)
14.6
mA/MHz
LPDSP32 running CoreMark
from RAM, VBAT = 1.25 V
At 48 MHz SYSCLK
(processor consumption only)
19.5
mA/MHz
LPDSP32 running CoreMark
from RAM, VBAT = 3 V
At 48 MHz SYSCLK
(processor consumption only)
8.2
mA/MHz
INTERNALLY GENERATED VDDC: Digital Block Supply Voltage
Supply voltage: operating range
VDDC
0.92
Supply voltage: trimming range
VDDCRANGE
0.75
Supply voltage: trimming step
VDDCSTEP
1.15
1.32
(Note 3)
V
1.38
V
10
mV
INTERNALLY GENERATED VDDM: Memories Supply Voltage
Supply voltage: operating range
VDDM
1.05
Supply voltage: trimming range
VDDMRANGE
0.75
Supply voltage: trimming step
VDDMSTEP
1.15
1.32
(Note 4)
1.38
10
V
V
mV
INTERNALLY GENERATED VDDRF: Radio Front end supply voltage
Supply voltage: operating range
VDDRF
1.00
Supply voltage: trimming range
VDDRFRANGE
0.75
Supply voltage: trimming step
VDDRFSTEP
1.10
1.32 (Notes
5 and 6)
V
1.38
V
10
mV
VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage
Digital I/O supply
VDDO
1.1
1.25
3.3
V
1.4
3.3
V
1.1
3.3
V
1.32
V
INDUCTIVE BUCK DC−DC CONVERTER
VBAT range when the DC−DC
converter is active (Note 7)
IN_RANGE
VBAT range when the LDO is
active
IN_RANGE
Output voltage: trimming range
DCDC
LDO
DCDC
1.1
1.2
OUT_RANGE
Supply voltage: trimming step
DCDCSTEP
10
mV
POWER−ON RESET
POR voltage
VBATPOR
0.4
0.8
1.0
V
RADIO FRONT−END: General Specifications
RF input impedance
Data rate FSK / MSK / GFSK
Zin
RFSK
Single ended
50
OQPSK as MSK
62.5
Data rate 4−FSK
On−air data rate
bps
GFSK
250
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1000
W
3000
kbps
4000
kbps
2000
kbps
RSL10 SIP
Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or
VBAT = VDDO = 3 V in DC−DC (buck) mode.
Description
Symbol
Conditions
Min
Typ
Max
Unit
RADIO FRONT−END: Crystal and Clock Specifications
Xtal frequency
FXTAL
Fundamental
48
Settling time
0.5
MHz
1.5
ms
RADIO FRONT−END: Synthesizer Specifications
Frequency range
2500
MHz
RX frequency step
FRF
Supported carrier frequencies
RX Mode frequency synthesizer
resolution
2360
100
Hz
TX frequency step
TX Mode frequency synthesizer
resolution
600
Hz
PLL Settling time, RX
tPLL_RX
RX Mode
15
25
ms
PLL Settling time, TX
tPLL_TX
TX mode, BLE modulation
5
10
ms
RADIO FRONT−END: Receive Mode Specifications
Current consumption at 1 Mbps,
VBAT = 1.25 V
IBATRFRX
VDDRF = 1.1 V, 100% duty cycle
5.6
mA
Current consumption at 2 Mbps,
VBAT = 1.25 V
IBATRFRX
VDDRF = 1.1 V, 100% duty cycle
6.2
mA
Current consumption at 1 Mbps,
VBAT = 3 V, DC−DC
IBATRFRX
VDDRF = 1.1 V, 100% duty cycle
3.0
mA
Current consumption at 2 Mbps,
VBAT = 3 V, DC−DC
IBATRFRX
VDDRF = 1.1 V, 100% duty cycle
3.4
mA
RX Sensitivity, 0.25 Mbps
0.1% BER (Notes 8, 9)
−96
dBm
RX Sensitivity, 0.5 Mbps
0.1% BER (Notes 8, 9)
−95
dBm
RX Sensitivity, 1 Mbps, BLE
0.1% BER (Notes 8, 9) Single−ended
match to 50 W
−93
dBm
RX Sensitivity, 2 Mbps, BLE
0.1% BER (Notes 8, 9)
−91
dBm
RSSI effective range
Without AGC
60
dB
2.4
dB
48
dB
6
dB
−10
dBm
Tx power 0 dBm, VDDRF = 1.07 V,
VDDPA: off, LDO mode
8.9
mA
Tx power 3 dBm, VDDRF = 1.1 V,
VDDPA: 1.26 V, LDO mode
17.4
mA
Tx power 6 dBm, VDDRF = 1.1 V,
VDDPA: 1.60 V, LDO mode
25
mA
Tx power 0 dBm, VDDRF = 1.07 V,
VDDPA: off, DC−DC mode
4.6
mA
Tx power 3 dBm, VDDRF = 1.1 V,
VDDPA = 1.26 V, DC−DC mode
8.6
mA
Tx power 6 dBm, VDDRF = 1.1 V,
VDDPA = 1.60 V, DC−DC mode
12
mA
RSSI step size
RX AGC range
RX AGC step size
Programmable
Max usable signal level
0.1% BER
RADIO FRONT−END: Transmit Mode Specifications
Tx peak power consumption at
VBAT = 1.25 V (Note 10)
Tx peak power consumption at
VBAT = 3 V (Note 10)
IBATRFTX
IBATRFTX
Transmit power range
BLE
Transmit power step size
Full band
−17
+6
(Note 12)
1
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dBm
dB
RSL10 SIP
Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or
VBAT = VDDO = 3 V in DC−DC (buck) mode.
Description
Symbol
Conditions
Min
Tx power 0 dBm. Full band. Relative to
the typical value.
−1.5
Typ
Max
Unit
1.5
dB
RADIO FRONT−END: Transmit Mode Specifications
Power in 2nd harmonic
0 dBm mode. 50 W for “Typ” value.
(Note 11)
−62
dBm
Power in 3rd harmonic
0 dBm mode. 50 W for “Typ” value.
(Note 11)
−70
dBm
Power in 4th harmonic
0 dBm mode. 50 W for “Typ” value.
(Note 11)
−82
dBm
ADC
Resolution
Input voltage range
INL
DNL
Channel sampling frequency
ADCRES
8
14
bits
ADCRANGE
0
2
V
ADCINL
−2
+2
mV
ADCDNL
ADCCH_SF
For the 8 channels sequentially,
SLOWCLK = 1 MHz
12
−1
+1
mV
0.0195
6.25
kHz
50
kHz
32 kHz ON−CHIP RC OSCILLATOR
Untrimmed Frequency
Trimming steps
FreqUNTR
20
Steps
32
1.5
%
3 MHz ON−CHIP RC OSCILLATOR
Untrimmed Frequency
FreqUNTR
2
3
5
MHz
Trimming steps
Steps
1.5
%
Hi Speed mode
Fhi
10
MHz
32768
Hz
32 kHz ON−CHIP CRYSTAL OSCILLATOR
Output Frequency
Freq32k
Depends on xtal parameters
Startup time
1
Internal load trimming range
Steps of 0.4 pF
Duty Cycle
0
40
50
3
s
25.2
pF
60
%
DC INPUT CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 2.97 V – 3.3 V, nominal: 3.0 V Logic
Voltage level for high input
VIH
2
VDDO + 0.3
V
Voltage level for low input
VIL
VSSD −
0.3
0.8
V
DC INPUT CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 1.1 V – 1.32 V, nominal: 1.2 V Logic
Voltage level for high input
VIH
0.65 *
VDDO
VDDO + 0.3
V
Voltage level for low input
VIL
VSSD −
0.3
0.35 *
VDDO
V
DC OUTPUT CHARACTERISTICS OF THE DIGITAL PADS
Voltage level for high output
VOH
IOH = 2 mA to 12 mA
VDDO −
0.4
Voltage level for low output
VOL
IOH = 2 mA to 12 mA
4
V
0.4
V
12
mA
DIO DRIVE STRENGTH
DIO drive strength
IDIO
2
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12
RSL10 SIP
Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or
VBAT = VDDO = 3 V in DC−DC (buck) mode.
Description
Symbol
Conditions
Min
Typ
Max
Unit
FLASH SPECIFICATIONS
Endurance of the 384 kB of flash
10000
write/
erase
cycles
Endurance for sections NVR1,
NVR2, and NVR3 (6 kB in total)
1000
write/
erase
cycles
25
years
Retention
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
4. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
5. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
6. The VDDRF calibrated target is 1.07 V (TX power = 0 dBm).
7. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it
is possible to save power by activating the DC−DC converter to generate VCC.
8. Signal generated by RF tester.
9. Single−ended match to 50 ohms, measured at pin E1 including loss of integrated Tx harmonic filter.
10. All values are based on evaluation board performance, including the harmonic filter loss.
11. The values shown here are including integrated RF filter.
12. For optimal performance, charge pump frequency of 125 kHz should be avoided when VDDPA supply is enabled.
Table 5. VDDM TARGET TRIMMING VOLTAGE IN FUNCTION OF VDDO VOLTAGE
NOTE:
VDDM Voltage (V)
DIO_PAD_CFG DRIVE
Maximum VDDO Voltage (V)
1.05
1
2.7
1.05
0
3.2
1.10
0
3.3
These are trimming targets at room/ATE temperature 25X30°C.
Table 6. VDDC TARGET TRIMMING VOLTAGE IN FUNCTION OF SYSCLK FREQUENCY
NOTE:
VDDC Voltage (V)
Maximum SYSCLK Frequency (MHz)
Restriction
0.92
≤ 24
The ADC will be functional in low frequency
mode and between 0 and 85°C only.
1.00
≤ 24
Fully functional
1.05
48
Fully functional
These are trimming targets at room/ATE temperature 25X30°C.
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12
RSL10 SIP
ANTENNA SPECIFICATIONS
The antenna performance of the RSL10 SIP depends on the size of the ground plane on which it is mounted. Figure 5 shows
an overview of different ground plane sizes with expected antenna return losses shown in Figure 6.
1
2
3
4
50 x 60mm
40 x 60mm
30 x 60mm
25 x 60mm
5
Figure 5. PCB ground planes. 1) 50x60, 2) 40x60, 3) 30x60, 4) 25x60, 5) 12.5x60. All sizes in mm
Efficiency
80.00
70.00
60.00
%
50.00
40.00
30.00
20.00
10.00
0.00
1
2
3
4
5
Figure 6. Antenna Efficiency vs. PCB Size
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13
6
25 x 25mm 12.4 x 60mm
6
RSL10 SIP
Figure 7. Radiation Pattern for 50 x 60 mm PCB Ground Plane
Figure 8. Radiation Pattern for 40 x 60 mm PCB Ground Plane
Figure 9. Radiation Pattern for 30 x 60 mm PCB Ground Plane
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14
RSL10 SIP
Figure 10. Radiation Pattern for 25 x 60 mm PCB Ground Plane
Figure 11. Radiation Pattern for 25 x 25 mm PCB Ground Plane
Figure 12. Radiation Pattern for 12.5 x 60 mm PCB Ground Plane
ENVIRONMENTAL SPECIFICATIONS
Electrostatic Discharge (ESD) Sensitive Device
CAUTION: ESD sensitive device. Permanent damage may occur on devices subjected to high−energy electrostatic
discharges.
Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of
functionality.
Solder Information
The RSL10 SIP is constructed with all RoHS compliant material and should be reflowed accordingly. This device is Moisture
Sensitive Class MSL3 and must be stored and handled accordingly. Re−flow according to IPC/JEDEC standard J−STD−020C,
Joint Industry Standard: Re−flow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Hand
soldering is not recommended for this part.
For more information, see SOLDERRM/D available from www.onsemi.com.
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15
RSL10 SIP
REGULATORY INFORMATION
FCC Regulatory and User Information
FCC ID: 2APD9−RSL10SIP
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and (2) this device must accept any interference received, including
interference that may cause undesired operation.
Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.
Module Usage Conditions
Manufacturers of products incorporating the RSL10SIP Bluetooth 5.2 Module are authorized to use the FCC Grant of the
RSL10SIP module for their own products according to the conditions referenced in the grant.
A product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wording
such as: “Contains FCC ID:2APD9−RSL10SIP”
The label of the host device shall also contain the following statement. When this is not possible, the information shall be
included in the User Manual of the host device:
“This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and (2) this device must accept any interference received, including
interference that may cause undesired operation.
Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.”
WARNING: RF Exposure Compliance
In order to comply with FCC RF exposure requirements this device must be installed to provide a separation distance of 5 mm
or greater between this device and the user.
ISED Regulatory and User Information
ISED ID 23763−RSL10SIP
HVIN RSL10SIP
This device contains licence−exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic
Development Canada’s licence−exempt RSS(s). Operation is subject to the following two conditions:
(1) This device may not cause interference.
(2) This device must accept any interference, including interference that may cause undesired operation of the device.
L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences et
Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux
conditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillage
radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.
Module Usage Conditions
A product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wording
such as: “Contains IC: 23763−RSL10SIP”
The label of the host device shall also contain the following statement. When this is not possible, the information shall be
included in the User Manual of the host device:
“This device contains licence−exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic
Development Canada’s licence−exempt RSS(s). Operation is subject to the following two conditions:
(1) This device may not cause interference.
(2) This device must accept any interference, including interference that may cause undesired operation of the device.”
The transmitter module may not be co−located with any other transmitter or antenna.
Un produit contenant le module RSL10SIP devra porter une étiquette du dispositif qui fait référence au module inclus.
L’étiquette du dispositif devra utiliser un libellé tel que: “Contient IC: 23763−RSL10SIP”
L’étiquette du dispositif devra également inclure la déclaration ci−dessous. Si cela n’est pas possible, cette information devra
être précisée dans le manuel de l’utilisateur:
L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences et
Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux
conditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillage
radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.
Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne.
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16
RSL10 SIP
WARNING: RF Exposure Compliance
In order to comply with ISED RF exposure requirements this device must be installed to provide a separation distance of 7 mm
or greater between this device and the user.
Afin de se conformer aux exigences d’exposition ISDE RF, cet appareil doit être installé pour fournir une distance de séparation
de 7 mm ou plus entre cet appareil et l’utilisateur.
Korean Regulatory and User Information
특정출 (터통
템 )
제 조 자 (제조자): onsemi
제 조
(지): 캐
제 품 (제품): NCH−RSL10−101S51−ACG
(): RSL10SIP
제조 (자): 중
장치 전화, Wi−Fi 투 장치 ! 통 장치" #$ %접한 장&' ( 할 )$ *작 +
-킬 ./0 123.
해5 67 전파혼 ./0 1-89 ;?@ '7 할 A BC.
The following ID information needs to be added to the product package (application and user documentation).
Korean KC Mark and Identifier as shown below. Height of KC mark is 5mm minimum. Colour preference is Navy (5PB 2/8
color according to KS A 0062). Acceptable other colours are black, gold and silver. Other colours may only be used if preferred
colours are not legible for the mark. The conformity assessment certification number is to be near the KC mark. (usually below).
R-CRM-oNs-RSL10SIP
European Regulatory and User Information
This device complies with the essential requirements of the Radio Equipment Directive 2014/53/EU. The following ID
information needs to be added to the product package (application and user documentation).
Japanese Regulatory and User Information
The following ID information needs to be added to the product package (application and user documentation).
ID (209−J00320) and must be combined with the Giteki (MIC) Mark as specified below.
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17
RSL10 SIP
Development Tools
Export Control Classification Number (ECCN)
RSL10 is supported by a full suite of comprehensive tools
including:
• An easy−to−use development board
• Software Development Kit (SDK) including an Oxygen
Eclipse−based development environment, Bluetooth
protocol stacks, sample code, libraries, and
documentation
The ECCN designation for RSL10 is 5A991.g.
Company or Product Inquiries
For more information about onsemi products or services
visit our Web site at www.onsemi.com.
For sales or technical support, contact your local
representative or authorized distributor.
Bluetooth is a registered trademark of Bluetooth SIG.
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries).
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18
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP51 8x6
CASE 127EY
ISSUE B
DATE 30 JUN 2020
GENERIC
MARKING DIAGRAM*
XXXXXXXX
XXXXXXXX
AWLYWG
DOCUMENT NUMBER:
DESCRIPTION:
98AON85298G
SIP51 8x6
A
WL
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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