NCL30082
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED Lighting
with Thermal Fold-back
The NCL30082 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device supports analog/digital dimming as well as
thermal current fold−back. While the NCL30082 has integrated fixed
overvoltage protection, the designer has the flexibility to program a
lower OVP level.
www.onsemi.com
8
8
1
1
Micro8
DM SUFFIX
CASE 846A
SOIC−8
D SUFFIX
CASE 751
MARKING DIAGRAMS
8
AAx
AYWG
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Quasi−resonant Peak Current−mode Control Operation
Primary Side Sensing (no optocoupler needed)
Wide VCC Range
Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate
Clamp
Precise LED Constant Current Regulation ±1% Typical
Line Feed−forward for Enhanced Regulation Accuracy
Low LED Current Ripple
250 mV ±2% Guaranteed Voltage Reference for Current Regulation
~0.9 Power Factor with Valley Fill Input Stage
Low Start−up Current (13 mA typ.)
Analog or Digital Dimming
Thermal Fold−back
Wide Temperature Range of −40 to +125°C
Pb−Free, Halide−Free MSL1 Product
Robust Protection Features
♦ Over Voltage / LED Open Circuit Protection
♦ Over Temperature Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Pin Fault Detection
♦ Latched and Auto−recoverable Versions
♦ Brown−out
♦ VCC Under Voltage Lockout
♦ Thermal Shutdown
These Devices are Pb−Free and Halogen Free/BFR Free
Typical Applications
January, 2015 − Rev. 5
AAx
= Specific Device Code
x
= C, D or H
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
8
L30082x
ALYW
G
1
L30082x = Specific Device Code
x
= B, B1, B2, B3, D
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
1
SD
ZCD
CS
GND
DIM
VIN
VCC
DRV
(Top View)
ORDERING INFORMATION
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
© Semiconductor Components Industries, LLC, 2015
1
See detailed ordering and shipping information on page 33 of
this data sheet.
1
Publication Order Number:
NCL30082/D
NCL30082
.
.
Aux
.
VDIM
1
8
2
7
3
6
4
5
Figure 1. Typical Application Schematic for NCL30082
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
SD
Thermal Fold−back
and shutdown
Connecting an NTC to this pin allows reducing the output current down to 50%
of its fixed value before stopping the controller. A Zener diode can also be
used to pull−up the pin and stop the controller for adjustable OVP protection
2
ZCD
Zero Crossing Detection
3
CS
Current sense
4
GND
−
5
DRV
Driver output
6
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage.
7
VIN
Input voltage sensing
Brown−Out
This pin observes the HV rail and is used in valley selection. This pin also
monitors and protects for low mains conditions.
8
DIM
Analog / PWM dimming
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the primary peak current
The controller ground
The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suitable to effectively drive a broad range of power MOSFETs.
This pin is used for analog or PWM dimming control. An analog signal than
can be varied between VDIM(EN) and VDIM100 can be used to vary the current,
or a PWM signal with an amplitude greater than VDIM100.
www.onsemi.com
2
NCL30082
CS_shorted Enable
Over Voltage
Protection
Aux_SCP
Fault
Management
Over Temperature
Protection
SD
Thermal
Foldback
Internal
Thermal
Shutdown
VTF
ZCD
CS
WOD_SCP
BO_NOK
VCC Over Voltage
Protection
VCC
Clamp
Circuit
offset_OK
Valley Selection
S
Aux_SCP
offset_OK
Leading
Edge
Blanking
Latch
VVIN VREF
Aux. Winding
Short Circuit Prot.
Line
Feedforward
VCC
VCC Management
VCC_max
Zero Crossing Detection
VVIN
OFF
UVLO
Ipkmax
Qdrv
VREF
VDD
STOP
Q
DRV
Qdrv
VVLY
R
VTF
STOP VREF
CS_reset
Constant−Current
Control
Dimming
Type
Detection
VDIMA
DIM
Ipkmax STOP
Enable
Enable VDIMA
Max. Peak
Current
Limit
VVIN
Ipkmax
VIN
VVIN
GND
CS Short
Protection
BO_NOK
CS_shorted
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
Note: CS Short Protection is disabled
Note: for NCL30082B1
Figure 2. Internal Circuit Architecture
www.onsemi.com
3
Brown−Out
NCL30082
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
VCC(MAX)
ICC(MAX)
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
Internally limited
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, VDRV (Note 1)
−500, +800
V
mA
VMAX
IMAX
Maximum voltage on low power pins (except pins ZCD, DIM, DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3, +5.5
−2, +5
V
mA
VZCD(MAX)
IZCD(MAX)
Maximum voltage for ZCD pin
Maximum current for ZCD pin
−0.3, +10
−2, +5
V
mA
VDIM(MAX)
Maximum voltage for DIM pin
−0.3, +10
V
RθJA
Thermal Resistance, Junction−to−Ambient (Note 4)
Micro8 version
SOIC−8 version
228
180
YJC
Thermal Characterization Parameter, Junction−to−Case Top
Micro8 version
SOIC−8 version
50
45
°C/W
TJ(MAX)
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
°C/W
Storage Temperature Range
−60 to +150
°C
ESD Capability, HBM model (Note 2)
4
kV
ESD Capability, MM model (Note 2)
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
4. With a 100 mm2, 2 oz copper area based on JEDEC EIA/JESD51-3 board design.
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Test Condition
Symbol
Min
Typ
Max
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(HYS)
VCC(reset)
16
8.2
8
3.5
18
8.8
–
4.5
20
9.4
–
5.5
Over Voltage Protection
VCC OVP threshold
VCC(OVP)
26
28
30
V
VCC(off) noise filter
VCC(reset) noise filter−
tVCC(off)
tVCC(reset)
–
–
5
20
–
–
ms
ICC(start)
–
13
30
mA
ICC(sFault)
–
46
60
Description
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal logic reset
V
Startup current
Startup current in fault mode
Supply Current
Device Disabled/Fault
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
mA
mA
VCC > VCC(off)
Fsw = 65 kHz
CDRV = 470 pF,
Fsw = 65 kHz
ICC1
ICC2
ICC3
0.8
–
–
1.2
2.3
2.7
1.4
4.0
5.0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design.
www.onsemi.com
4
NCL30082
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Maximum Internal current limit
VILIM
Leading Edge Blanking Duration for VILIM
(Tj = −25°C to 125°C) (Not applicable for NCL30082D)
tLEB
Leading Edge Blanking Duration for VILIM
(Tj = −40°C to 125°C)
Unit
0.95
1
1.05
V
250
300
350
ns
tLEB
240
300
350
ns
CURRENT SENSE
Ibias
–
0.02
–
mA
tILIM
–
50
150
ns
VCS(stop)
1.35
1.5
1.65
V
tBCS
–
120
–
ns
Blanking time for CS to GND short detection VpinVIN = 1 V
tCS(blank1)
6
–
12
ms
Blanking time for CS to GND short detection VpinVIN = 1 V
NCL30082D
tCS(blank1)D
8
10.7
14
ms
Input Bias Current
DRV high
Propagation delay from current detection to gate off−state
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for VCS(stop)
Blanking time for CS to GND short detection VpinVIN = 3.3 V
tCS(blank2)
2
–
4
ms
Blanking time for CS to GND short detection VpinVIN = 3.3 V
NCL30082D
tCS(blank2)D
2.6
3.6
4.6
ms
Drive Resistance
DRV Sink
DRV Source
RSNK
RSRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 6)
DRV Source (Note 6)
ISNK
ISRC
–
–
500
300
–
–
GATE DRIVE
W
mA
Rise Time (10% to 90%)
CDRV = 470 pF
tr
–
40
–
ns
Fall Time (90% to 10%)
CDRV = 470 pF
tf
–
30
–
ns
DRV Low Voltage
VCC = VCC(off)+0.2 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(low)
8
–
–
V
DRV High Voltage
VCC = 30 V
CDRV = 470 pF,
RDRV = 33 kW
VDRV(high)
10
12
14
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design.
www.onsemi.com
5
NCL30082
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
ZCD threshold voltage
VZCD increasing
VZCD(THI)
25
45
65
mV
ZCD threshold voltage (Note 6)
VZCD decreasing
VZCD(THD)
5
25
45
mV
ZCD hysteresis (Note 6)
VZCD increasing
VZCD(HYS)
10
–
–
mV
VZCD(short)
0.8
1
1.2
V
tOVLD
70
90
110
ms
trecovery
3
4
5
s
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
VCH
VCL
–
−0.9
9.5
−0.6
–
−0.3
VZCD decreasing
tDEM
–
–
150
ns
tPAR
–
20
–
ns
tBLANK
2.25
3
3.75
ms
tBLANKB2
1.2
1.6
2.0
ms
tTIMO
5
6.5
8
ms
ZERO VOLTAGE DETECTION CIRCUIT
Threshold voltage for output short circuit or aux. winding
short circuit detection
Short circuit detection Timer
VZCD < VZCD(short)
Auto−recovery timer duration
Input clamp voltage
High state
Low state
V
Propagation Delay from valley detection to DRV high
Equivalent time constant for ZCD input (Note 6)
Blanking delay after on−time
Blanking delay after on−time NCL30082B2 and
NCL30082B3
Timeout after last demag transition
CONSTANT CURRENT CONTROL
Reference Voltage at TJ = 25°C
VREF
245
250
255
mV
Reference Voltage TJ = −40°C to 125°C
VREF
242.5
250
257.5
mV
Reference Voltage NCL30082D (TJ = 25°C)
VREFD
495
500
505
mV
Reference Voltage NCL30082D (TJ = 0°C to 85°C)
VREFD
492
500
508
mV
Reference Voltage NCL30082D (TJ = −40°C to 125°C)
VREFD
488
500
512
mV
Reference Voltage NCL30082B3 (TJ = 25°C)
VREFB3
329
333
337
mV
Reference Voltage NCL30082B3 (TJ = 0°C to 85°C)
VREFB3
325
333
341
mV
Reference Voltage NCL30082B3 (TJ = −40°C to 125°C)
VREFB3
321
333
345
mV
50% reference voltage (for thermal foldback)
VREF50
–
125
–
mV
25% reference voltage (for thermal foldback) NCL30082D
VREF25D
−
125
−
mV
Current sense lower threshold for detection of the
leakage inductance reset time
VCS(low)
30
55
80
mV
KLFF
15
17
19
mA/V
VpinVIN = 4.5 V
Ioffset(MAX)
67.5
76.5
85.5
mA
VREF value below which the offset current source is turned off
VREF decreases
VREF(off)
–
37.5
–
mV
VREF value above which the offset current source is turned on
VREF increases
VREF(on)
–
50
–
mV
Threshold for line range detection Vin increasing
(1st to 2nd valley transition for VREF > 0.75 V)
VVIN increases
VHL
2.28
2.4
2.52
V
Threshold for line range detection Vin decreasing
(2nd to 1st valley transition for VREF > 0.75 V)
VVIN decreases
VLL
2.18
2.3
2.42
V
tHL(blank)
15
25
35
ms
LINE FEED−FORWARD
VVIN to ICS(offset) conversion ratio
Offset current maximum value
VALLEY SELECTION
Blanking time for line range detection
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design.
www.onsemi.com
6
NCL30082
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
Valley thresholds
1st to 2nd valley transition at LL and 2nd to 3rd valley HL
2nd to 1st valley transition at LL and 3rd to 2nd valley HL
2nd to 4th valley transition at LL and 3rd to 5th valley HL
4th to 2nd valley transition at LL and 5th to 3rd valley HL
4th to 7th valley transition at LL and 5th to 8th valley HL
7th to 4th valley transition at LL and 8th to 5th valley HL
7th to 11th valley transition at LL and 8th to 12th valley HL
11th to 7th valley transition at LL and 12th to 8th valley HL
11th to 13th valley transition at LL and 12th to 15th valley HL
13th to 11th valley transition at LL and 15th to 12th valley HL
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VREF decreases
VREF increases
VVLY1−2/2−3
VVLY2−1/3−2
VVLY2−4/3−5
VVLY4−2/5−3
VVLY4−7/5−8
VVLY7−4/8−5
VVLY7−11/8−12
VVLY11−7/12−8
VVLY11−13/12−15
VVLY13−11/15−12
177.5
185.0
117.5
125.0
–
–
–
–
–
–
187.5
195.0
125.0
132.5
75.0
82.5
37.5
50.0
15.0
20.0
197.5
205.0
132.5
140.0
–
–
–
–
–
–
DIM pin voltage for zero output current (OFF voltage)
VDIM(EN)
0.66
0.7
0.74
V
DIM pin voltage for maximum output current
VDIM100
2.25
2.45
2.65
V
Dimming range
VDIM(range)
–
1.75
–
V
Clamping voltage for DIM pin
VDIM(CLP)
–
7.8
–
V
Dimming pin pull−up current source
IDIM(pullup)
–
280
–
nA
Reference current for direct connection of an NTC (Note 6)
IOTP(REF)
80
85
90
SD pin voltage at which thermal fold−back starts
VTF(start)
0.9
1
1.1
V
SD pin voltage at which thermal fold−back stops
(Iout = 50% Iout(nom))
VTF(stop)
0.64
0.68
0.72
V
SD pin voltage at which thermal fold−back stops
NCL30082D (Iout = 25% Iout(nom))
VTF(stop)D
0.86
0.90
0.94
V
VALLEY SELECTION
mV
DIMMING SECTION
THERMAL FOLD−BACK AND OVP
IOTP(REF)
80
85
90
mA
VOTP(off)
0.47
0.5
0.53
V
VOTP(off)D
0.81
0.85
0.89
V
VOTP(on)
0.64
0.68
0.72
V
SD pin level at which controller re−start switching after OTP
detection NCL30082D
VOTP(on)D
0.86
0.9
0.94
V
SD pin Over temperature Protection Hysteresis NCL30082D
VOTP(hys)D
15
50
100
mV
Reference current for direct connection of an NTC
Fault detection level for OTP
VSD decreasing
Fault detection level for OTP NCL30082D
SD pin level at which controller re−start switching after OTP
detection
VSD increasing
VTF(start) over IOTP(REF) ratio (Note 5)
TJ = +25°C to +125°C
RTF(start)
10.8
11.7
12.6
kW
VTF(stop) over IOTP(REF) ratio (Note 5)
TJ = +25°C to +125°C
RTF(stop)
7.4
8.0
8.6
kW
VOTP(off) over IOTP(REF) ratio (Note 5)
TJ = +25°C to +125°C
ROTP(off)
5.4
5.9
6.4
kW
VOTP(on) over IOTP(REF) ratio (Note 5)
TJ = +25°C to +125°C
ROTP(on)
7.4
8.0
8.6
kW
VTF(stop) over IOTP(REF) ratio NCL30082D (Note 5)
TJ = +25°C to +125°C
RTF(stop)D
9.9
10.5
11.1
kW
VOTP(off) over IOTP(REF) ratio NCL30082D (Note 5)
TJ = +25°C to +125°C
ROTP(off)D
9.4
10.0
10.6
kW
VOTP(on) over IOTP(REF) ratio NCL30082D (Note 5)
TJ = +25°C to +125°C
ROTP(on)D
9.9
10.5
11.1
kW
5. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design.
www.onsemi.com
7
NCL30082
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V;
For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Description
Test Condition
Symbol
Min
Typ
Max
Unit
tOTP(start)
180
–
300
ms
THERMAL FOLD−BACK AND OVP
Timer duration after which the controller is allowed to start
pulsing
Clamped voltage (SD pin left open)
SD pin open
Clamp series resistor
SD pin detection level for OVP
VSD increasing
Delay before OVP or OTP confirmation (OVP and OTP)
VSD(clamp)
1.13
1.35
1.57
V
RSD(clamp)
–
1.6
–
kW
VOVP
2.35
2.5
2.65
V
TSD(delay)
15
30
45
ms
TSHDN
130
150
170
°C
TSHDN(HYS)
–
50
–
°C
VBO(on)
0.90
1
1.10
V
THERMAL SHUTDOWN
Thermal Shutdown (Note 6)
Device switching
(FSW around 65 kHz)
Thermal Shutdown Hysteresis (Note 6)
BROWN−OUT
Brown−Out ON level (IC start pulsing)
VSD increasing
Brown−Out OFF level (IC shuts down)
VSD decreasing
VBO(off)
0.85
0.9
0.95
V
BO comparators delay
tBO(delay)
–
30
–
ms
Brown−Out blanking time
tBO(blank)
35
50
65
ms
Brown−Out blanking time NCL30082D
tBO(blank)D
10.5
15
19.5
ms
IBO(bias)
−250
–
250
nA
Brown−out pin bias current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design.
www.onsemi.com
8
NCL30082
TYPICAL CHARACTERISTICS
8.90
18.15
8.85
18.10
8.80
VCC(off) (V)
VCC(on) (V)
18.20
18.05
8.75
18.00
8.70
17.95
8.65
17.90
−40
−20
0
20
40
60
80
8.60
−40
120
100
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
27.80
18
17
27.75
ICC(start) (mA)
VCC(OVP) (V)
16
27.70
27.65
27.60
15
14
13
12
27.55
11
27.50
−40
−20
0
20
40
60
80
100
10
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. ICC(start) vs. Junction Temperature
1.30
52
1.28
50
1.24
48
ICC1 (mA)
ICC(sFault) (mA)
1.26
46
44
1.22
1.20
1.18
1.16
42
1.14
40
−40
−20
0
20
40
60
80
100
1.12
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC(sFault) vs. Junction Temperature
Figure 8. ICC1 vs. Junction Temperature
www.onsemi.com
9
120
NCL30082
TYPICAL CHARACTERISTICS
2.40
2.85
2.80
2.35
2.75
ICC3 (mA)
ICC2 (mA)
2.30
2.25
2.20
2.70
2.65
2.60
2.55
2.15
−20
0
20
40
60
80
100
2.45
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. ICC2 vs. Junction Temperature
Figure 10. ICC3 vs. Junction Temperature
1.000
1.495
0.995
1.490
0.990
0.985
0.980
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VCS(stop) (V)
VILIM (V)
2.10
−40
2.50
120
1.485
1.480
−20
0
20
40
60
80
100
1.475
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VILIM vs. Junction Temperature
Figure 12. VCS(stop) vs. Junction Temperature
305
1.010
303
1.005
301
VZCD(short) (V)
tLEB (ns)
299
297
295
293
291
289
287
285
−40
1.000
0.995
0.990
0.985
−20
0
20
40
60
80
100
0.980
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. tLEB vs. Junction Temperature
Figure 14. VZCD(short) vs. Junction
Temperature
www.onsemi.com
10
120
NCL30082
TYPICAL CHARACTERISTICS
3.20
7.1
7.0
6.9
tTIMO (ms)
tBLANK (ms)
3.15
3.10
6.8
6.7
3.05
6.6
−20
0
20
40
60
80
6.5
−40
120
100
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. tBLANK vs. Junction Temperature
Figure 16. tTIMO vs. Junction Temperature
255
55.0
254
54.5
253
54.0
252
251
250
249
−40
53.5
53.0
−20
0
20
40
60
80
100
52.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VREF vs. Junction Temperature
Figure 18. VCS(low) vs. Junction Temperature
16.60
37.6
16.55
37.5
16.50
37.4
16.45
16.40
16.35
16.30
−40
120
52.5
VREF(off) (mV)
KLFF (mA/V)
−20
TJ, JUNCTION TEMPERATURE (°C)
VCS(low) (mV)
VREF (mV)
3.00
−40
37.3
37.2
37.1
−20
0
20
40
60
80
100
37.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. KLFF vs. Junction Temperature
Figure 20. VREF(off) vs. Junction Temperature
www.onsemi.com
11
NCL30082
TYPICAL CHARACTERISTICS
49.0
2.400
48.5
2.395
47.5
2.390
47.0
VHL (V)
VREF(on) (mV)
48.0
46.5
46.0
2.385
2.380
45.5
45.0
2.375
44.5
44.0
−40
−20
0
20
40
60
80
100
2.370
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. VREF(on) vs. Junction Temperature
Figure 22. VHL vs. Junction Temperature
120
28.0
2.300
2.295
tHL(BLANK) (ms)
27.5
VLL (V)
2.290
2.285
2.280
27.0
26.5
2.275
−20
0
20
40
60
80
100
26.0
−40
120
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VLL vs. Junction Temperature
Figure 24. tHL(BLANK) vs. Junction Temperature
187.0
198
186.5
197
186.0
185.5
185.0
184.5
184.0
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
VVLY2−1/3−2 (mV)
VVLY1−2/2−3 (mV)
2.270
−40
196
195
194
193
192
−20
0
20
40
60
80
100
191
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. VVLY1−2/2−3 vs. Junction
Temperature
Figure 26. VVLY2−1/3−2 vs. Junction
Temperature
www.onsemi.com
12
120
NCL30082
TYPICAL CHARACTERISTICS
124.5
135
VVLY4−2/5−3 (mV)
136
VVLY2−4/3−5 (mV)
125.0
124.0
123.5
123.0
122.5
−20
0
20
40
60
80
100
132
130
−40
120
20
40
60
80
100
Figure 27. VVLY2−4/3−5 vs. Junction
Temperature
Figure 28. VVLY4−2/5−3 vs. Junction
Temperature
87
75.5
86
75.0
74.5
74.0
120
85
84
83
82
81
−20
0
20
40
60
80
100
80
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. VVLY4−7/5−8 vs. Junction
Temperature
Figure 30. VVLY7−4/8−5 vs. Junction
Temperature
50
37.6
49
37.5
48
VVLY11−7/12−8 (mV)
37.7
37.4
37.3
37.2
37.1
37.0
−40
0
TJ, JUNCTION TEMPERATURE (°C)
76.0
73.0
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
73.5
VVLY7−11/8−12 (mV)
133
131
VVLY7−4/8−5 (mV)
VVLY4−7/5−8 (mV)
122.0
−40
134
120
47
46
45
44
−20
0
20
40
60
80
100
43
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. VVLY7−11/8−12 vs. Junction
Temperature
Figure 32. VVLY11−7/12−8 vs. Junction
Temperature
www.onsemi.com
13
120
NCL30082
TYPICAL CHARACTERISTICS
15.05
20.5
15.00
20.0
VVLY13−11/15−12 (mV)
21.0
VVLY11−13/12−15 (mV)
15.10
14.95
14.90
14.85
14.80
19.0
18.5
18.0
17.5
14.75
14.70
−40
−20
0
20
40
60
80
100
17.0
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. VVLY11−13/12−15 vs. Junction
Temperature
Figure 34. VVLY13−11/15−12 vs. Junction
Temperature
0.710
2.46
0.705
2.45
VDIM(100) (V)
VDIM(EN) (V)
19.5
0.700
0.695
120
2.44
2.43
0.690
−40
−20
0
20
40
60
80
100
2.42
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. VDIM(EN) vs. Junction Temperature
Figure 36. VDIM(100) vs. Junction Temperature
88.0
4.55
87.5
4.50
86.5
trecovery (s)
tOVLD (ms)
87.0
86.0
85.5
85.0
4.45
4.40
4.35
84.5
84.0
−40
−20
0
20
40
60
80
100
4.30
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 37. tOVLD vs. Junction Temperature
Figure 38. trecovery vs. Junction Temperature
www.onsemi.com
14
NCL30082
TYPICAL CHARACTERISTICS
2.500
86.5
2.495
86.0
85.5
IOTP(ref) (mA)
VOVP (V)
2.490
2.485
2.480
85.0
84.5
84.0
2.475
83.5
2.470
−40
−20
0
20
40
60
80
100
83.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 39. VOVP vs. Junction Temperature
Figure 40. IOTP(ref) vs. Junction Temperature
0.690
0.997
0.995
VTF(start) (V)
VOTP(on), VTF(stop) (V)
0.688
0.686
0.684
0.991
0.989
0.682
0.987
0.680
−40
−20
0
20
40
60
80
100
0.985
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 41. VOTP(on), VTF(stop) vs. Junction
Temperature
Figure 42. VTF(start) vs. Junction Temperature
0.994
0.906
0.992
0.904
0.990
VBO(off) (V)
VBO(on) (V)
0.993
0.988
0.902
0.900
0.986
0.898
0.984
0.982
−40
−20
0
20
40
60
80
100
0.896
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 43. VBO(on) vs. Junction Temperature
Figure 44. VBO(off) vs. Junction Temperature
www.onsemi.com
15
NCL30082
TYPICAL CHARACTERISTICS
504
130
503
129
128
VREF25D (mV)
VREFD (mV)
502
501
500
499
127
126
125
124
123
498
122
497
496
−40
−20
0
20
40
60
80
100
121
120
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 45. VREFD vs. Junction Temperature
Figure 46. VREF25D vs. Junction Temperature
0.900
0.850
0.898
VOTP(on)D, VTF(stop)D (V)
VOTP(off)D (V)
0.848
0.846
0.844
0.842
0.896
0.894
0.892
0.890
0.888
−20
0
20
40
60
80
100
0.886
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 47. VOTP(off)D vs. Junction Temperature
Figure 48. VOTP(on)D, VTF(stop)D vs. Junction
Temperature
48.2
15.5
48.0
15.4
47.8
15.3
tBO(BLANK)D (ms)
VOTP(HYS)D (mV)
0.840
−40
47.6
47.4
47.2
47.0
46.8
−40
15.2
15.1
15.0
14.9
−20
0
20
40
60
80
100
14.8
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 49. VOTP(HYS)D vs. Junction
Temperature
Figure 50. tBO(BLANK)D vs. Junction
Temperature
www.onsemi.com
16
120
NCL30082
TYPICAL CHARACTERISTICS
56.0
tBO(BLANK) (ms)
55.5
55.0
54.5
54.0
53.5
53.0
52.5
−40
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 51. tBO(BLANK) vs. Junction Temperature
APPLICATION INFORMATION
The NCL30082 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current of the flyback converter without
using any opto−coupler or measuring directly the secondary
side current.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30082 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to compensate
for the leakage inductance of the transformer and allow
accurate control of the secondary side current.
• Line Feed−forward: compensation for possible
variation of the output current caused by system slew
rate variation.
• Open LED protection: if the voltage on the VCC pin
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting switching.
• Thermal Fold−back / Over Temperature / Over
Voltage Protection: by combining a dual threshold on
the SD pin, the controller allows the direct connection
of an NTC to ground plus a Zener diode to a monitored
voltage. The temperature is monitored and the output
current is linearly reduced in the event that the
•
•
•
•
•
temperature exceeds a prescribed level. If the
temperature continues to increase, the current will be
further reduced until the controller is stopped. The
control will automatically restart if the temperature is
reduced. This pin can implement a programmable OVP
shutdown that can also auto−restart the device.
Brown−Out: the controller includes a brown−out
circuit which safely stops the controller in case the
input voltage is too low. The device will automatically
restart if the line recovers.
Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold VILIM, the
MOSFET is turned off for the rest of the switching
cycle.
Winding Short−Circuit Protection: an additional
comparator with a short LEB filter (tBCS) senses the CS
signal and stops the controller if VCS reaches 1.5 x
VILIM. For noise immunity reasons, this comparator is
enabled only during the main LEB duration tLEB.
Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. The
auto−restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version (A
suffix), the controller is latched as long as VCC stays
above the VCC(reset) threshold.
Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
www.onsemi.com
17
NCL30082
Constant Current Control
Figure 53 portrays the primary and secondary current of
a flyback converter in discontinuous conduction mode
(DCM). Figure 52 shows the basic circuit of a flyback
converter.
Transformer
Vbulk
Lleak
Cclp
Nsp
Rclp
Vout
.
Lp
.
Clamping
network
DRV
Clump
Rsense
Figure 52. Basic Flyback Converter Schematic
When the diode conducts, the secondary current decreases
linearly from ID,pk to zero. When the diode current has
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (Lp+Lleak)
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in flyback mode. Thus, by looking
at the auxiliary winding voltage, we can detect the end of the
conduction time of secondary diode. The constant current
control block picks up the leakage inductor current, the end
of conduction of the output rectifier and controls the drain
current to maintain the output current constant.
We have:
During the on−time of the MOSFET, the bulk voltage
Vbulk is applied to the magnetizing and leakage inductors Lp
and Lleak and the current ramps up.
When the MOSFET is turned−off, the inductor current
first charges Clump. The output diode is off until the voltage
across Lp reverses and reaches:
N spǒV out ) V fǓ
(eq. 1)
The output diode current increase is limited by the leakage
inductor. As a consequence, the secondary peak current is
reduced:
I D,pk t
I L,pk
N sp
(eq. 2)
I out +
The diode current reaches its peak when the leakage inductor
is reset. Thus, in order to accurately regulate the output
current, we need to take into account the leakage inductor
current. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
is connected to Rsense instead of the bulk voltage Vbulk.
Then, by reading the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 53).
V REF
2N spR sense
(eq. 3)
The output current value is set by choosing the sense
resistor:
R sense +
V ref
2N spI out
(eq. 4)
From Equation 3, the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
www.onsemi.com
18
NCL30082
IL,pk
NspID,pk
Ipri(t)
Isec(t)
time
t1
t2
ton
tdemag
Vaux(t)
time
Figure 53. Flyback Currents and Auxiliary Winding Voltage in DCM
Internal Soft−Start
At startup or after recovering from a fault, there is a small
internal soft−start of 40 ms.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 54 shows a soft−start simulation example for a 9 W
LED power supply.
www.onsemi.com
19
NCL30082
16.0
(V)
12.0
1
Vout
2
I out
4
VControl
3
VCS
8.00
4.00
0
800m
(A)
600m
400m
200m
0
800m
(V)
600m
400m
200m
0
604u
1.47m
2.34m
time in seconds
3.21m
4.07m
Figure 54. Startup Simulation Showing the Natural Soft−start
Cycle−by−Cycle Current Limit
Winding and Output Diode Short−Circuit Protection
When the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of the
switching cycle (Figure 55).
In parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a higher
threshold (1.5 V typical) is able to sense winding
short−circuit and immediately stops the DRV pulses. The
controller goes into auto−recovery mode in version B, B1,
B2, B3 and D.
In version A, the controller is latched. In latch mode, the
DRV pulses stop and VCC ramps up and down. The circuit
un−latches when VCC pin voltage drops below VCC(reset)
threshold.
www.onsemi.com
20
NCL30082
S
DRV
Q
Q
aux
Vdd
latch
CS
R
LEB1
Rsense
+
Vcontrol
Vcc
management
PWMreset
VCC
−
+
VCCstop
UVLO
grand
8_HICC
reset
Ipkmax
−
VILIMIT
OVP
LEB2
+
STOP
OVP
WOD_SCP
latch
−
S
VCS(stop)
Q
Q
OFF WOD_SCP
S
Q
Q
R
R
grand
reset
from Fault Management Block
8_HICC
Figure 55. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
Thermal Fold−back and Over Voltage / Over
Temperature Protection
constant current control VREF is decreased proportionally to
VSD. When VSD reaches VTF(stop), VREF is clamped to
VREF50, corresponding to 50% of the nominal output current
(versions A, B, B1, B2, B3). For the NCL30082D, the output
current is decreased to 25% of the nominal output current.
If VSD drops below VOTP, the controller enters into the
auto−recovery fault mode for version B, B1, B2, B3 and D
meaning that the 4−s timer is activated. The controller will
re−start switching after the 4−s timer has elapsed and when
VSD > VOTP(on) to provide some temperature hysteresis.
For version A, this protection is latched: reset occurs when
VCC < VCC(reset).
The thermal fold−back circuit reduces the current in the
LED string when the ambient temperature exceeds a set
point. The current is gradually reduced to 50% of its nominal
value if the temperature continues to rise. (Figure 56). The
thermal foldback starting temperature depends of the
Negative Coefficient Temperature (NTC) resistor chosen by
the power supply designer.
Indeed, the SD pin allows the direct connection of an NTC
to sense the ambient temperature. When the SD pin voltage
VSD drops below VTF(start), the internal reference for the
Iout
Temperature increases
Temperature decreases
Temperature increases
Temperature decreases
Iout
Shutdown
50% Iout(nom)
25% Iout(nom)
VSD
VOTP(off)
VTF(stop)
VOTP(on)
Shutdown
Iout(nom)
Iout(nom)
VSD
VOTP(off)
VTF(start)
VTF(stop)
VOTP(on)
VTF(start)
Figure 56. Output Current Reduction vs. SD Pin
Voltage for NCL30082 Versions A, B, B1, B2, B3
Figure 57. Output Current Reduction vs. SD Pin
Voltage for NCL30082D
www.onsemi.com
21
NCL30082
At startup, when VCC reaches VCC(on), the controller is
not allowed to start pulsing for at least 180 ms in order to
allow the SD pin voltage to reach its nominal value if a
filtering capacitor is connected to the SD pin. This is to avoid
flickering of the LED light in case of over temperature.
VOVP
VCC
Vdd
noise delay
−
Dz
IOTP(REF)
OVP
+
S
Q
SD
OFF
Q
OTP_Timer end
Rclamp
Clamp
R
OTP
−
4−s Timer
+
NTC
noise delay
Vclamp
(OTP latched for version A)
VOTP
0.5 V if OTP low
0.7 V if OTP high
S
Q
Latch
Q
VTF
R
VCCreset
Figure 58. Thermal Fold−back and OVP/OTP Circuitry
In the case of excess voltage, the Zener diode starts to
conduct and inject current into the internal clamp resistor
Rclamp thus causing the pin SD voltage to increase. When
this voltage reaches the OVP threshold (2.5 V typ.), the
controller shuts−down and waits for at least 4 seconds before
restarting switching.
www.onsemi.com
22
NCL30082
VCC
VCC(on)
VCC(off)
VCC > VCC(on):
DRV pulses restart
VCC(reset)
VDRV
4−s Timer
VSD
VSD > VOVP:
controller stops
switching
4−s timer has elapsed:
waiting for VCC > VCC(on)
to restart DRV pulses
VOVP
VSD(clamp)
Vout
Figure 59. OVP with SD Pin Chronograms
www.onsemi.com
23
NCL30082
VCC
VCC(on)
VCC(off)
VCC(reset)
VDRV
VSD > VTF(stop) and
VCC > VCC(on):
DRV pulses restart
4−s Timer
VSD < VOTP(off):
controller stops
switching
VSD
4−s timer has elapsed
but VSD < VTF(stop)
≥ no restart
VTF(start)
VTF(stop)
VOTP(off)
Iout
Figure 60. Thermal Fold−back / OTP Chronograms
PWM or Linear Dimming Detection
If a voltage lower than VDIM(EN) is applied to the DIM pin,
the DRV pulses are disabled. Thus, for PWM dimming, a
PWM signal with a low state value < VDIM(EN) and a high
state value > VDIM100 should be applied.
The DIM pin is pulled up internally by a small current
source. Thus, if the pin is left open, the controller is able to
start.
The pin DIM allows implementing either linear dimming
or PWM dimming of the LED light.
If the power supply designer apply an analog signal
varying from VDIM(EN) to VDIM100 to the DIM pin, the
output current will increase or decrease proportionally to the
voltage applied. For VDIM = VDIM100, the power supply
delivers the maximum output current.
VDIM
Analog dimming
PWM dimming
VDIM100
100% Iout
VDIM(EN)
0% Iout
Figure 61. Pin DIM Chronograms
Note:
• If a PWM voltage with a high state value < VDIM100 is
applied to the DIM pin, the product will still be in
PWM dimming mode, but the reference voltage will be
decreased according to VDIM. This allows increased
dynamic range on the dimming control pin.
• Thermal Foldback and dimming: if the IC is in a
dimming state and the thermal foldback (TF) is
activated, the output current is further reduced to a
value equal to Dimming*TF.
www.onsemi.com
24
NCL30082
VCC Over Voltage Protection (Open LED Protection)
In the NCL30082, when the VCC voltage reaches the
VCC(OVP) threshold, the controller stops the DRV pulses and
the 4−s timer starts counting. The IC re−start pulsing after
the 4−s timer has elapsed and when VCC ≥ VCC(on).
If no output load is connected to the LED power supply,
the controller must be able to safely limit the output voltage
excursion.
40.0
V CC(OVP)
(V)
30.0
1 V CC
V CC(on)
20.0
10.0
VCC(off)
0
40.0
(V)
30.0
2 Vout
20.0
10.0
0
800m
(A)
600m
400m
200m
3 I out
0
8.00
(V)
6.00
4 OVP
4.00
2.00
0
1.38
3.96
6.54
time in seconds
9.11
11.7
Figure 62. Open LED Protection Chronograms
Valley Lockout
or the output current set−point varies significantly. This
avoids valley jumping and the inherent noise caused by this
phenomenon.
The input voltage is sensed by the VIN pin (line range
detection in Figure 63). The internal logic selects the
operating valley according to VIN pin voltage, SD pin
voltage and DIM pin voltage.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
Quasi−square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30082 changes the valley as the input voltage
increases and as the output current set−point is varied
(dimming and thermal fold−back). This limits the switching
frequency excursion. Once a valley is selected, the
controller stays locked in the valley until the input voltage
www.onsemi.com
25
NCL30082
Vbulk
VIN
+
LLine
HLine
25−ms blanking time
−
2.4 V if LLine low
2.3 V if LLine high
Figure 63. Line Range Detector
Table 4. VALLEY SELECTION
VIN pin voltage for valley change
Iout value at which the
controller changes valley
(Iout decreasing)
0
100%
75%
50%
30%
15%
6%
0%
0
−LL−
2.3 V
−HL−
1st
2nd
2nd
3rd
4th
5th
7th
8th
11th
12th
13th
15th
−LL−
2.4 V
−HL−
VVIN increases
VIN pin voltage for valley change
www.onsemi.com
26
5V
100%
78%
53%
33%
20%
8%
0%
5V
Iout increases
Iout decreases
Iout value at which the
controller changes valley
(Iout increasing)
VVIN decreases
NCL30082
Zero Crossing Detection Block
the valleys. To avoid such a situation, the NCL30082
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the VZCD(THD) threshold
for 6.5 ms.
The time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the voltage on pin 1 crosses
below the VZCD(THD) internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
V ZCD
3
4
V ZCD(THD)
The 3rd valley
is validated
high
14
2nd, 3rd
low
12
The 3rd valley is not detected
by the ZCD comp
The 2nd valley is detected
By the ZCD comparator
high
15 ZCD comp
low
high
low
16
TimeOut
17
Clk
Time−out circuit adds a pulse to
account for the missing 3rd valley
high
low
Figure 64. Time−out Chronograms
Normally with this type of time−out function, in the event
the ZCD pin or the auxiliary winding is shorted, the
controller could continue switching leading to improper
regulation of the LED current. Moreover during an output
short circuit, the controller will strive to maintain constant
current operation.
To avoid these scenarios, a protection circuit consisting of
a comparator and secondary timer starts counting when the
ZCD voltage is below the VZCD(short) threshold. If this timer
reaches 90 ms, the controller detects a fault and shutdown.
The auto−restart version (B, B1, B2, D suffix) waits 4
seconds, then the controller restarts switching. In the latched
version (A suffix), the controller is latched as long as VCC
stays above the VCC(reset) threshold.
www.onsemi.com
27
NCL30082
Tblank
Time−Out
ZCD
+
Clock
VZCD(TH)
.
−
Tblank
+
VZCD(short)
−
90−ms
Timer
Enable_b
S
Q
Aux_SCP
Q
R
4−s Timer
Figure 65. ZCD Block Schematic
Line Feed−Forward
V CS(offset) + K LFFV pinVINR CS
Because of the propagation delays, the MOSFET is not
turned−off immediately when the current set−point is
reached. As a result, the primary peak current is higher than
expected and the output current increases. To compensate
the peak current increase brought by the propagation delay,
a positive voltage proportional to the line voltage is added
on the current sense signal. The amount of offset voltage can
be adjusted using the RCS resistor as shown in Figure 66.
(eq. 5)
The offset voltage is applied only during the MOSFET
on−time.
This offset voltage is removed at light load during
dimming when the output current drops below 15% of the
programmed output current.
Bulk rail
VDD
VIN
ICS(offset)
CS
RCS
Rsense
Q_drv
Offset_OK
Figure 66. Line Feed−Forward Schematic
www.onsemi.com
28
NCL30082
Brown−out
below 0.9 V for 50 ms nominal. For the NCL30082D, the
blanking time is reduced to 15 ms. Exiting a brown−out
condition overrides the hiccup on VCC (VCC does not wait
to reach VCC(off)) and the IC immediately goes into startup
mode (ICC = ICC(start)).
In order to protect the supply against a very low input
voltage, the NCL30082 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 1 V is applied to the VIN pin and
shuts−down if the VIN pin voltage decreases and stays
Vbulk
VIN
+
BO_NOK
Blanking time
−
1 V if BONOK high
0.9 V if BONOK low
Figure 67. Brown−out Circuit
160
(V)
120
VBulk
80.0
1
40.0
0
18.0
(V)
2
VCC(on)
16.0
14.0
VCC
12.0
VCC(off)
10.0
1.10
V BO(on)
(V)
900m
V BO(off)
700m
V pinVIN
500m
3
300m
8.00
BO Blanking Time
(V)
6.00
BO_NOK low
=> Startup mode
4.00
2.00
BO_NOK
4
0
46.1m
138m
231m
time in seconds
323m
Figure 68. Brown−Out Chronograms (Valley Fill circuit is used)
www.onsemi.com
29
415m
NCL30082
CS Pin Short Circuit Protection
Normally, if the CS pin or the sense resistor is shorted to
ground, the Driver will not be able to turn off, leading to
potential damage of the power supply. To avoid this, the
versions A, B, B1, B2, B3 and D feature a circuit to protect
the power supply against a short circuit of the CS pin. When
the MOSFET is on, if the CS voltage stays below VCS(low)
after the adaptive blanking timer has elapsed, the controller
shuts down and will attempt to restart on the next VCC
hiccup. In the NCL30082B1, this protection is disabled.
Adaptative
Blanking Time
VVIN
Q_drv
CS
−
+
S
VCS(low)
Q
CS_short
Q
R
UVLO
BO_NOK
Figure 69. CS Pin Short Circuit Protection Schematic
Fault Management
In this mode, the DRV pulses are stopped. The VCC
voltage decrease through the controller own consumption
(ICC1).
For the output diode short circuit protection, the CS pin
short circuit protection, the output / aux. winding short
circuit protection and the OVP2, the controller waits 4
seconds (auto−recovery timer) and then initiates a startup
sequence (VCC ≥ VCC(on)) before re−starting switching.
Latch Mode
This mode is activated by the output diode short−circuit
protection (WOD_SCP), the OTP and the Aux−SCP in
version A only.
In this mode, the DRV pulses are stopped and the
controller is latched. There are hiccups on VCC.
The circuit un−latches when VCC < VCC(reset).
OFF Mode
The circuit turns off whenever a major condition prevents
it from operating:
• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when VCC drops below
VCC(off) and remains high until VCC exceeds VCC(on).
• OTP
• VCC OVP
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
www.onsemi.com
30
NCL30082
Reset
Timer has
finished
counting
VCC > VCC(on)
OVP2 or
VCC_OVP
VCC < VCC(off)
or
BO_NOK ↓
BO_NOK high
or OTP
or TSD
or CS_Short
Stop
4−s
Timer
VCC
Disch.
BO_NOK high
or OTP
or TSD
or CS_Short
OVP2
or WOD_SCP
or Aux_SCP
or VCC_OVP
Run
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching, tOTP(start) has elapsed
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Note: For the NCL30082B1, the CS pin short circuit Protection is disabled
Figure 70. State Diagram for B, B1, B2, B3 and D Version Faults
www.onsemi.com
31
NCL30082
Reset
Timer has
finished
counting
VCC > VCC(on)
VCC < VCC(off)
or
BO_NOK ↓
VCC < VCC(reset)
4−s
Timer
OVP2 or
VCC_OVP
OVP2 or
VCC_OVP
BO_NOK high
or TSD
or CS_Short
Stop
VCC
Disch.
OTP
BO_NOK high
or TSD
or CS_Short
Latch
Run
OTP or
WOD_SCP or
Aux_SCP
With states: Reset
Stop
Run
VCC Disch.
4−s Timer
Latch
→
→
→
→
→
→
VCC < VCC(off)
Controller is reset, ICC = ICC(start)
Controller is ON, DRV is not switching, tOTP(start) has elapsed
Normal switching
No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)
the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),
only VCC(reset) can release the latch.
Figure 71. State Diagram for A Version Faults
www.onsemi.com
32
NCL30082
OPTIONS
Controller
Output SCP
Winding/
Output
Diode SCP
Over
Temperature
Protection
CS Pin
Short
Protection
VREF
ZCD
Blanking
Brown-Out
blanking
Thermal
Foldback
NCL30082A
Latched
Latched
Latched
Yes
250 mV
3 ms
50 ms
Smooth output
current
decrease
NCL30082B
Auto-recovery
Auto-recovery
Auto-recovery
Yes
250 mV
3 ms
50 ms
Smooth output
current
decrease
NCL30082B1
Auto-recovery
Auto-recovery
Auto-recovery
No
250 mV
3 ms
50 ms
Smooth output
current
decrease
NCL30082B2
Auto-recovery
Auto-recovery
Auto-recovery
Yes
250 mV
1.5 ms
50 ms
Smooth output
current
decrease
NCL30082B3
Auto-recovery
Auto-recovery
Auto-recovery
Yes
333 mV
1.5 ms
50 ms
Smooth output
current
decrease
NCL30082B4
Auto-recovery
Auto-recovery
Auto-recovery
No
250 mV
1.5 ms
50 ms
Smooth output
current
decrease
NCL30082B5
Auto-recovery
Auto-recovery
Auto-recovery
No
333 mV
1.5 ms
50 ms
Smooth output
current
decrease
NCL30082D
Auto-recovery
Auto-recovery
Auto-recovery
Yes
500 mV
3 ms
15 ms
Steep output
current
decrease
ORDERING INFORMATION
Device
Package Marking
Package Type
Shipping†
NCL30082ADMR2G
AAC
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
NCL30082BDMR2G
AAD
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
NCL30082B1DMR2G
AAH
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
NCL30082BDR2G
L30082B
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082B1DR2G
L30082B1
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082B2DR2G
L30082B2
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082B3DR2G
L30082B3
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082B4DR2G
L30082B4
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082B5DR2G
L30082B5
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCL30082DDR2G
L30082D
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
33
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
