NCP1015
Self-Supplied Monolithic
Switcher for Low StandbyPower Offline SMPS
The NCP1015 integrates a fixed−frequency current−mode
controller and a 700 V voltage MOSFET. Housed in a PDIP−7 or
SOT−223 package, the NCP1015 offers everything needed to build a
rugged and low−cost power supply, including soft−start, frequency
jittering, short−circuit protection, skip−cycle, a maximum peak
current set−point and a Dynamic Self−Supply (no need for an auxiliary
winding).
Unlike other monolithic solutions, the NCP1015 is quiet by nature:
during nominal load operation, the part switches at one of the available
frequencies (65−100 kHz). When the current set−point falls below a
given value, e.g. the output power demand diminishes, the IC
automatically enters the so−called skip cycle mode and provides
excellent efficiency at light loads. Because this occurs at typically 0.25
of the maximum peak value, no acoustic noise takes place. As a result,
standby power is reduced to the minimum without acoustic noise
generation.
Short−circuit detection takes place when the feedback signal fades
away e.g. un−true short−circuit or is broken optocoupler cases. Finally
soft−start and frequency jittering further ease the designer task to
quickly develop low−cost and robust offline power supplies.
For improved standby performance, the connection of an auxiliary
winding stops the DSS operation and helps to consume less than
100 mW at high line.
MARKING
DIAGRAMS
PDIP−7
CASE 626A
AP SUFFIX
8
1
P1015APyy
AWL
YYWWG
1
4
SOT−223
CASE 318E
ST SUFFIX
4
1
yy
y
A
WL
YY
WW
G or G
AYW
1015y G
G
1
= 06 (65 kHz), 10 (100 kHz)
= A (65 kHz), B (100 kHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
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Built−in 700 V MOSFET with typical RDS(on) of 11 W
Large Creepage Distance between High−voltage Pins
Current−mode Fixed Frequency Operation: 65 kHz − 100 kHz
Skip−cycle Operation at Low Peak Currents Only: No Acoustic Noise!
Dynamic Self−Supply, No Need for an Auxiliary Winding
Internal 1 ms Soft−start
Auto−recovery Internal Output Short−circuit Protection
Frequency Jittering for Better EMI Signature
Below 100 mW Standby Power if Auxiliary Winding is Used
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient and AC Analysis
This is a Pb−Free Device
Typical Applications
• Low Power ac−dc Adapters for Chargers
• Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
PIN CONNECTIONS
PDIP−7
VCC 1
8 GND
NC 2
7 GND
GND 3
FB 4
5 DRAIN
(Top View)
SOT−223
VCC
1
FB
2
DRAIN
3
4
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 3
1
Publication Order Number:
NCP1015/D
NCP1015
Indicative Maximum Output Power from NCP1015
RDS(on) − Ip
230 Vac
100 − 250 Vac
11 W − 450 mA DSS
14 W
6.0 W
11 W − 450 mA Auxiliary Winding
19 W
8.0 W
1. Informative values only, with: Tamb = 50°C, circuit mounted on minimum copper area as recommended.
Vout
+
+
100−250 Vac
1
8
2
7
3
4
+
5
GND
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin No.
SOT−223
PDIP−7
Pin Name
Function
Description
1
1
VCC
Powers the Internal Circuitry
This pin is connected to an external capacitor of typically
10 mF. The natural ripple superimposed on the VCC
participates to the frequency jittering. For improved
standby performance, an auxiliary VCC can be connected
to Pin 1. The VCC also includes an active shunt which
serves as an opto fail−safe protection.
−
2
NC
−
−
−
3
GND
The IC Ground
−
2
4
FB
Feedback Signal Input
By connecting an optocoupler to this pin, the peak current
setpoint is adjusted accordingly to the output power
demand.
3
5
DRAIN
Drain Connection
−
−
−
−
−
−
7
GND
The IC Ground
−
4
8
GND
The IC Ground
−
The internal drain MOSFET connection.
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2
NCP1015
VCC
Startup Source
VCC 1
8 GND
Drain
Rsense
UVLO
Management
High when VCC t 3 V
250 ns
L.E.B.
Reset
NC 2
EMI Jittering
4V
65 kHz
100 kHz
Clock
Set
Flip−Flop
Dmax = 65%
Q
7
GND
Driver
Reset
VCC
18 k
Error flag armed?
GND 3
−
+
−
+
0.5 V
Overload?
Soft−Start
Startup Sequence
Overload
FB 4
+
-
Drain
5
DRAIN
Figure 2. Simplified Internal Circuit Architecture
MAXIMUM RATINGS
Symbol
Rating
Value
Unit
VCC
Power Supply voltage on all pins, except pin 5 (drain)
−0.3 to 10
V
Vds
Drain voltage
−0.3 to 700
V
Idspk
Drain peak current during transformer saturation
1
A
I_VCC
Maximum current into pin 1
15
RqJL
RqJA
RqJL
RqJA
TJMAX
Thermal Characteristics
P Suffix, Case 626A
Junction−to−Lead
Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad
0.36 Sq. Inch (2.32 Sq. Cm)
1.0 Sq. Inch (6.45 Sq. Cm)
ST Suffix, Plastic Package Case 318E
Junction−to−Lead
Junction−to−Air, 2.0 oz (70 mm) Printed Circuit Copper Clad
0.36 Sq. Inch (2.32 Sq. Cm)
1.0 Sq. Inch (6.45 Sq. Cm)
Maximum Junction Temperature
9.0
77
60
14
74
55
150
Storage Temperature Range
ESD Capability, Human Body Model (HBM) (All pins except HV)
ESD Capability, Machine Model (MM)
mA
°C/W
°C
−60 to +150
°C
2
kV
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NCP1015
ELECTRICAL CHARACTERISTICS (For typical values TJ=25°C, for min/max values TJ=−40°Cto125°C, VCC=8V unless otherwise noted)
Rating
Symbol
Pin
Min
Typ
Max
Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC(off)
VCC increasing level at which the current source turns−off
1
7.9
8.5
9.1
V
VCC(on)
VCC decreasing level at which the current source turns−on
1
6.9
7.5
8.1
V
V
VCCLATCH
Decreasing level at which the Latch−off phase Ends
1
4.4
4.7
5.1
DVCC
Hysteresis between VCC(off)
1
−
1.0
−
ICC1
Internal IC consumption, MOSFET switching at 65 kHz
1
−
0.92
1.1
mA
ICC1
Internal IC consumption, MOSFET switching at 100 kHz
1
−
0.95
1.15
mA
Vclamp
Active zener voltage positive offset to VCC(off)
1
140
200
300
mV
5
5
−
−
11
−
19
24
5
700
−
−
Power Switch & Startup breakdown voltage off−state leakage current
TJ = −40°C (Vds = 650 V)
TJ = 25°C (Vds = 700 V)
TJ = 125°C (Vds = 700 V)
5
5
5
−
−
−
70
50
30
120
−
−
Switching characteristics (RL = 50 W, Vds set for Ids = 0.7 x Idslim)
Turn−on time (90% − 10%)
Turn−off time (10% − 90%)
5
5
−
−
20
10
−
−
1
5.0
5.0
8.0
8.0
10
11
mA
1
−
10
−
mA
POWER SWITCH CIRCUIT
RDS(on)
Vdsb
IDS(off)
ton
toff
Power Switch Circuit on−state resistance (Id = 50 mA)
TJ = 25°C
TJ = 125°C
Power Switch Circuit & Startup breakdown voltage
(IDS(off) = 100 mA, TJ = 25°C)
W
V
mA
ns
INTERNAL START−UP CURRENT SOURCE
IC1
High−voltage current source, VCC = 8 V
IC2
High−voltage current source, VCC = 0
0°C < TJ < 125°C
−40°C < TJ < 125°C
CURRENT COMPARATOR TJ = 255C (Note 2)
Ipeak
Maximum internal current set−point
5
405
450
495
mA
ILskip
Default internal current set−point for skip cycle operation,
percentage Ipeakmax
−
−
25
−
%
tDEL
Propagation delay from current detection to drain OFF state
−
−
125
−
ns
tLEB
Leading Edge Blanking Duration
−
−
250
−
ns
INTERNAL OSCILLATOR
fOSC
Oscillation frequency, 65 kHz version, TJ = 25°C (Note 2)
59
65
71
kHz
fOSC
Oscillation frequency, 100 kHz version, TJ = 25°C (Note 2)
90
100
110
kHz
fdither
Frequency dithering compared to switching frequency (with active DSS)
−
±3.3
−
%
Dmax
Maximum Duty−cycle
62
67
72
%
FEEDBACK SECTION
Rup
Internal pull−up resistor
4
−
18
−
kW
tss
Internal soft−start (guaranteed by design)
−
−
1.0
−
ms
SKIP CYCLE GENERATION
Vskip
Default skip mode level on FB pin
4
0.5
V
Temperature shutdown
150
°C
Hysteresis in shutdown
50
°C
TEMPERATURE MANAGEMENT
TSD
2. See characterization curves for temperature evolution
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4
NCP1015
−2
1.5
−3
1.4
−4
1.3
−5
1.2
−6
1.1
ICC1 (mA)
IC1 ( mA)
TYPICAL CHARACTERISTICS
−7
−8
1.0
0.9
−9
0.8
−10
0.7
−11
0.6
−12
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
0.5
−40
120
Figure 3. IC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
9.0
0.38
8.9
0.36
20
40
60
80
TEMPERATURE (°C)
100
120
8.8
VCC−OFF ( V )
0.34
ICC2 (mA)
0
Figure 4. ICC1 @ VCC = 8.0 V, FB = 1.5 V
vs. Temperature
0.40
0.32
0.30
0.28
0.26
8.7
8.6
8.5
8.4
0.24
0.22
0.20
−40
−20
8.3
−20
0
20
40
60
80
TEMPERATURE (°C)
100
8.2
−40
120
Figure 5. ICC2 @ VCC = 6.0 V, FB = Open
vs. Temperature
−20
0
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 6. VCC OFF, FB = 1.5 V vs. Temperature
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NCP1015
TYPICAL CHARACTERISTICS
69
8.0
7.9
7.7
DUTY CYCLE (%)
VCC−ON ( V)
7.8
7.6
7.5
7.4
7.3
68
67
7.2
7.1
7.0
66
−40
−20
0
20
40
80
60
100
−40 −20
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCC ON, FB = 3.5 V vs. Temperature
Figure 8. Duty Cycle vs. Temperature
600
Ipeak (mA)
550
500
450
400
350
−40
−20
0
20
40
80
60
100
120
TEMPERATURE (°C)
Figure 9. Ipeak−RR, VCC = 8.0 V, FB = 3.5 V
vs. Temperature
25
110
100 kHz
20
90
RDSon (W)
fOSC (kHz)
100
80
70
15
10
65 kHz
5
60
50
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
0
−40
120
Figure 10. Frequency vs. Temperature
−20
0
60
20
40
80
TEMPERATURE (°C)
100
Figure 11. ON Resistance vs. Temperature
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120
NCP1015
APPLICATION INFORMATION
Introduction
averaged version to help you closing the loop.
Ready−to−use templates can be downloaded in
OrCAD’s PSpice, and INTUSOFT’s IsSpice4 from ON
Semiconductor web site, NCP1015 related section.
The NCP1015 offers a complete current−mode control
solution (actually an enhanced NCP1200 controller section)
together with a high−voltage power MOSFET in a
monolithic structure. The component integrates everything
needed to build a rugged and low−cost Switch−Mode Power
Supply (SMPS) featuring low standby power. The quick
selection table details the differences in operating
frequency.
• No need for an auxiliary winding: ON Semiconductor
Very High Voltage Integrated Circuit technology lets
you supply the IC directly from the high−voltage dc
rail. We call it Dynamic Self−Supply (DSS). This
solution simplifies the transformer design and ensures a
better control of the SMPS in difficult output
conditions, e.g. constant current operations. However,
for improved standby performance, an auxiliary
winding can be connected to the VCC pin to disable the
DSS operation.
• Short−circuit protection: by permanently monitoring
the feedback line activity, the IC is able to detect the
presence short−circuit, immediately reducing the output
power for a total system protection. Once the short has
disappeared, the controller resumes and goes back to
normal operation.
• Low standby−power: If SMPS naturally exhibit a good
efficiency at nominal load, they begin to be less
efficient when the output power demand diminishes. By
skipping un−needed switching cycles, the NCP1015
drastically reduces the power wasted during light load
conditions. An auxiliary winding can further help
decreasing the standby power to extremely low levels
by invalidating the DSS operation. Typical
measurements show results below 80 mW @ 230 Vac
for a typical 7 W universal power supply.
• No acoustic noise while operating: Instead of skipping
cycles at high peak currents, the NCP1015 waits until
the peak current demand falls below a fixed 0.25 of the
maximum limit. As a result, cycle skipping can take
place without having a singing transformer. You can
thus select cheap magnetic components free of noise
problems.
• SPICE model: a dedicated model to run transient
cycle−by−cycle simulations is available but also an
Dynamic Self−Supply
When the power supply is first powered from the mains
outlet, the internal current source (typically 8 mA) is biased
and charges up the VCC capacitor from the drain pin. Once
the voltage on this VCC capacitor reaches the VCC(off) level
(typically 8.5 V), the current source turns off and pulses are
delivered by the output stage: the circuit is awake and
activates the power MOSFET. Figure 12 details the internal
circuitry:
Vref OFF = 8.5 V
Vref ON = 7.5 V
VrefLatch = 4.7 V
+
Startup Source
Internal Supply
+
Vref
Drain
VCC(off)
+200 mV
(8.7 V Typ.)
VCC
+
CVCC
Figure 12. The Current Source Regulates VCC
by Introducing a Ripple
Being loaded by the circuit consumption, the voltage on
the VCC capacitor goes down. When the DSS controller
detects that VCC has reached 7.5 V (VCC(on)), it activates the
internal current source to bring VCC toward 8.5 V and stops
again: a cycle takes place whose low frequency depends on
the VCC capacitor and the IC consumption. A 1 V ripple
takes place on the VCC pin whose average value equals
(VCC(off) + VCC(on)) / 2. Figure 13 shows a typical operation
of the DSS.
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NCP1015
8.5V
8.00
7.5V
Vcc
6.00
4.00
Device
internally
pulses
2.00
0
Startup period
Figure 13. The Charge/Discharge Cycle over a 10 mF VCC Capacitor
the so−called latch−off level, where the current source
activates again to attempt a new re−start. If the error has
gone, the IC automatically resumes its operation. If the
default is still there, the IC pulses during 8.5 V down to 7.5 V
and enters a new latch−off phase. The resulting burst
operation guarantees a low average power dissipation and
lets the SMPS sustain a permanent short−circuit. Figure 14
presents the corresponding diagram:
As one can see, the VCC capacitor shall be dimensioned to
offer an adequate startup time, i.e. ensure regulation is
reached before VCC crosses 7.5 V (otherwise the part enters
the fault condition mode). If we know that DV = 1 V and
ICC1 is 1.2 mA (for instance we selected a 11 W device
switching at 65 kHz), then the VCC capacitor can be
calculated using:
Cw
ICC1 @ t startup
DV
(eq. 1)
Let’s suppose that the SMPS needs 10 ms to startup, then
we will calculate C to offer a 15 ms period. As a result, C
should be greater than 18 mF thus the selection of a 33 mF /
16 V capacitor is appropriate.
Current Sense
Information
4V
FB
Short Circuit Protection
The internal protection circuitry involves a patented
arrangement that permanently monitors the assertion of an
internal error flag. This error flag is, in fact, a signal that
instructs the controller that the internal maximum peak
current limit is reached. This naturally occurs during the
startup period (Vout is not stabilized to the target value) or
when the optocoupler LED is no longer biased, e.g in a
short−circuit condition or when the feedback network is
broken. When the DSS normally operates, the logic checks
for the presence of the error flag every time VCC crosses
VCC(on). If the error flag is low (peak limit not active) then
the IC works normally. If the error signal is active, then the
NCP1015 immediately stops the output pulses, reduces its
internal current consumption and does not allow the startup
source to activate: VCC drops toward ground until it reaches
+
−
Division
Max
Ip
Clamp
Active?
VCC
To
Latch
Reset
VCC(on)
Flag
Figure 14. Simplified NCP1015 Short−Circuit
Detection Circuitry
The protection burst duty−cycle can easily be computed
through the various timing events as portrayed by Figure 15:
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NCP1015
Tsw
1 V Ripple
Tstart
TLatch
Latch−off
Level
Figure 15. NCP1015 Facing a Fault Condition (Vin = 150 Vdc)
The rising slope from the latch−off level up to 8.5 V is
expressed by:
Figure 16 shows a typical drain−ground wave−shape
where leakage effects have been removed:
P DSS + V in @ ICC1
Vds(t)
t start + DV1 @ C
IC1
toff
The time during which the IC actually pulses is given by:
t sw + DV2 @ C
ICC1
Vin
Vr
dt
Finally, the latch−off time can be derived using the same
formula topology:
t latch + DV3 @ C
ICC2
ton
From these three definitions, the burst duty−cycle D can
be computed:
Tsw
t sw
t start ) t sw ) t latch
(eq. 2)
Figure 16. A Typical Drain−ground Waveshape
where Leakage Effects are Not Accounted for
DV2
DV3 Ǔ
DV2
) DV1
) ICC2
ICC1 @ ǒICC1
IC1
(eq. 3)
By looking at Figure 16 the average result can easily be
derived by additive square area calculation:
D+
D+
t
Feeding the equation with values extracted from the
parameter section gives a typical duty−cycle D of 13%,
precluding any lethal thermal runaway while in a fault
condition.
t V DS(t) u+ V in @ (1 * D) ) V r @
(eq. 5)
By developing Equation 5 we obtain:
t V DS(t) u+ V in * V in @
DSS Internal Dissipation
The Dynamic Self−Supplied pulls the energy out from the
drain pin. In the Flyback−based converters, this drain level
can easily go above 600 V peak and thus increase the stress
on the DSS startup source. However, the drain voltage
evolves with time and its period is small compared to that of
the DSS. As a result, the averaged dissipation, excluding
capacitive losses, can be derived by:
P DSS + ICC1 @t V DS(t) u
t off
t sw
t
t on
) V r @ off
t sw
t sw
(eq. 6)
toff can be expressed by:
t off + I p @
Lp
Vr
(eq. 7)
Lp
V in
(eq. 8)
ton can be evaluated by:
t on + I p @
(eq. 4)
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NCP1015
Plugging Equation 7 and Equation 8 into Equation 6 leads
to = Vin and thus:
P DSS + V in @ ICC1
V nom * V clamp
I trip
(eq. 9)
v R lim v
V stby * V CC(on)
ICC1
(eq. 10)
Where:
Vnom is the auxiliary voltage at nominal load
Vstdby is the auxiliary voltage when standby is entered
Itrip is the current corresponding to the nominal operation.
It thus must be selected to avoid false tripping in overshoot
conditions.
ICC1 is the controller consumption. This number slightly
decreases compared to ICC1 from the spec since the part in
standby does almost not switch.
VCC(on) is the level above which Vaux must be maintained
to keep the DSS in the OFF mode. It is good to shoot around
8 V in order to offer an adequate design margin, e.g. to not
re−activate the startup source (which is not a problem in
itself if low standby power does not matter)
Since Rlimit shall not bother the controller in standby, e.g.
keep Vaux to around 8 V (as selected above), we purposely
select a Vnom well above this value. As explained before,
experience shows that a 40% decrease can be seen on
auxiliary windings from nominal operation down to standby
mode. Let’s select a nominal auxiliary winding of 20 V to
offer sufficient margin regarding 8 V when in standby (Rlimit
also drops voltage in standby). Plugging the values in
Equation 10 gives the limits within which Rlimit shall be
selected:
The worse case occurs at high line, when Vin equals
370 Vdc. With ICC1 = 1.2 mA (65 kHz version), we can
expect a DSS dissipation around 440 mW. If you select a
higher switching frequency version, the ICC1 increases and
it is likely that the DSS consumption exceeds 500 mW. In
that case, we recommend adding an auxiliary winding in
order to offer more dissipation room to the power MOSFET.
Please read application note AND8125/D “Evaluating the
power capability of the NCP101X members” to help
selecting the right part / configuration for your application.
Lowering the Standby Power with an Auxiliary
Winding
The DSS operation can bother the designer when a) its
dissipation is too high b) extremely low standby power is a
must. In both cases, one can connect an auxiliary winding to
disable the self−supply. The current source then ensures the
startup sequence only and stays in the off state as long as
VCC does not drop below VCC(on) or 7.5 V. Figure 17 shows
that the insertion of a resistor (Rlimit) between the auxiliary
dc level and the VCC pin is mandatory a) not to damage the
internal 8.7 V zener diode during an overshoot for instance
(absolute maximum current is 15 mA) b) to implement the
fail−safe optocoupler protection as offered by the active
clamp. Please note that there cannot be bad interaction
between the clamping voltage of the internal zener and
VCC(off) since this clamping voltage is actually built on top
of VCC(off) with a fixed amount of offset (200 mV typical).
Self−supplying controllers in extremely low standby
applications often puzzles the designer. Actually, if a SMPS
operated at nominal load can deliver an auxiliary voltage of
an arbitrary 16 V (Vnom), this voltage can drop to below
10 V (Vstby) when entering standby. This is because the
recurrence of the switching pulses expands so much that the
low frequency re−fueling rate of the VCC capacitor is not
enough to keep a proper auxiliary voltage. Figure 18 shows
a typical scope shot of a SMPS entering deep standby
(output un−loaded). So care must be taken when calculating
Rlimit 1) to not excess the maximum pin current in normal
operation but 2) not to drop too much voltage over Rlimit
when entering standby. Otherwise the DSS could reactivate
and the standby performance would degrade. We are thus
able to bound Rlimit between two equations:
20 * 8.7 v R
12 * 8
limit v 1.1 m
6.3 m
(eq. 11)
that is to say: 1.8 kW < Rlimit < 3.6 kW.
If we are designing a power supply delivering 12 V, then
the ratio auxiliary/power must be: 12 / 20 = 0.6. The ICC
current has to not exceed 6.4 mA. This will occur when Vaux
grows−up to: 8.7 V + 1.8 k x (6.4 m + 1.1 m) = 22.2 V for
the first boundary or 8.7 V + 3.6 k x (6.4 m +1.1 m) = 35.7 V
for second boundary. On the power output, it will
respectively give 22.6 x 0.6 = 13.3 V and 35.7 x 0.6 = 21.4 V.
As one can see, tweaking the Rlimit value will allow the
selection of a given overvoltage output level. Theoretically
predicting the auxiliary drop from nominal to standby is an
almost impossible exercise since many parameters are
involved, including the converter time constants. Fine
tuning of Rlimit thus requires a few iterations and
experiments on a breadboard to check Vaux variations but
also output voltage excursion in fault. Once properly
adjusted, the fail−safe protection will preclude any lethal
voltage runaways in case a problem would occur in the
feedback loop.
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NCP1015
Drain
VCC(off) = 8.5 V
VCC(on) = 7.5 V
+
-
Startup Source
+
VCC
Rlimit
D1
+
+
−
+
CVCC
+
CAux
Laux
Ground
Figure 17. A Detailed View of the NCP1015 with Properly Connected Auxiliary Winding
u30 ms
Figure 18. The Burst Frequency becomes So Low that it is Difficult to
Keep an Adequate Level on the Auxiliary VCC
Lowering the Standby Power with Skip−cycle
excited by the skipping pulses. A possible solution,
successfully implemented in the NCP1200 series, also
authorizes skip cycle but only when the power demand as
dropped below a given level. At this time, the peak current
is reduced and no noise can be heard. Figure 19 shows the
peak current evolution of the NCP1015 entering standby:
Skip cycle offers an efficient way to reduce the standby
power by skipping unwanted cycles at light loads. However,
the recurrent frequency in skip often enters the audible range
and a high peak current obviously generates acoustic noise
in the transformer. The noise takes its origins in the
resonance of the transformer mechanical structure which is
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11
NCP1015
100%
Peak current
at nominal power
Skip−cycle
current limit
25%
Figure 19. Low Peak Current Skip−Cycle Guarantees Noise−Free Operation
the benefit to artificially reduce the measurement noise on
a standard EMI receiver and pass the tests more easily. The
EMI sweep is implemented by routing the VCC ripple
(induced by the DSS activity) to the internal oscillator. As a
result, the switching frequency moves up and down to the
DSS rhythm. Typical deviation is ±4% of the nominal
frequency. With a 1 V peak−to−peak ripple, the frequency
will equal 65 kHz in the middle of the ripple and will
increase as VCC rises or decrease as VCC ramps down.
Figure 20 shows the behavior we have adopted:
Full power operation involves the nominal switching
frequency and thus avoids any noise when running.
Experiments carried on a 5 W universal mains board
unveiled a standby power of 300 mW @ 230 Vac with the
DSS activated and dropped to less than 100 mW when an
auxiliary winding is connected.
Frequency Jittering for Improved EMI Signature
By sweeping the switching frequency around its nominal
value, it spreads the energy content on adjacent frequencies
rather than keeping it centered in one single ray. This offers
VCC Ripple
VCCOFF
67.6 kHz
65 kHz
62.4 kHz
Internal Sawtooth
VCCON
Figure 20. The VCC Ripple Causes the Frequency Jittering on the Internal Oscillator Saw−tooth
(65 kHz version)
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12
NCP1015
Soft−Start
soft−start is also activated during the over current burst
(OCP) sequence. Every re−start attempt is followed by a
soft−start activation. Generally speaking, the soft−start will
be activated when VCC ramps up either from zero (fresh
power−on sequence) or 4.5 V, the latch−off voltage
occurring during OCP. Figure 21 shows the soft−start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
The NCP1015 features an internal 1 ms soft−start
activated during the power on sequence (PON). As soon as
VCC reaches VCC(off), the peak current is gradually
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1 ms and
further to that time period, the peak current limit is blocked
to the maximum until the supply enters regulation. The
8.5 V
VCC
0 V (Fresh PON)
or
4.7 V (Overload)
Current
Sense
Max Ip
1.0 ms
Figure 21. Soft−Start is Activated During a Start−up Sequence or an OCP Condition
Non−latching Shutdown
and ground. By pulling FB below the internal skip level
(Vskip), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 22 shows the
application example:
In some cases, it might be desirable to shut off the part
temporarily and authorize its re−start once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
1
8
2
7
3
4
ON/OFF
+
5
Transformer
CVCC
Figure 22. A Non−latching Shutdown where Pulses are Stopped as long as the NPN is Biased
Full Latching Shutdown
When the OVP level exceeds the zener breakdown voltage,
the NPN biases the PNP and fires the equivalent SCR,
permanently bringing down the FB pin. The switching
pulses are disabled until the user un−plugs the power supply.
Other applications require a full latching shutdown, e.g.
when an abnormal situation is detected (over temp or
overvoltage). This feature can easily be implemented
through two external transistors wired as a discrete SCR.
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13
NCP1015
Rhold
12 k
OVP
10 k
1
8
2
7
3
BAT54
4
+
0.1 mF
5
Transformer
CVCC
10 k
Figure 23. Two Bipolar Transistors Ensures a Total Latch−off of the SMPS in Presence of an OVP
Rhold ensures that the SCR stays on when fired. The bias
current flowing through Rhold should be small enough to let
the VCC ramp up (8.5 V) and down (7.5 V) when the SCR
is fired. The NPN base can also receive a signal from a
temperature sensor. Typical bipolar can be MMBT2222 and
MMBT2907 for the discrete latch. The NST3946 features
two bipolar NPN + PNP in the same package and could also
be used.
P max +
T J(max) * T AMB(max)
R qJA
(eq. 12)
which gives around 1 W for an ambient of 50°C. The losses
inherent to the MOSFET RDS(on) can be evaluated using the
following formula:
P mos + 1 @ I p 2 @ D @ R DS(on)
3
(eq. 13)
where Ip is the worse case peak current (at the lowest line
input), D is the converter operating duty−cycle and RDS(on)
the MOSFET resistance for TJ = 100°C. This formula is only
valid for Discontinuous Conduction Mode (DCM)
operation where the turn−on losses are null (the primary
current is zero when you re−start the MOSFET). Figure 24
gives a possible layout to help dropping the thermal
resistance. When measured on a 35 mm (1 oz.) copper
thickness PCB, we obtained a thermal resistance of 75°C/W:
Power Dissipation and Heatsinking
The power dissipation of NCP1015 consists of the
dissipation DSS current−source (when active) and the
dissipation of MOSFET. Thus Ptot = PDSS + PMOSFET.
When the PDIP7 package is surrounded by copper, it
becomes possible to drop its thermal resistance
junction−to−ambient, RqJA down to 75°C/W and thus
dissipate more power. The maximum power the device can
thus evacuate is:
Clamping Elements
To Secondary Diode
DC
Figure 24. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient
Design Procedure
1. In any case, the lateral MOSFET body−diode shall
never be forward biased, either during start−up
(because of a large leakage inductance) or in
normal operation as shown by Figure 25.
The design of a SMPS around a monolithic device does
not differ from that of a standard circuit using a controller
and a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices:
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14
NCP1015
350
250
150
50.0
> 0 !!
−50.0
1.004M
1.011M
1.018M
1.025M
1.032M
Figure 25. The Drain−Source Wave Shall Always be Positive . . .
As a result, the Flyback voltage which is reflected on
the drain at the switch opening cannot be larger than
the input voltage. When selecting components, you
thus must adopt a turn ratio which adheres to the
following equation:
N @ (V out ) V f) t V IN(min)
e.g. the Vout target is almost reached and Ip is still
pushed to the maximum.
Taking into account all previous remarks, it becomes
possible to calculate the maximum power that can be
transferred at low line:
When the switch closes, Vin is applied across the primary
inductance Lp until the current reaches the level imposed by
the feedback loop. The duration of this event is called the ON
time and can be defined by:
(eq. 14)
For instance, if you operate from a 120 V dc rail and
you deliver 12 V, we can select a reflected voltage of
100 VDC maximum: 120 − 100 > 0. Therefore, the
turn ratio Np : Ns must be smaller than 100 / (12 +
1) = 7.7 or Np : Ns < 7.7. We will see later on how
it affects the calculation.
2. Current−mode architecture is, by definition,
sensitive to subharmonic oscillations.
Subharmonic oscillations only occur when the
SMPS is operating in Continuous Conduction
Mode (CCM) together with a duty−cycle greater
than 50%. As a result, we recommend operating
the device in DCM only, whatever duty−cycle it
implies (max. = 65%).
3. Lateral Mosfets have a poorly doped body−diode
which naturally limits their ability to sustain the
avalanche. A traditional RCD clamping network
shall thus be installed to protect the MOSFET. In
some low power applications, a simple capacitor
can also be used since:
V DRAIN(max) + V in ) N @ (V out ) V f) ) I p @
t on +
Lp @ Ip
V in
(eq. 16)
At the switch opening, the primary energy is transferred
to the secondary and the flyback voltage appears across Lp,
reseting the transformer core with a slope of:
N @ (V out ) V f)
@ t off
Lp
the toff time is thus:
t off +
Lp @ Ip
N @ (V out ) V f)
(eq. 17)
If one wants to keep DCM only, but still need to pass the
maximum power, we will not allow a dead−time after the
core is reset, but rather immediately re−start. The switching
time tsw can be expressed by:
t sw + t off ) t on + L p @ I p @
Ǹ
Lf
(eq. 15)
C tot
ǒ
Ǔ
1 )
1
(eq. 18)
V in N @ (V out ) V f)
The Flyback transfer formula dictates that:
P out
1
2
h + 2 @ L p @ I p @ f sw
where Lf is the leakage inductance, Ctot the total
capacitance at the drain node (which is increased by
the capacitor you will wire between drain and
source), N the Np : Ns turn ratio, Vout the output
voltage, Vf the secondary diode forward drop and
finally, Ip the maximum peak current. Worse case
occurs when the SMPS is very close to regulation,
(eq. 19)
which, by extracting Ip and plugging into Equation 19 leads to:
t sw + L p
Ǹ
ǒ
2 @ P out
1
@ 1 )
V in N @ (V out ) V f)
h @ f sw @ L p
Extracting Lp from Equation 20 gives:
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15
Ǔ
(eq. 20)
NCP1015
L Pcritical +
(V in @ V r) 2 @ h
2 @ f sw @ [P out @ (V r 2 ) 2 @ V r @ V in ) V in 2)]
with Vr = N . (Vout + Vf) and h the efficiency.
If Lp critical gives the inductance value above which
DCM operation is lost, there is another expression we can
write to connect Lp, the primary peak current bounded by the
NCP1015 and the maximum duty−cycle that needs to stay
below 50%:
L P(max) +
D max @ V IN(min) @ t sw
I P(max)
P max + t sw 2 @ V IN(min) 2 @ V r 2 @ h @
(eq. 21)
where VIN(min) corresponds to the lowest bulk voltage,
hence the longest ton duration or largest duty−cycle. IP(max)
is the available peak current from the considered part, e.g.
450 mA typical for the NCP1015 (however, the minimum
value of this parameter shall be considered for reliable
evaluation). Combining Equations 21 and 22 gives the
maximum theoretical power you can pass respecting the
peak current capability of the NCP1015, the maximum
duty−cycle and the discontinuous mode operation:
(eq. 22)
f sw
(eq. 23)
(2L P(max)V r 2 ) 4L P(max)V rV IN(min) ) V IN(min) 2)
From Equation 22 we obtain the operating duty−cycle D:
D+
Ip @ Lp
V in @ t sw
(eq. 24)
This lets us calculate the RMS current circulating in the
MOSFET:
I D(rms) + I p @
ǸD3
Applying the above equations leads to :
Selected maximum reflected voltage = 120 V
with Vout = 12 V, secondary drop = 0.5 V ³ Np : Ns = 1 : 0.1
Lp critical = 3.9 mH
Ip = 250 mA
Dmax = 0.39
IDRAIN(rms) = 90 mA
(eq. 25)
From this equation, we obtain the average dissipation in
the MOSFET:
P avg + 1 @ I p 2 @ D @ R DS(on)
3
(eq. 26)
PMOSFET = 202 mW at RDS(on) = 25 W (TJ > 100°C)
PDSS = 1.2 mA x 350 V = 420 mW, if DSS is used
Secondary diode voltage stress = (350 x 0.1) + 12 = 47 V
(e.g. a MBRS360T3, 3 A / 60 V would fit)
to which switching losses shall be added.
If we stick to Equation 23, compute Lp and follow the
above calculations, we will discover that a power supply
built with the NCP1015 and operating from a 100 Vac line
minimum will not be able to deliver more than 7 W
continuous, regardless of the selected switching frequency
(however the transformer core size will go down as fsw is
increased). This number grows up significantly when
operated from single European mains (18 W).
For more different flyback converters then are the below
examples we recommend use following support:
1) Application note AND8125/D “Evaluating the power
capability of the NCP101X members”
2) Application note AND8134/D “Designing Converters
with the NCP101X members.”
3) Application note AND8142/D “A 6W/12W Universal
mains adapter with NCP101X series”.
4) The PSpice or Orcad simulation models
Example 2.: A 12 V 16 W SMPS Operating on Narrow
European Mains with NCP1015:
Vin = 230 Vac ± 15%, or 276 Vdc ÷ 370 Vdc
Efficiency = 80%
Vout = 12 V, Iout = 1.25 A
fsw = 65 kHz
IP(max) = 450 mA − 10% = 405 mA
Applying the equations leads to :
Selected maximum reflected voltage = 250 V
with Vout = 12 V, secondary drop = 0.5 V ³ Np : Ns = 1:0.05
Lp = 7,2 mH
Ip = 0.27 mA
Dmax = 0.41
IDRAIN(rms) = 100 mA
Example 1.: A 12 V 7.0 W SMPS Operating on a Large
Mains with NCP1015:
Vin = 100 Vac ÷ 250 Vac or 140 Vdc ÷ 350 Vdc once
rectified, assuming a low bulk ripple
Efficiency = 80%
Vout = 12 V, Iout = 580 mA
fsw = 65 kHz
IP(max) = 450 mA − 10% = 405 mA
PMOSFET = 250 mW at RDS(on) = 25 W (TJ > 100°C)
PDSS = 1.2 mA x 370 V = 444 mW, if DSS is used below an
ambient of 50°C.
Secondary diode voltage stress = (370 x 0.05) + 12 = 30.5 V
(e.g. a MBRS340T3, 3 A / 40 V)
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16
NCP1015
MOSFET Protection
Please note that these calculations assume a flat DC rail
whereas a 10 ms ripple naturally affects the final voltage
available on the transformer end. Once the Bulk capacitor
has been selected, one should check that the resulting ripple
(min Vbulk?) is still compatible with the above calculations.
As an example, to benefit from the largest operating range,
a 7 W board was built with a 47 mF bulk capacitor which
ensured discontinuous operation even in the ripple
minimum waves.
HV
As in any Flyback design, it is important to limit the drain
excursion to a safe value, e.g. below the MOSFET BVdss
which is 700 V. Figures 26A, B, and C present possible
implementations:
HV
HV
Rclamp
Cclamp
Dz
D
D
CVcc
1
8
1
8
1
2
7
2
7
2
7
3
6
3
6
3
6
4
5
4
5
4
5
NCP1015
CVcc
NCP1015
C
CVc
c
NCP1015
C
B
A
8
Figure 26. Different Options to Clamp the Leakage Spike
current. Worse case occurs when Ip and Vin are maximum
and Vout is close to reach the steady−state value.
Figure 26C: This option is probably the most expensive of
all three but it offers the best protection degree. If you need
a very precise clamping level, you must implement a zener
diode or a TVS. There are little technology differences
behind a standard zener diode and a TVS. However, the die
area is far bigger for a transient suppressor than that of zener.
A 5 W zener diode like the 1N5388B will accept 180 W peak
power if it lasts less than 8.3 ms. If the peak current in the
worse case (e.g. when the PWM circuit maximum current
limit works) multiplied by the nominal zener voltage
exceeds these 180 W, then the diode will be destroyed when
the supply experiences overloads. A transient suppressor
like the P6KE200 still dissipates 5 W of continuous power
but is able to accept surges up to 600 W @ 1 ms. Select the
zener or TVS clamping level between 40 to 80 volts above
the reflected output voltage when the supply is heavily
loaded.
Figure 26A: The simple capacitor limits the voltage
according to Equation 15. This option is only valid for low
power applications, e.g. below 5 W, otherwise chances exist
to destroy the MOSFET. After evaluating the leakage
inductance, you can compute C with Equation 15. Typical
values are between 100 pF and up to 470 pF. Large
capacitors increase capacitive losses.
Figure 26B: The most standard circuitry called the RCD
network. You calculate Rclamp and Cclamp using the
following formulas:
R clamp +
2 @ V clamp @ (V clamp * (V out ) V f sec) @ N)
L leak @ I p 2 @ f sw
C clamp +
V clamp
V ripple @ f sw @ R clamp
(eq. 27)
(eq. 28)
Vclamp is usually selected 50−80 V above the reflected
value N x (Vout + Vf). The diode needs to be a fast one and
a MUR160 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
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17
NCP1015
Typical Application Examples
input range. The board uses the Dynamic Self−Supply and
a simplified zener−type feedback. This configuration was
selected for cost reasons and a more precise circuitry can be
used, e.g. based on a TL431:
A 6.5 W NCP1015−based Flyback converter. (For
evaluation a universal NCP1012 demo−board can be used)
Figure 27 shows a converter originally built with a
NCP1012 which can be easily used for evaluation of
NCP1015 device delivering 6.5 W from a universal volts
D1
1N4007
1 TR1 8
7
D2
1N4007
E1
10 m/400 V
R1
47 R
1
D3
1N4007
D4
1N4007
D5
U160
4
6
5
IC1
NCP1012
1
2
J1
CEE7.5/2
C1
2n2/Y
R2
150 k
VCC DRAIN
2
GND
3
GND
7
GND
E2
10 m/63 V
FB
GND
5
4
IC2
PC817
D6
B150
E3
470 m/25 V
ZD1
11 V
R3
100 R
8
2
1
J2
CZM5/2
R4
180 R
C2
2n2/Y
Figure 27. A NCP1012−based Flyback Converter Delivering 6.5 W
• Efficiency at Vin = 100 Vac and Pout = 6.5 W = 75.7%
• Efficiency at Vin = 230 Vac and Pout = 6.5 W = 76.5%
The converter built according to Figure 28 layouts, gave
the following results:
Figure 28. The NCP1012−based PCB Layout and its Associated Component Placement
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18
NCP1015
A 7.0 W NCP1015−based Flyback Converter Featuring Low Standby Power
thus offering more room for the MOSFET. In this
application, the feedback is made via a TLV431 whose low
bias current (100 mA min) helps to lower the no−load
standby power.
Figure 29 shows another typical application showing a
NCP1015−65 kHz operating in a 7 W converter up to 70°C
of ambient temperature. We can grow−up the output power
since an auxiliary winding is used, the DSS is disabled, and
Vbulk
1N4148
D4
R4 22
C8
10 nF
400 V
T1
Aux
+ C10
33 mF/25 V
R7
100 k/
1W
+
T1
+
C6 C8
470 mF/16 V
12 V @
0.5 A
+ 100 mF/16 V
C7
GND
D3
MUR160
R2
3.3 k
C2
47 mF/
450 V
L2
22 mH
D2
MBRS360T3
R3
1k
NCP1015
+
R5
39 k
1 VCC GND 8
2 NC
NC 7
3 NC
4 FB DRAIN 5
+ 100 mF/10 V
C3
C4
C9
1 nF
IC1
SFH6156−2
100 nF
IC2
TLV431
C5
R6
4.3 k
2.2 nF
Y1 Type
Figure 29. A Typical Converter Delivering 5 W from a Universal Mains
Measurements have been taken from a demonstration
board implementing Figure 12 12’s sketch and the following
results were achieved, with either the auxiliary winding in
place or through the Dynamic Self−Supply:
Vin = 230 Vac, auxiliary winding, Pout = 0, Pin = 60 mW
Vin = 100 Vac, auxiliary winding, Pout = 0, Pin = 42 mW
Vin = 230 Vac, Dynamic Self−Supply, Pout = 0, Pin =
300 mW
Vin = 100 Vac, Dynamic Self−Supply, Pout = 0, Pin =
130 mW
For a quick evaluation of Figure 29 application example,
the following transformers are available from Coilcraft:
A9619−C, Lp = 3 mH, Np : Ns = 1: 0.1, 7 W application on
universal mains, including auxiliary winding, NCP1015−
65 kHz
A0032−A, Lp = 6 mH, Np : Ns = 1: 0.055, 10 W application
on European mains, DSS operation only, NCP1015−65 kHz
Coilcraft
1102 Silver Lake Road
CARY, IL 60013
Email: info@coilcraft.com
Tel. : 847−639−6400
Fax.: 847−639−1469
Pout = 7 W, h = 81% @ 230 Vac, with aux winding
Pout = 7 W, h = 81.3% @ 100 Vac, with aux winding
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19
NCP1015
ORDERING INFORMATION
Device Order Number
Frequency
(kHz)
Package Type
NCP1015AP065G
65
PDIP−7
(Pb−Free)
NCP1015AP100G
100
PDIP−7
(Pb−Free)
NCP1015ST65T3G
65
SOT−223
(Pb−Free)
NCP1015ST100T3G
100
SOT−223
(Pb−Free)
Shipping†
50 Units / Rail
4000 / Tape & Reel
RDSon
(W)
Ipk (mA)
11
450
11
450
11
450
11
450
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 6)
CASE 626A
ISSUE C
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
1
4
E1
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11774D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PDIP−7 (PDIP−8 LESS PIN 6)
PAGE 1 OF 1
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