NCP1034

NCP1034 100V Synchronous PWM Buck Controller Description The NCP1034 is a high voltage PWM controller designed for high performance synchronous Buck DC/DC applications with input voltages up to 100 V. The NCP1034 drives a pair of external N−MOSFETs. The switching frequency is programmable from 25 kHz up to 500 kHz allowing the flexibility to tune for efficiency and size. A synchronization feature allows the switching frequency to be set by an external source or output a synchronization signal to multiple NCP1034 controllers. The output voltage can be precisely regulated using the internally trimmed 1.25 V reference voltage for low voltage applications. Protection features include user programmable undervoltage lockout and hiccup current limit. Features http://onsemi.com MARKING DIAGRAM NCP1034D AWLYWWG SOIC−16 D SUFFIX CASE 751B A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package • • • • • • • • • • • • • • • • High Voltage Operating up to 100 V Programmable Switching Frequency up to 500 kHz 2 A Output Drive Capability Precision Reference Voltage (1.25 V) Programmable Soft−Start with Prebiased Load Capability Programmable Overcurrent Protection Programmable Undervoltage Protection Hiccup Current Limit Using MOSFET RDS(on) Sensing External Frequency Synchronization 16 Pin SOIC Package This is a Pb−Free Device 48 V Non−Isolated DC−DC Converter Embedded Telecom Systems Networking and Computing Voltage Regulator Distributed Point of Load Power Architectures General High Voltage DC−DC Converters VIN: 48 V VCC: 12 V R4 110k C2 100n C3 100n 12 5 15 4 16 1 14 R5 3k9 C5 220n R6 20k R7 11k D1 1N4148 8 VCC SYNC RT SS/SD UVLO OCSET GND IC1 NCP1034 9 HDRV VS OCIN LDRV PGND FB COMP 10 11 13 7 6 2 3 C6 R3 4k7 12n C7 330p R8 10k DRVVCC VB C4 100n C1A 2u2 PIN CONNECTIONS OCset 1 FB 2 Comp 3 SS/SD 4 SYNC 5 PGND 6 LDRV 7 DRVCC 8 (Top View) 16 UVLO 15 RT 14 GND 13 OCIN 12 VCC 11 VS 10 HDRV 9 VB Applications ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 22 of this data sheet. C1B 2u2 GND GND GND R10 10k GND Q1 NTD3055 L1 13m Q2 NTD24N06 VOUT 5 V @ 5 A, 200 kHz C9 47m C9B 47m C9C 47m R1 16k9 R9 1k2 C8 1n8 R2 5k6 GND GND GND GND GND GND Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 2 1 Publication Order Number: NCP1034/D VCC Bias Generator 1.25V = Vref POR Vref 5V = VBIAS GND UVLO Vcc UVLO SYNC Rt Rt Oscillator S Ct Q FAULT R Reset Dom S R Q POR VBIAS 20uA 64uA Max 1uA Error Amp Error Comparator OCP LowUVLO UV Detect Delay LS Positive Current Q DR POR OCP LowUVLO Clk OCP TONMIN Limit PWM UV High Voltage Level Shift Circuit UV Detect Vb HDrv Vs SS/SD DrvVCC NCP1034 Figure 2. Internal Block Diagram http://onsemi.com 25k 0.3V SS/SD Vref FAULT Iocset PWM MKO 350ns FAULT 0.25V AC ON SS/SD 2 1.25V LDrv Fb Comp PGND S OCP Q R 0.225x Iocset Active Clamp OCP Reset 0.0410x Iocset VBIAS VBIAS OCin AC ON OCset Positive Current Negative Output AC ON NCP1034 PIN FUNCTION DESCRIPTION PIN 1 2 3 4 PIN NAME OCset FB COMP SS/SD DESCRIPTION Current limit set point. A resistor from this pin to GND will set the positive and negative current limit threshold Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. Soft−Start / Shutdown. This pin provides user programmable soft−start function. External capacitor connected from this pin to ground sets the startup time of the output voltage. The converter can be shutdown by pulling this pin below 0.3 V. The internal oscillator can be synchronized to an external clock via this pin and other IC’s can be synchronized via this pin to internal oscillator. If it is not used this pin should be connected via 10 kW resistor to ground. Power Ground. This pin serves as a separate ground for the MOSFET driver and should be connected to the system’s power ground plane. Output driver for low side MOSFET. This pin provides biasing for the internal low side driver. A minimum of 0.1 mF, high frequency capacitor must be connected from this pin to power ground. This pin powers the high side driver and must be connected to a voltage higher than input voltage. A minimum of 0.1 mF, high frequency capacitor must be connected from this pin to switch node. Output driver for high side MOSFET Switch Node. This pin is connected to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is return path for the upper gate driver. This pin provides power for the internal blocks of the IC. A minimum of 0.1 mF, high frequency capacitor must be connected from this pin to ground. Overcurrent sensing input. A serial resistor from this pin to drain of low MOSFET must be used to limit the current into this pin. Signal ground for internal reference and control circuitry. Connecting a resistor from this pin to ground sets the oscillator frequency. An external voltage divider is used to set the undervoltage threshold levels. 5 6 7 8 9 10 11 12 13 14 15 16 SYNC PGND LDRV DRVVCC VB HDRV VS VCC OCIN GND RT UVLO http://onsemi.com 3 NCP1034 ABSOLUTE MAXIMUM RATINGS Rating VCC, DRVVCC Supply Voltage VFB, VUVLO VSYNC Vs Supply Voltage Vb Supply Voltage OCin Input Current All voltages referenced to GND Rating Thermal Resistance, Junction−to−Ambient Operating Ambient Temperature Range Storage Temperature Range Junction Operating Temperature ESD Withstand Voltage (Note 1) Human Body Model Machine Model Latchup Capability per Jedec JESD78 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Excluding pins Vb, VS and HDRV. Symbol RthJA TA TSTG TJ VESD Value 130 −40 to 125 −55 to 150 −40 to 150 2.0 200 Unit °C/W °C °C °C kV Symbol Min −0.3 −0.3 −0.3 −1 VS Max 20 10 5 150 VS + 20 20 Unit V V V V V mA TYPICAL ELECTRICAL PARAMETERS RECOMMENDED OPERATING CONDITIONS Symbol VIN VCC DRVCC VB to VS FSW TJ Converting Voltage Supply Voltage Supply Voltage Supply Voltage Operating Frequency Junction Temperature Definition Min 12 10 10 10 25 −40 Max 100 18 18 18 500 125 Unit V V V V kHz °C http://onsemi.com 4 NCP1034 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V, DRVVCC = VB = 12 V, −40°C < TJ < 125°C) Parameter REFERENCE VOLTAGE Feedback Voltage Accuracy FB Voltage Line Regulation SUPPLY CURRENT VCC Supply Current (Stat) DRVVCC Supply Current (Stat) VB Supply Current (Stat) UNDERVOLTAGE LOCKOUT VCC−Start−Threshold VCC−Stop−Threshold VCC−Hysteresis DRVCC−Start−Threshold DRVCC−Stop−Threshold DRVCC−Hysteresis VB−Start−Threshold VB−Stop−Threshold VB−Hysteresis Undervoltage Threshold Value Undervoltage Threshold Value OSCILLATOR Frequency Ramp Amplitude Min Duty Cycle Min Pulse Width Max Duty Cycle SYNC Frequency Range SYNC Pulse Duration SYNC High Level SYNC Low Level SYNC Input Threshold SYNC Input Hysteresis SYNC Input Impedance SYNC Output Impedance SYNC Output Pulse Width ERROR AMPLIFIER Input Bias Current IFB SS = 3 V, FB = 1 V −0.1 −0.4 mA FS Vramp Dmin Dmin(ctrl) Dmax SYNC(FS) SYNC(pulse) SYNC(H) SYNC(L) SYNC(Thre) SYNC(Hyst) SYNC(ZIN) SYNC(OUT) SYNC(Pulse Width) (Note 3) (Note 3) FS = 500 kHz, (Note 3) 300 16 2.5 300 1.6 RT = 20 kW RT = 10 kW (Note 3) FB = 2 V FS = 200 kHz, (Note 3) FS = 400 kHz, FB = 1.2 V 20% Above Free Running Frequency 200 2.0 0.8 80 500 170 320 200 375 2.0 0 200 230 430 kHz V % ns % kHz ns V V V mV kW kW ns UUVLO (Rising) UUVLO (Falling) VB_UVLO (R) VB_UVLO (F) DRVCC_UVLO (R) DRVCC_UVLO (F) VCC_UVLO (R) VCC_UVLO (F) Supply Ramping Up Supply Ramping Down Supply Ramping Up and Down Supply Ramping Up Supply Ramping Down Supply Ramping Up and Down Supply Ramping Up Supply Ramping Down Supply Ramping Up and Down 1.19 1.10 7.9 7.3 7.9 7.3 7.9 7.3 8.9 8.2 0.7 8.9 8.2 0.7 8.9 8.2 0.7 1.25 1.15 1.31 1.20 9.8 9.0 9.8 9.0 9.8 9.0 V V V V V V V V V V V ICC(Static) IC(Static) IB(Static) SS = 0 V, No Switching, RT = 10 kW, ROCSET = 10 kW SS = 0 V, No Switching SS = 0 V, No Switching 2.0 0.1 0.1 3.0 0.3 0.3 mA mA mA LREG VFB −40°C < TJ < 125°C 10 V < VCC < 18 V (Note 3) −1.5 1.25 +1.5 2.0 V % mV Symbol Test Condition Min Typ Max Unit 2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. 3. Guaranteed by design but not tested in production. http://onsemi.com 5 NCP1034 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V, DRVVCC = VB = 12 V, −40°C < TJ < 125°C) Parameter ERROR AMPLIFIER Source/Sink Current Bandwidth DC gain Transconductance SOFT−START/SD Soft−Start Current Shutdown Output Threshold OVERCURRENT PROTECTION OCSET Voltage Hiccup Current Hiccup Duty Cycle OUTPUT DRIVERS LO, Drive Rise Time HI Drive Rise Time LO Drive Fall Time HI Drive Fall Time Dead Band Time LO Output High Short Circuit Pulsed Current HI Output High Short Circuit Pulsed Current LO Output Low Short Circuit Pulsed Current HI Output Low Short Circuit Pulsed Current LO Output Resistor, Source LO Output Resistor, Sink HI Output Resistor, Source HI Output Resistor, Sink tr(Lo) tr(Hi) tf(Lo) tf(Hi) tdead tLDRVhigh tHDRVhigh tLDRVhigh tHDRVhigh RLOH RLOL RHIH RHIL CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) CL = 1.5 nF (See Figure 3) (See Figure 3) VLDRV = 0 V, PW v 10 ms, TJ = 25°C (Note 3) VHDRV = 0 V, PW v 10 ms, TJ = 25°C (Note 3) VLDRV = DRVVCC, PW v 10 ms, TJ = 25°C (Note 3) VHDRV = VB, PW v 10 ms, TJ = 25°C (Note 3) Typical Value @ 25°C, (Note 3) Typical Value @ 25°C, (Note 3) Typical Value @ 25°C, (Note 3) Typical Value @ 25°C, (Note 3) 30 17 17 10 10 60 1.4 2.2 1.4 2.2 7 2 7 2 12 8 12 8 120 ns ns ns ns ns A A A A W W W W VOCSET IHiccup Hiccup(duty) (Note 3) IHiccup/ISS, (Note 3) 1.25 1.0 5.0 V mA % ISS SD SS = 0 V 15 20 0.3 25 0.4 mA V gm I(Source/Sink) (Note 3) (Note 3) (Note 3) 1500 50 4.0 100 10 55 3150 4000 120 mA MHz dB mmho Symbol Test Condition Min Typ Max Unit 2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. 3. Guaranteed by design but not tested in production. http://onsemi.com 6 NCP1034 tr 9V High−Side Driver (HDrv) 2V tr 9V Low−Side Driver (LDrv) 2V Deadband H to L Deadband L to H tf tf Figure 3. Definition of Rise−Fall Time and Deadband Time http://onsemi.com 7 NCP1034 TYPICAL OPERATING CHARACTERISTICS 1.3 1.28 1.26 1.24 1.22 1.2 −40 UVLOVB (V) 9.0 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8.0 −20 0 20 40 60 80 100 120 7.9 −40 −20 0 20 40 60 80 100 120 Falling VB (V) Rising TEMPERATURE (°C) TEMPERATURE (°C) Figure 4. VFB Figure 5. UVLOVB 9.2 9.0 8.8 8.6 8.4 8.2 8.0 −40 Rising 9.2 9.1 9.0 UVLODRVVCC (V) 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 −20 0 20 40 60 80 100 120 8.1 −40 −20 0 20 40 60 80 100 120 Falling Rising UVLOVCC (V) Falling TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. UVLOVCC Figure 7. UVLODRVVCC 1.4 2.3 1.35 ICC (stat) (mA) 1.3 UVLO (V) 1.25 1.2 1.15 1.1 −40 Falling 2.2 Rising 2.1 2.0 1.9 1.8 −40 −20 0 20 40 60 80 TEMPERATURE (°C) 100 120 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 8. UVLO Figure 9. ICC (Stat) http://onsemi.com 8 NCP1034 220 215 210 fSW (kHz) Dmax (%) 205 200 195 190 185 180 −40 −20 0 20 40 60 80 100 120 90 88 86 84 82 80 78 76 74 72 70 −40 −20 0 20 40 60 80 100 120 Figure 10. Switching Frequency @ RT = 20 kW 210 205 200 gm (mmho) tonmin (ns) 195 190 185 180 175 170 −40 −20 0 20 40 60 80 100 120 2000 1500 3500 3000 2500 4500 4000 TEMPERATURE (°C) Figure 11. Maximum Duty Cycle @ f = 400 kHz TEMPERATURE (°C) −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Minimum on Time 90 85 80 75 70 t (ns) 65 60 55 50 45 40 −40 −20 0 20 40 60 80 100 120 High to Low Low to High R (W) 12 11 10 9 8 7 6 5 Figure 13. Error Amplifier Transconductance DRVVCC = VB = 10 V 12 V 18 V 4 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Deadtime Figure 15. Driver Pullup Resistance http://onsemi.com 9 NCP1034 4.0 3.5 VDSLOWFET (V) 120 3.0 R (W) 2.5 2.0 1.5 1.0 −40 DRVVCC = VB = 10 V −0.2 −0.21 −0.22 −0.23 −0.24 −0.25 −0.26 −0.27 −0.28 −0.29 −20 0 20 40 60 80 100 −0.3 −40 −20 0 20 40 60 80 100 120 12 V 18 V TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Driver Pulldown Resistance Figure 17. OCP @ R8 = 10 kW, ROCIN = 10 kW 0.8 0.7 0.6 VDSLOWFET (V) 0.5 0.4 0.3 0.2 0.1 0 −40 −20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 18. POSOCP @ R8 = 10 kW, ROCIN = 10 kW http://onsemi.com 10 NCP1034 Undervoltage Lock−out There are four undervoltage lock−out circuits. Two of them protect external high−side and low−side drivers, the third ensures that the IC does not start until VCC is under a set threshold. The last one can be programmed by the user. It has a rising threshold at 1.25 V and a falling threshold at 1.15 V, and the user can define the undervoltage level by an external resistor divider. If the voltage is not over the threshold value, the device stops operating. The high−side driver UVLO only stops switching the high−side MOSFET Programmed falling and rising UVLO voltage can be calculated by Equations 1 and 2: R4 V UVLO,falling + 1.15 @ 1 ) R5 (eq. 1) resistor can be selected from Figure 20, which shows switching frequency versus the timing resistor value. 500 450 400 350 f (kHz) 300 250 200 150 100 50 0 0 50 100 Rt (kW) 150 200 250 and R4 V UVLO,rising + 1.25 @ 1 ) R5 Shutdown (eq. 2) Figure 20. Frequency Dependence of Rt Value Frequency Synchronization The output voltage can be disabled by pulling the SS/SD pin below 0.3 V. A small transistor can be used to pull it down as shown in Figure 19. During this time, both external MOSFETs are turned off. After the SS/SD pin is released, the IC starts its operation with a soft−start sequence. SS/SD SS/SD Figure 19. Shutdown Interface Operating Frequency Selection The operating frequency is set by an external resistor connected from the Rt Pin to ground. The value of this The NCP1034 can be synchronized to an external clock signal. The input synchronization signal should be a TTL logic level. The oscillator is synchronized to the rising edge of the synchronizing signal. When synchronization is used, the free running frequency must be set by the timing resistor to a frequency at least 80% of the external synchronization frequency. The NCP1034 can also output synchronization pulses on the Sync pin. Pulses are generated when the internal oscillator ramp reaches the high threshold voltage. The frequency of these pulses is set by an external Rt resistor. Up to five NCP1034 controllers can be connected directly to the SYNC pin, all of which are synchronized to the controller with the highest frequency. The lowest frequency must be at least 80% of the highest one. The equivalent internal circuit of the Sync pin is shown in Figure 21. Connection options (without synchronization, external synchronization and master−slave synchronization) are shown on Figure 22. http://onsemi.com 11 NCP1034 VBIAS SYNC Rt Rt Oscillator Ct Figure 21. Equivalent Connection of the Sync Pin SYNC SYNC SYNC SYNC NCP1034 f = fres NCP1034 f = fext • 0.8 … fext SYNC NCP1034 f = fres a) NCP1034 f = fext • 0.8 … fext b) NCP1034 f = fext • 0.8 … fext c) Figure 22. Synchronization − a) Not Connect; b) External; c) Master Slave Synchronization Output Voltage Output Capacitor Selection Output voltage can be set by an external resistor divider according to this Equation 3: V OUT + V ref @ 1 ) R1 R2 (eq. 3) Where Vref is the internal reference voltage 1.25 V. Absolute values of resistors R1 and R2 depend on compensation network type. See compensation paragraph for details. Inductor Selection The output voltage ripple and transient requirements determine the output capacitor type and value. The important parameter for the selection of the output capacitor is equivalent serial resistance (ESR). If the capacitor has low ESR, it often has sufficient capacity for filtering as well as an adequate RMS current rating. The value of the output capacitor should be calculated using the following equation: C OUT w DI L 8 @ f @ DV OUT * DI L @ ESR (eq. 5) The inductor selection is based on the output power, frequency, input and output voltage and efficiency requirements. High inductor values cause low current ripple, slower transient response, higher efficiency and increased size. Inductor design can be reduced to desire maximum current ripple in the inductor. It is good to have current ripple (DILmax) between 20% and 50% of the output current. For buck converter, the inductor should be chosen according to Equation 4. L+ V OUT f @ DI Lmax 1* V OUT V INmax (eq. 4) For higher switching frequency, it is suitable to use multi−layer ceramic capacitor (MLCC) with very low ESR. The advantages are small size, low output voltage ripple and fast transient response. The disadvantage of MLCC type is the requirement to use a Type III compensation network. Input Capacitor Selection The input capacitor is used to supply current pulses while high−side MOSFET is on. When the MOSFET is off, the input capacitor is being charged. The value of this capacitor can be selected with Equation 6: http://onsemi.com 12 NCP1034 I OUT @ C IN w VOUT VIN @ 1* VOUT VIN (eq. 6) P SW + V DS(off) 2 @ tON ) t OFF @ f @ I OUT (eq. 10) f @ DV IN Where DVIN is the input voltage ripple and the recommended value is about 2% − 5% of VIN. The input capacitor must be large enough to handle the input ripple current. Its value should be calculated using Equation 7: V OUT @ 1 * I RMS + I OUT @ Power MOSFET Selection V IN VOUT VIN tON and tOFF times are dependent on the transistor gate. The MOSFET output capacitance loss is caused by the charging and discharging during the switching process and can be computed using Equation 11. P COSS + C OSS @ V IN 2 @ f 2 (eq. 11) (eq. 7) The NCP1034 uses two N−channel MOSFET’s. They can be primary selected by RDS(on), maximum drain−to−source voltage and gate charge. RDS(on) impacts conductive losses and gate charge impacts switching losses. The low side MOSFET is selected primarily for conduction losses, and the high−side MOSFET is selected to reduce switching losses especially when the output voltage is less than 30% of the input voltages. The drain−to−source breakdown voltage must be higher than the maximum input voltage. Conductive power losses can be calculated using the Equations 8 and 9: P COND*HIGHFET + I 2OUT @ R DS(on) @ P COND*LOWFET + I 2OUT @ R DS(on) @ 1 * VOUT (eq. 8) V IN V IN (eq. 9) Where COSS = CDS + CGS. Significant power dissipation is caused by the reverse recovery charge in the low−side MOSFET body diode, which conducts at dead time. This charge is needed to close the diode. The current from the input power supply flows through the high−side MOSFET to the low−side MOSFET body diode. This power dissipation can be calculated using Equation 12. P QRR + Q RR @ V IN @ f (eq. 12) V OUT QRR is the diode recovery charge as given in the manufacturer’s datasheet. For some types of MOSFETs, this dissipation may be dominant at high input voltages. It is necessary to take care when selecting a MOSFET. An external Schottky diode across the low−side MOSFET can be used to eliminate the reverse recovery charge power loss. The Schottky diode’s forward voltage should be lower than that of the body diode, and reverse recovery time (trr) should be lower then that of the body diode. The Schottky diode’s capacitance loss can be calculated as shown in Equation . P C(Schottky) + C Schottky @ V IN 2 @ f 2 (eq. 13) Switching losses are depended on drain−to−source voltage at turn−off state, output current and switch−on and switch−off time as is shown by Equation 10. http://onsemi.com 13 NCP1034 tdead tdead High−Side Logic Signal Low−Side Logic Signal td(on) RDSmax High−Side MOSFET RDS(on)min tr td(off) tr RDSmax Low−Side MOSFET RDS(on)min td(on) td(off) tf tf Figure 23. MOSFETs Timing Diagram MOSFETs delays, turn−on and turn−off times must be short enough to prevent cross conduction. If not, there will be cross conduction from the input through both MOSFETs to ground. Due to this fact, the following conditions must be true: t d(on)high ) t dead u t d(off)low ) t f low t d(on)low ) t dead u t d(off)high ) t f high (eq. 14) Where tdead is the controller dead band time, td(on), tr, td(off) and tf are MOSFETs parameters. These parameters can be found in the datasheet for specific conditions. Bootstrap Circuit This circuit is used to obtain a voltage higher than the input voltage in order to switch−on high side N MOSFET. The bootstrap capacitor is charged from the IC’s supply voltage through D1, when the low side MOSFET is switched−on up to the IC’s supply voltage. It must have enough capacity to supply power for the high−side circuit when the high−side MOSFET is being switched on. The minimum value recommended for the bootstrap capacitor is 100 nF. Diode D1 has to be designed to withstand a reverse voltage given by the following equation: D1 VRmin + V IN * V CC Soft−Start (eq. 15) The soft−start time is set by capacitor connected between SS/SD Pin and ground. This function is used for controlling the output voltage slope and limiting startup currents. The start−up sequence initiates when Power On Ready (POR) internal signal rises to logic high level. That means the supply voltage, low side drive supply voltage and external UVLO are over the set thresholds. The soft−start capacitor is charged by 20 mA current source. If POR is low, the SS/SD Pin is internally pulled to GND, which means that the NCP1034 is in a shutdown state. The SS/SD Pin voltage (0 V to 2.6 V) controls internal current source (64 mA to 0 mA) with negative linear characteristic. This current source injects current into the resistor (25 kW) connected between the Fb pin and negative input of the error amplifier and into the external feedback resistor network. Voltage drop on these resistors is over 1.6 V, which is enough to force the error amplifier into negative saturation state and to block switching. When the soft−start pin reaches around 1.2 V (exact value depends on feedback and compensation network and on soft−start capacitor; a larger soft−start capacitor and a lower compensation capacity decrease this level) the IC starts switching. The impact of controlled current source decreases and the output voltage starts to rise. When the soft−start capacitor voltage reaches 2.6 V, the output voltage is at nominal value. The soft−start time must be at least 10 times longer than the time needed to charge the compensation network from the output of the error amplifier. If the soft−start time is not long enough, the soft−start sequence would be faster than the charging compensation network and the IC would start without slowly increasing the output voltage. The soft−start capacitance can be calculated using Equation 16. C SS + 15 @ 10 −6 @ T SS (eq. 16) http://onsemi.com 14 NCP1034 POR 5V SS 0V VOUT 64mA IFB >1.6V 1.25V FB Voltage 1.25V 0V ~2.6V ~1.2V Figure 24. Soft−Start Start to Prebiased Output The NCP1034 is able to startup into a prebiased output capacitor. The low−side MOSFET does not turn on before high−side MOSFET gets the first turn−on pulse. During this time, the energy is not discharged by the low−side MOSFET until the soft−start sequence crosses the programmed output voltage. VOUT ~2.6V ~1.2V SS ~5V LDRV HDRV Figure 25. Startup to Prebiased Output Overcurrent Protection The voltage drop across the low side MOSFET RDS(on) is connected through resistor R8 and into the IC though pin 13 OCin. Within the IC, this value is compared with the value programmed by resistor R7 to set the overcurrent limit. The programmed current limit is set by selecting the value of R7, which is connected between pin 1 OCset and GND. If the voltage drop is larger than the set value, the NCP1034 goes into hiccup mode. During this time, both external MOSFETs are turned off and the soft start capacitor is discharged with a current equal to 5% of the charging current. The capacitor continues to discharge until the voltage reaches 0.25 V, and then the IC initiates a standard soft start sequence. The recommended value for the protection resistor R8 is 10 kW. The R7 resistance value can be calculated using Equation 17: R7 + R8 3.56 @ R DS(on) @ I pk (eq. 17) http://onsemi.com 15 NCP1034 5V ~2.6V SS ~1.2V ~1.2V 0.3V ~1.2V ~1.9V 0.3V ~1.9V 0.3V 5V ~2.6V ~1.2V VOUT IOUT ROUT Figure 26. Overcurrent Protection (Hi−Cup Mode) The NCP1034 provides protection of the low−side MOSFET against positive overcurrent (from output to this MOSFET). Its value can be calculated using Equation 18: I Pos + 5125 * 0.184 @ R8 R7 @ R DS(on) (eq. 18) f P0 + 1 2 @ p @ L @ C OUT (eq. 19) One zero of this LC filter is given by the output capacitance and output capacitor ESR. Its value can be calculated by using the following equation: f Z0 + 1 2 @ p @ C OUT @ ESR (eq. 20) Compensation Circuit The NCP1034 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45°). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows: Table 1. COMPENSATION TYPES Zero Crossover Frequency Condition fP0 < fZ0< f0 < fS/2 fP0 < f0< fZ0 < fS/2 fP0 < f0 < fS/2 < fZ0 The next parameter that must be chosen is the zero crossover frequency f0. It can be chosen to be 1/10 − 1/5 of the switching frequency. These three parameters show the necessary type of compensation that can be selected from Table 1. Compensation Type Type II (PI) Type III (PID) Method I Type III (PID) Method II Typical Output Capacitor Type Electrolytic, Tantalum Tantalum, Ceramic Ceramic Compensation Type II (PI) This compensation is suitable for low−cost electrolytic capacitor. The zero created by the capacitor’s ESR is a few kHz and the zero crossover frequency is chosen to be 1/10 of the switching frequency. Components of the PI compensation (Figure 27) network can be specified by the following equations: http://onsemi.com 16 NCP1034 VOUT R1 − + R2 Vref for tantalum output capacitors, which have a higher ESR than ceramic, and its zeros and poles can be calculated shown below: f Z1 + 0.75 @ f P0 OTA RC1 f Z2 + f P0 f P2 + f Z0 f P3 + CC1 CC2* (eq. 22) fS 2 The second one (method II) is for ceramic capacitors: f Z2 + f 0 @ 1 * sin q max 1 ) sin q max 1 ) sin q max 1 * sin q max (eq. 23) *Optional Figure 27. PI compensation (II Type) 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 f P2 + f 0 @ R C1 + C C1 + C C2 + f Z1 + 0.5 @ f Z2 f P3 + 0.5 @ fS The remaining calculations are the same for both methods. (eq. 21) 1 p @ R C1 @ f S V OUT * V ref R1 + @ R2 V ref R C1 uu C C1 + C C2 + C FB1 + R FB1 + R1 + 2 gm 1 2 @ p @ f Z1 @ R C1 1 2 @ p @ f P3 @ R C1 2 @ p @ f 0 @ L @ V RAMP @ C OUT V IN @ R C1 1 2p @ C FB1 @ f P2 1 * R FB1 (eq. 24) VRAMP is the peak−to−peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional. Compensation Type III (PID) Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This situation needs to be compensated by the PID compensation network that is show in Figure 28. V OUT C C2 R FB1 R1 C FB1 R C1 − OTA + C C1 2 @ p @ C FB1 @ f Z2 V ref R2 + @ R1 V OUT * V ref To check the design of this compensation network, the equation must be true R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 @ R1 @ R2 u 1 (eq. 25) gm If it is not true, then a higher value of RC1 must be selected. Input Power Supply R2 V REF The NCP1034 controller and built−in drivers need to be powered through VCC, DRVVCC and Vb pins with a voltage between 10 V – 18 V. The supply current requirement is a summation of the static and dynamic currents. Static current consumption can be calculated by the following equation: I CS + I CC ) I C ) I B (eq. 26) Figure 28. PID Compensation (III Type) There are two methods to select the zeros and poles of compensation network. The first one (method I) is useable http://onsemi.com 17 NCP1034 Dynamic current consumption is calculated using the following equation, base on the switching frequency and MOSFET gate charge. I CD + Q G(low) ) Q G(high) @ f (eq. 27) To power the device, an external power supply or voltage regulator from VIN can be used. Two options are a linear shunt voltage regulator and a shunt voltage regulator with transistor, as shown in Figure 29. A voltage regulator without a transistor can be used when the power consumption is low and zener diode power dissipation is acceptable. Otherwise, a shunt regulator with transistor can be used. VIN VIN VCC VCC R D C D C Figure 29. Linear Shunt Voltage Regulator Figure 30. Shunt Voltage Regulator with Transistor For the linear shunt voltage regulator (option a) the VCC voltage is the same as the zener diode reverse voltage VZ. The value of the resistor R can be calculated using Equation 28, where IZT is the minimum reverse current at VZ. The value selected should be lower than the calculated value. The maximum power losses of resistor R and the zener diode D can be calculated by Equations 29 and 30. Rt V INmin * V CC I CS ) ICD ) I ZT (eq. 28) (eq. 29) (eq. 30) DC current gain. The maximum power dissipation of the resistor, zener diode and transistor are calculated by Equations 32 to 34. The transistor reverse breakdown voltage must be selected to be able to withstand the voltage difference between maximum input voltage and VCC. Rt V INmin * V ZT I CS )I b CD ) IZT ) I ZT @ V ZT @ V ZT (eq. 31) P R + (V INmax * V CC) @ (I CS ) I CD) PD + V INmax * V CC R * ICS P R + V INmax * V CC @ PD + PD + I CS ) I CD b * I CS b I CS b (eq. 32) V INmax * V ZT R V INmax * V ZT R (eq. 33) The shunt voltage regulator with transistor (option b) is advantageous when the zener diode loss is too high or when input voltage varies across a wide range and it is difficult to set a bias point. The output voltage is lower than VZ due to the VBE of the transistor. The maximum resistor value of R can be calculated by Equation 31, where b is the transistor Table 2. POWER SUPPLY REGULTOR EXAMPLES Components LS−FET HS−FET LS−FET HS−FET MOSFETs NTD24N06 NTD3055 NTD24N06 NTD24N06 QG(TOT) (nC) 24 7.1 24 24 300 60 20 f (kHz) 200 VINmax (V) 60 VINmin (V) 36 * (eq. 34) (eq. 35) P T + V INmax * V CC @ I CS ) ICD ISUPPLYmax (mA) 8.7 RBIAS (kW) 2.6 ZD MMSZ4699 Transistor − 16.9 10 MMSZ4699 MJD31 PCB Layout The layout of high−frequency and high−current switching converters has a large impact on the circuit parameters. It is important, therefore, to pay close attention to the PCB layout. http://onsemi.com 18 NCP1034 The input capacitor, MOSFETs, inductor and output capacitor should be placed as close as possible to one another. This is suitable to reduce EMI and to minimize VS overshoots. Connecting the signal and power ground at one point near the output connector improves load regulation. Connection between the source pin of the low side MOSFET and the IC should be very short with wide traces and optimally using two layers to achieve minimum inductance between them. The blocking and bootstrap capacitors should be placed as close as possible to the IC. The feedback and compensation network should be close to the IC to minimize noise. TYPICAL APPLICATION X1−1 48 V $20% X1−2 X2−2 C9 47m C9B 47m C9C 47m R1 16k9 R9 1k2 C8 1n8 R3 IC1 NCP1034SMD 4k7 C7 GND GND GND GND GND GND 330p GND C6 12n R15 0R 5V@5A, 200kHz X2−1 R2 5k6 R11A R11B R11C R11D R11E 10k 10k 10k 10k 10k MMSZ4699 GND C3 100n D2 C10 100n GND GND GND C2 100n 8 VCC SYNC RT SS/SD UVLO OCSET GND 9 HDRV VS OCIN LDRV PGND FB COMP 10 11 13 7 6 2 3 R8 10k D1 1N4148 C4 100n Q2 NTD3055 L1 13m Q3 NTD24N06 C1A 2u2 C1B 2u2 12 5 DRVVCC VB GND R4 110k 15 4 16 1 14 R5 3k9 R10 C5 10k 220n R6 20k R7 10k Figure 31. Single Output Buck Converter from 38 V − 58 V to 5 V/5 A @ 200 kHz 90 85 80 EFFICIENCY (%) 75 70 65 60 55 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 38 V 48 V VIN = 58 V IOUT (A) Figure 32. Efficiency and Power Loss of Circuit at Figure 31 http://onsemi.com 19 NCP1034 Bill of Materials Designator R9 R5 R3 R2 R1 R6 R11A, R11B, R11C, R11D, R11E R4 R7, R8, R10 C8 C6 C5 C7 C2, C3, C4, C10 C9A, C9B, C9C C1A, C1B L1 D1 D2 Q2 Q3 IO1 Qty 1 1 1 1 1 1 5 Description Resistor Resistor Resistor Resistor Resistor Resistor Resistor Value 1k2 3k9 4k7 5k6 16k9 20k 12k Tolerance Footprint 1% 1% 1% 1% 1% 1% 1% 1206 1206 1206 1206 1206 1206 1206 Manufacturer Vishay Vishay Vishay Vishay Vishay Vishay Vishay Manufacturer Part Number CRCW10261K20FKEA CRCW10263K90FKEA CRCW10264K60FKEA CRCW10265K60FKEA CRCW102616K9FKEA CRCW102620K0FKEA CRCW102612K0FKEA 1 3 1 1 1 1 4 3 2 1 1 1 1 1 1 Resistor Resistor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Inductor SMD Switching Diode Zener Diode 12V Power N−MOSFET Power N−MOSFET Synchronous PWM Buck Controller 110k 10k 1n8 12n 220n 330p 100n 47m/6.3V 2.2m/100V 13m MMSD4148 MMSZ4699 NTD3055 NTD24N06 NCP1034 1% 1% 10% 10% 10% 10% 10% 20% 10% 20% − − − − − 1206 1206 1206 1206 1206 1206 1206 1210 1210 13x13 SOD123 SOD123 DPAK DPAK SOIC16 Vishay Vishay Kemet Kemet Kemet Kemet Kemet Kemet Murata Würth ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor CRCW1206110KFKEA CRCW120610K0FKEA C1206C182K5FA−TU C1206C123K5FACTU C1206C224K5RACTU − C1206F104K1RACTU C1210C476M9PAC7800 GRM32ER72A225KA35L 744355131 MMSD4148T1G MMSZ4699T1G NTD3055−150G NTD24N06T4G NCP1034DR2G http://onsemi.com 20 NCP1034 Figure 33. Top Layer Figure 34. Bottom Layer Figure 35. Top Side Components Figure 36. Bottom Side Components http://onsemi.com 21 NCP1034 44 mm_ Figure 37. Typical Application Board Photos ORDERING INFORMATION Device NCP1034DR2G Package SOIC−16 (Pb−Free) Shipping† 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 70 mm_ http://onsemi.com 22 NCP1034 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 −B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S SOLDERING FOOTPRINT* 6.40 16X 8X 1.12 16 1 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP1034), may be covered by one or more of the following U.S. patents; 6,097,075; 7,176,723; 6,362,067. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 23 NCP1034/D