NCP1091

NCP1090, NCP1091, NCP1092 Integrated IEEE 802.3af PoE-PD Interface Controller Description The NCP1090, NCP1091 and NCP1092 are members of ON Semiconductor’s high power HIPOt Power over Ethernet Powered Device (PoE−PD) product family and integrate an IEEE 802.3af PoE−PD interface controller. The 3 variants all incorporate the required functions as such detection, classification, under voltage lockout, inrush and operational current limit. A power good signal has been added to guarantee a good enabling/disabling of the DC−DC controller. In addition, the NCP1091 offers a programmable under−voltage while the NCP1092 provide an auxiliary pin for applications supporting auxiliary supplies. The NCP1090, NCP1091 and NCP1092 are fabricated in a robust high voltage process and integrates a rugged vertical N−channel DMOS suitable for the most demanding environments and capable of withstanding harsh environments such as hot swap and cable ESD events. The NCP1090, NCP1091 and NCP1092 complement ON Semiconductor’s ASSP portfolio in industrial devices and can be combined with stepper motor drivers, CAN bus drivers and other high−voltage interfacing devices to offer complete solutions to the industrial and security market. Features http://onsemi.com SOIC−8 S SUFFIX CASE 751AZ TSSOP−8 T SUFFIX CASE 948S PIN CONFIGURATION INRUSH CLASS DET VPORTN (Top View) * NCP1090 = NC NCP1091 = UVLO NCP1092 = AUX 8 XXXXX AYWWG G 1 XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package 1 VPORTP * PGOOD RTN • • • • • • • • • • • Fully Supports IEEE 802.3af Specifications Programmable Classification Current Adjustable Under Voltage Lock Out (NCP1091 Only) Open−Drain Power Good Indicator 130 mA Inrush Current Limit 500 mA Operational Current Limit Pass Switch Disabling Input for Rear Auxiliary Supply Operation (NCP1092 Only) Over−temperature Protection Industrial Temperature Range −40°C to 85°C with Full Operation up to 125°C Junction Temperature 0.5 W Hot−swap Pass−switch Vertical N−channel DMOS Pass−switch Offers the Robustness of Discrete MOSFETs ORDERING INFORMATION Device NCP109xxxx NCP109xxxx Package SOIC−8 (Pb−Free) TSSOP−8 (Pb−Free) Shipping† 2500/Tape & Reel 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 2 1 Publication Order Number: NCP1090/D NCP1090, NCP1091, NCP1092 VPORTP DETECTION DET INTERNAL SUPPLY & VOLTAGE REFERENCE THERMAL SHUTDOWN UVLO EXTERNAL SELECTION NCP1091 only UVLO CLASS CLASSIFICATION VPORT MONITOR IEEE Interface Shutdown (AUX supply priority) NCP1092 only AUX HOT SWAP SWITCH INRUSH INRUSH & OPERATIONAL CURRENT LIMIT CONTROL & CURRENT LIMIT BLOCKS POWER GOOD INDICATOR PGOOD VPORTN RTN Figure 1. NCP1090/91/92 Functional Block Diagram http://onsemi.com 2 NCP1090, NCP1091, NCP1092 Simplified Application Diagrams RJ−45 VPORTP Data Pairs Rdet DB1 Rclass Z_line Cline DET PGOOD Cpd CLASS NCP1090 INRUSH RTN Spare Pairs DB2 NC To DC−DC Converter Rinrush VPORTN Figure 2. Typical Application Circuit using the NCP1090 RJ−45 VPORTP Data Pairs DB1 Rdet DET Rclass Z_line Cline PGOOD Cpd CLASS NCP1091 INRUSH RTN UVLO Ruvlo2 VPORTN To DC−DC Converter Rinrush Ruvlo1 Spare Pairs DB2 Figure 3. Typical Application Circuit using the NCP1091 with External UVLO Setting http://onsemi.com 3 NCP1090, NCP1091, NCP1092 Table 1. PIN DESCRIPTION Pin No. Name INRUSH CLASS DET VPORTN RTN PGOOD NC UVLO NCP1090 1 2 3 4 5 6 7 − NCP1091 1 2 3 4 5 6 − 7 NCP1092 1 2 3 4 5 6 − − Type Output Output Output, Open Drain Ground Ground Output, Open Drain − Input Description Current limit programming pin. Connect a resistor between INRUSH and VPORTN. Classification current programming pin. Connect a resistor between CLASS and VPORTN. Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a valid PD detection signature. Negative input power. Connected to the source of the internal pass−switch DC−DC controller power return. Connected to the drain of the internal pass−switch Open Drain Power Good Indicator. Pin is in HZ mode when the power good signal is active. No connection Under−voltage lockout input. Voltage with respect to VPORTN. Connect a resistor−divider from VPORTP to UVLO to VPORTNx to set an external UVLO threshold. Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows a supply transition from PSE to the rear auxiliary supply connected between VPORTP and RTN. Positive input power. Voltage with respect to VPORTN. AUX − − 7 Input VPORTP 8 8 8 Input Operating Conditions Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VPORTP RTN CLASS INRUSH AUX UVLO PGOOD Ta Tj Tj−TSD Tstg TθJA ESD−HBM ESD−CDM ESD−MM LU Parameter Input power supply Analog ground supply 2 Analog output Analog output Analog input Analog input Analog output Ambient temperature Junction temperature Junction temperature (Note 1) Storage Temperature Thermal Resistance, Junction to Air (Note 2) Human Body Model Charged Device Model Machine Model Latch−up Min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −40 − − −55 150 160 2 500 200 ±100 Max 72 72 72 3.6 72 3.6 72 85 125 175 150 240 260 Units V V V V V V V °C °C °C °C °C/W kV V V mA SOIC−8 TSSOP−8 per EIA−JESD22−A114 standard per ESD−STM5.3.1 standard per EIA−JESD22−A115−A standard per JEDEC Standard JESD78 Thermal shutdown condition Conditions Voltage with respect to VPORTN Pass−switch in off−state (voltage with respect to VPORTN) Voltage with respect to VPORTN Voltage with respect to VPORTN Voltage with respect to VPORTN Voltage with respect to VPORTN Voltage with respect to RTN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. Low qJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural convection. Refer to Jedec JESD51 for details. http://onsemi.com 4 NCP1090, NCP1091, NCP1092 Recommended Operating Conditions Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the recommended operating conditions for extended periods of time may affect device reliability. Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol INPUT SUPPLY VPORT Input supply voltage 0 57 V VPORT = VPORTP – VPORTN Parameter Min Typ Max Units Conditions SIGNATURE DETECTION Offset_det1 Sleep_det1 Offset_det2 Sleep_det2 CLASSIFICATION Vcl_on Vcl_off Vclass_reg Icl_bias Iclass0 Iclass1 Iclass2 Iclass3 Iclass4 Classification current turn−on lower threshold Classification current turn−off upper threshold Classification buffer output voltage I(vportp) quiescent current during classification Class 0: Rclass 4420 W (Note 3) Class 1: Rclass 953 W (Note 3) Class 2: Rclass 549 W (Note 3) Class 3: Rclass 357 W (Note 3) Class 4: Rclass 255 W (Note 3) 0 9 17 26 36 9.8 21 9.8 600 − − − − − 4 12 20 30 44 11.3 13 24 V V V mA mA mA mA mA mA VPORTP rising VPORTP rising 13 V < VPORTP < 21 V I(class) excluded 13 V < VPORTP < 21 V 13 V < VPORTP < 21 V 13 V < VPORTP < 21 V 13 V < VPORTP < 21 V 13 V < VPORTP < 21 V 13 V < VPORTP < 21 V I(VPORTP) + I(RTN) I(VPORTP) + I(RTN) I(VPORTP) + I(RTN) + I(DET) I(VPORTP) + I(RTN) + I(DET) 73 390 2 15 77 400 5 21 81 412 mA mA mA mA VPORTP = RTN = 1.9 V Rdet = 24.9 KW VPORTP = RTN = 9.8 V Rdet = 24.9 KW VPORTP = RTN = 1.9 V Rdet = 24.9 KW VPORTP = RTN = 9.8 V Rdet = 24.9 KW UVLO − INTERNAL SETTING − NCP1090/91/92 Vuvlo_on Vuvlo_off Vhyst_int Uvlo_filter Default turn on voltage Default turn off voltage UVLO internal hysteresis UVLO On / Off filter time − 29.6 − − 37 31 6 100 40 − − − V V V mS V V V mA V 0.6 − V KW For information only For information only VPORTP rising VPORTP falling UVLO − EXTERNAL SETTING – NCP1091 ONLY Vuvlo_pr Vuvlo_on2 Vhyst_off2 Uvlo_ipd UVLO external programming range External UVLO turn on voltage External UVLO turn off voltage UVLO internal pull down current 25 1.14 0.95 − − 1.2 1 2.5 50 1.26 1.05 − VPORTP rising AUXILIARY SUPPLY SETTING – NCP1092 ONLY Aux_h Aux_l Aux_pd AUX input high level voltage AUX input low level voltage AUX internal pull down resistor 3.1 − 100 − − − 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. http://onsemi.com 5 NCP1090, NCP1091, NCP1092 Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.) Symbol Parameter Min Typ Max Units Conditions PASS−SWITCH AND CURRENT LIMITING Ron I_inrush I_ilim Pass−switch Rds−on Inrush current with Rinrush = 178 kW Operating current limit with Rinrush = 178 kW − 75 425 0.5 120 500 1 170 575 W mA mA Measured with I(RTN) = 200 mA Measured at RTN−VPORTN = 3 V Current limit threshold POWER GOOD INDICATOR Vds_pgood_on Vds_pgood_off Pgood_filter Ipgood Vpgood_low RTN−VPORTN threshold voltage required for power good status RTN−VPORTN latchoff threshold voltage PGOOD filter time I(PGOOD) sinking current PGOOD voltage output low − − 0.8 9 1 10 100 − 0.2 5 0.5 1.2 11 V V mS mA V Voltage with respect to RTN RTN−VPORTN falling RTN−VPORTN rising Rising and falling / for information only CURRENT CONSUMPTION IvportP I(VPORTP) internal current consumption − 600 900 mA VPORTP = 48 V THERMAL SHUTDOWN TSD Thyst Thermal shutdown threshold Thermal hysteresis 150 − − 15 − − °C Tj °C Tj Tj = junction temperature Tj = junction temperature THERMAL RATINGS Ta Tj Ambient temperature Junction temperature −40 − − − 85 125 °C °C 3. A tolerance of 1% on the Rclass resistor is included in the min/max values. http://onsemi.com 6 NCP1090, NCP1091, NCP1092 Description of Operation Powered Device Interface Under Voltage Lock Out (UVLO) The integrated PD interface supports the IEEE 802.3af defined operating modes: detection signature, current source classification, undervoltage lockout, inrush and operating current limits. The following sections give an overview of these previous processes. Detection During the detection phase, the incremental equivalent resistance seen by the PSE through the cable must be in the IEEE 802.3af standard specification range (23.70 kW to 26.30 kW) for a PSE voltage from 2.7 V to 10.1 V. In order to compensate for the non−linear effect of the diode bridge and satisfy the specification at low PSE voltage, the NCP1090/91/92 present a suitable impedance in parallel with the 24.9 kW Rdet external resistor. For some types of diodes (especially Schottky diodes), it may be necessary to adjust this external resistor. The Rdet resistor has to be inserted between VPORTP and DET pins. During the detection phase, the DET pin is pulled to ground and goes in high impedance mode (open−drain) once the device exit this mode, reducing thus the current consumption on the cable. Classification The NCP1090/91/92 incorporate a fixed under voltage lock out (ULVO) circuit which monitors the input voltage and determines when to turn on the pass switch and charge the dc−dc converter input capacitor before the power up of the application. The NCP1091 offers a fixed or adjustable Vuvlo_on threshold depending if the UVLO pin is used or not. In Figure 5, the UVLO pin is strapped to ground and the Vuvlo_on threshold is defined by the internal level. VPORTP VPORT UVLO VPORTN1,2 Figure 5. Default Internal UVLO Configuration (NCP1091 only) Once the PSE device has detected the PD device, the classification process begins. In classification, the PD regulates a constant current source that is set by the external resistor RCLASS value on the CLASS pin. Figure 4 shows the schematic overview of the classification block. The current source is defined as: Iclass + VPORTP VPORTP EN 1.2 V To define the UVLO threshold externally, the ULVO pin must be connected to the center of an external resistor divider between VPORTP and VPORTN as shown in Figure 6. In order to guarantee the detection signature, the equivalent input resistor made of the Ruvlo1, Ruvlo2 and Rdet should be equal to 24.9 kW. VPORTP Ruvlo1 Rdet DET Ruvlo2 UVLO VPORTN1,2 9.8 V Rclass Class_enable VPORT CLASS 9.8 V NCP1091 Figure 6. Default Internal UVLO Configuration (NCP1091 only) VPORTN For a Vuvlo_on desired turn−on voltage threshold, Ruvlo1 and Ruvlo2 can be calculated using the following equations: Ruvlo + 24.9 k @ Rdet Rdet * 24.9 k Figure 4. Classification Block Diagram Power Mode with and Ruvlo1 ) Ruvlo2 + Ruvlo Ruvlo2 + 1.2 @ Ruvlo Vuvlo_on When the classification hand−shake is completed, the PSE and PD devices move into the operating mode. With: Vuvlo_on: Desired Turn−On voltage threshold http://onsemi.com 7 NCP1090, NCP1091, NCP1092 Example for a Targeted Uvlo_on of 35 V: Let’s start with a Rdet of 30.1 kΩ. This gives a Ruvlo of 144 kΩ made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of 140 kΩ (closest values from E96 series). Note that there is a pull down current of 2.5 mA typ on the UVLO. Assuming the previous example, this pull down current will create a (non critical) systematic offset of 350 mV on the Uvlon_on level of 35 V. The external UVLO hysteresis on the NCP1091 is about 15 percent typical. Inrush and Operational Current Limitations Both inrush and operational current limit are defined by an external Rinrush resistor connected between INRUSH and VPORTN. The low inrush current limit allows smooth charge of large dc−dc converter input capacitor by limiting the power dissipation over the internal pass switch. In power mode, the operational current limit protects the pass switch and the PD application against excessive transient current and failure on the dc−dc converter output. Once the input supply reached the Vulvo_on level, the charge of Cpd capacitor starts with a current limitation set to to the INRUSH level. When this capacitor is fully charged, the current limit switches without any spikes from the inrush current to the operational current level and the power good indicator on PGOOD pin is turned on. The capacitor is considered to be fully charged once the following conditions are satisfied: 1. The drain−source voltage of the Pass Switch has decreased below the Vds_pgood_on level (typical 1 V) 2. The gate−source voltage of the Pass Switch is sufficiently high (above 2 V typical) which means the current in the pass switch has decreased below the current limit. This mechanism is depicted in the following Figure 7. PGOOD Pgood_on Inrush current limit 0 Operational current limit 1 Pgood_on Delay 100 mS VDDA1 & detector 1 V / 10 V RTN VDDA1 VDDA1 2V Vds_pgood comparator VPORTNx Vgs_pgood comparator Sense Resistor Pass Switch RTN Figure 7. Inrush and Operational Current Limitation Selection Mechanism The operational current limit and the power good indicator stays active as long as RTN voltage stays below the vds_pgood_off threshold (10 V typical) and the input supply stay above the Vulvo_off level. Therefore, fast and large voltage step lower than 10 V are tolerated on the input without interruption of the converter controller. Higher input transient will not affect the behavior if RTN does not exceed 10 V for more than 100 mS. Such input voltage steps may be introduced by a PSE which is switched to a higher power supply. In case RTN is still above 10 V after this delay, the power good is turned off and the pass switch current limit falls back to the inrush level. PGOOD Indicator The NCP1090/91/92 integrate a Power Good indicator circuitry indicating the end of the dc−dc converter input capacitor charge, and the enabling of the operational current limit. This indicator is implemented on the PGOOD pin which goes in open drain state when active and which is pulled to ground during turn off. A possible usage of this PGOOD pin is illustrated in Figure 8. During the inrush phase, the converter controller is forced in standby mode due to the PGOOD pin forcing low the under voltage lock out pin of the controller. Once the Cpd capacitor is fully charged, PGOOD goes in open drain state, allowing the start up sequence of the converter controller. http://onsemi.com 8 NCP1090, NCP1091, NCP1092 VPORTP Rdet DET Rclass PGOOD Cpd NCP1090 INRUSH RTN VDD UVLO NCP103x DC−DC Converter Controller OVLO GATE VSS CLASS Rinrush VPORTN Figure 8. Power GOOD Implementation Auxiliary Supply To support application connected to non−PoE enabled networks and minimize the bill of materials, the NCP1093 supports drawing power from an external supply and allows simplified designs with PoE or auxiliary supply priorities. RJ−45 VAUX (+) In most of the cases, the auxiliary supply is connected between VPORTP and RTN with a serial diode between VPORTP and VAUX, as shown in Figure 9. VPORTP Data Pairs DB1 Rdet DET Rclass Z_line Cline PGOOD Cpd CLASS NCP1092 INRUSH RTN Spare Pairs DB2 AUX To DC−DC Converter Rinrush VPORTN VAUX (−) Figure 9. Auxiliary Supply Dominant PD Interface The NCP1092 offers an AUX input pin which turns off the pass switch when pulled high. This feature is useful for PD applications where the auxiliary supply has to be dominant over the PoE supply. When the auxiliary supply is inserted on a POE powered application, the pass switch disconnection will move the current path from the PSE to the rear auxiliary supply. Since the current delivered by the PSE will goes below the DC MPS level (specified in IEEE 802.3 af/at standard), the PSE will disconnect the PoE−PD and the application will remain supplied by the auxiliary supply. The transition will happens without any power conversion interruption since the PGOOD indicator stays active (high impedance state). Next Figure 10 depicts an other PD application where the POE supply is dominant over the VAUX supply. A diode D1 has been added in order to not corrupt the PD detection signature when the dc−dc converter is supplied by VAUX. http://onsemi.com 9 NCP1090, NCP1091, NCP1092 RJ−45 VAUX (+) D1 VPORTP Data Pairs DB1 Rdet DET Rclass Cline PGOOD Cpd CLASS NCP1092 INRUSH RTN Spare Pairs DB2 AUX To DC−DC Converter Z_line Rinrush VPORTN VAUX (−) Figure 10. PoE Supply Dominant PD Interface Thermal Shutdown Company or Product Inquiries The NCP1090/91/92 include a thermal shutdown which protect the device in case of high junction temperature. Once the thermal shutdown (TSD) threshold is exceeded, the classification block, the pass switch and the PGOOD indicator are disabled. The NCP109X returns automatically to normal operation once the die temperature has fallen below the TSD low limit. For more information about ON Semiconductor’s Power over Ethernet products visit our Web site at http://www.onsemi.com. http://onsemi.com 10 NCP1090, NCP1091, NCP1092 PACKAGE DIMENSIONS SOIC−8 CASE 751AZ−01 ISSUE O http://onsemi.com 11 NCP1090, NCP1091, NCP1092 PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE C 8x K REF 0.10 (0.004) M 0.20 (0.008) T U S TU S V S 2X L/2 8 5 L PIN 1 IDENT 1 4 B −U− J J1 K1 K 0.20 (0.008) T U S A −V− C SECTION N−N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 --1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.114 0.122 0.169 0.177 --0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.076 (0.003) D −T− SEATING PLANE G DETAIL E N N F DETAIL E All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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