NCP1239FD65R2G

DATA SHEET www.onsemi.com Fixed Frequency Current‐Mode Controller for Flyback Converter SOIC−7 CASE 751U NCP1239 PIN CONNECTIONS The NCP1239 is a fixed-frequency current-mode controller featuring a high-voltage start-up current source to provide a quick and lossless power-on sequence. This function greatly simplifies the design of the auxiliary supply and the VCC capacitor by activating the internal start-up current source to supply the controller during start-up, transients, latch, stand-by etc. With a supply range up to 35 V, the controller hosts a jittered 65 or 100-kHz switching circuitry operated in peak current mode control. When the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to minimum level of 26 kHz. As the power further goes down, the part enters skip cycle while limiting the peak current that insures excellent efficiency in light load condition. NCP1239 features a timer-based fault detection circuitry that ensures a quasi-flat overload detection, independent of the input voltage. Features • Fixed-Frequency 65-kHz or 100-kHz Current-Mode Control • • • • • • • • • • • • • • • • Operation Frequency Foldback Down to 26 kHz and Skip Mode to Maximize Performance in Light Load Conditions Adjustable Over Power Protection (OPP) Circuit High-Voltage Current Source with Brown-Out (BO) Detection Internal Slope Compensation Internal Fixed Soft-Start Frequency Jittering in Normal and Frequency Foldback Modes 64-ms Timer-Based Short-Circuit Protection with Auto-Recovery or Latched Operation Pre-Short Ready for Latched OCP Versions Latched OVP on VCC – Autorecovery for C and E Versions Latched OVP/OTP Input for Improved Robustness 35-V VCC Operation ±500 mA Peak Source/Sink Drive Capability Internal Thermal Shutdown Extremely Low No-Load Standby Power Pin-to-Pin Compatible with the Existing NCP1236/1247 Series These Devices are Pb-Free and are RoHS Compliant 8 HV 3 6 VCC 4 5 DRV Fault 1 FB 2 CS GND MARKING DIAGRAM 8 1239xfff ALYWX G 1 1239xfff = Specific Device Code x = A, B, C, D, E, F, G, H, I, J, K, L, M, N, P, Q or R fff = 065 or 100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information on page 26 of this data sheet. Typical Applications • AC-DC Converters for TVs, Set-Top Boxes and Printers • Offline Adapters for Notebooks and Netbooks © Semiconductor Components Industries, LLC, 2016 September, 2023 − Rev. 26 1 Publication Order Number NCP1239/D NCP1239 Vbulk . OVP . Vout NCP1239 8 . 1 2 3 6 4 5 OPP adjsut. NTC Figure 1. Application Schematic (OPP Adjustment) Table 1. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 Fault 2 FB Hooking an optocoupler collector to this pin will allow regulation. 3 CS This pin monitors the primary peak current but also offers an overpower compensation adjustment. When the CS pin is brought above 1.2 V, the part is permanently latched off. 4 GND The controller ground. 5 DRV The driver’s output to an external MOSFET gate. 6 VCC This pin is connected to an external auxiliary voltage. An OVP comparator monitors this pin and offers a means to latch the converter in fault conditions. 7 NC Non-connected for improved creepage distance. 8 HV Connected to the bulk capacitor or rectified ac line, this pin powers the internal current source to deliver a startup current. It is also used to provide the brown-out detection and the HV sensing for the Overpower protection. The controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. A precise pull up current source allows direct interface with an NTC thermistor. Fault detection triggers a latch. www.onsemi.com 2 NCP1239 Table 2. DEVICE OPTION AND DESIGNATIONS Device Frequency OCP Protection OCP Timer Vcc OVP Threshold Vcc OVP Protection Fault pin Protection BO Levels BO Timer Soft− start Timer DSS Function NCP1239AD65R2G 65 kHz Latch 64 ms 25.5 V Latch Latch 110 / 101 68 ms 8 ms Disable NCP1239BD65R2G 65 kHz Auto− Recovery 64 ms 25.5 V Latch Latch 110 / 101 68 ms 8 ms Disable NCP1239CD65R2G 65 kHz Auto− Recovery 64 ms 25.5 V Auto− Recovery Latch 110 / 101 68 ms 8 ms Disable NCP1239DD65R2G 65 kHz Auto− Recovery 64 ms 25.5 V Latch Latch 101 / 95 68 ms 8 ms Disable NCP1239ED65R2G 65 kHz Auto− Recovery 64 ms 25.5 V Auto− Recovery Auto− Recovery 110 / 101 68 ms 8 ms Disable NCP1239FD65R2G 65 kHz Latch 64 ms 32 V Latch Latch 229 / 176 68 ms 4 ms Disable NCP1239HD65R2G 65 kHz Latch 64 ms 25.5 V Latch Latch 229 / 224 68 ms 8 ms Disable NCP1239ID65R2G 65 kHz Latch 128 ms 25.5 V Latch Latch 101 / 95 68 ms 4 ms Disable NCP1239JD65R2G 65 kHz Latch 128 ms 32 V Latch Latch 101 / 95 68 ms 8 ms Enable NCP1239KD65R2G 65 kHz Auto− Recovery 128 ms 25.5 V Auto− Recovery Auto− Recovery 110 / 101 68 ms 8 ms Disable NCP1239LD65R2G 65 kHz Auto− Recovery 128 ms 25.5 V Latch Latch 82 / 77 68 ms 4 ms Disable NCP1239MD65R2G 65 kHz Auto− Recovery 128 ms 32 V Auto− Recovery Auto− Recovery 229 / 224 68 ms 4 ms Enable NCP1239ND65R2G 65 kHz Auto− Recovery 128 ms 32 V Auto− Recovery Latch 229 / 224 68 ms 4 ms Enable NCP1239PD65R2G 65 kHz Auto− Recovery 64 ms 25.5 V Auto− Recovery Auto− Recovery 82 / 79 68 ms 8 ms Disable NCP1239QD65R2G 65 kHz Auto− Recovery 128 ms 25.5 V Auto− Recovery Auto− Recovery 82 / 79 68 ms 8 ms Disable NCP1239RD65R2G 65 kHz Auto− Recovery 128 ms 25.5 V Latch Latch 101 / 95 272 ms 4 ms Disable NCP1239AD100R2G 100 kHz Latch 64 ms 25.5 V Latch Latch 110 / 101 68 ms 8 ms Disable NCP1239BD100R2G 100 kHz Auto− Recovery 64 ms 25.5 V Latch Latch 110 / 101 68 ms 8 ms Disable NCP1239DD100R2G 100 kHz Auto− Recovery 64 ms 25.5 V Latch Latch 101 / 95 68 ms 8 ms Disable NCP1239ED100R2G 100 kHz Auto− Recovery 64 ms 25.5 V Auto− Recovery Auto− Recovery 110 / 101 68 ms 8 ms Disable NCP1239GD100R2G 100 kHz Latch 64 ms 25.5 V Latch Latch 95 / 86 136 ms 8 ms Disable NCP1239LD100R2G 100 kHz Auto− Recovery 128 ms 25.5 V Latch Latch 82 / 77 68 ms 4 ms Disable www.onsemi.com 3 NCP1239 NC VFault(OVP) Vdd 600−ns time constant Clock IOTP OVP/OTP gone? Up counter Fault HV sample BO BO end RST 4 Vfault(clamp) HV detection & sampling BO TSD VFault(OTP) Option for OVP_VCC HV Dual HV startup current source TSD Vcc(reset) S Latch Q UVLO Q Vdd Vcc(reset) R Skip Vcc logic management Vdd OVP_VCC Jitter 20us time constant TSD end Rup Vskip Stop Foldback FB Vcc VCC(OVP) BO end Clock Oscillator 65 kHz / 100 kHz /4 Slope Compensation + Clamp S Drv Q PWM Q Soft−start Ramp 8 ms HV sample R Soft−start OPP Current Generation Latch Ibias CS TSD Overcurrent S Iopp Vdd OCP_flag Q VLimit1 Q Skip LEB R 300 ns PWM LEB Up counter 120 ns 4 OVP_VCC (option) Protection Mode RST Reset VLimit2 OCP_flag Dmax GND BO SS end OCP Timer 64 ms OCP Fault gone? Auto−recovery Timer UVLO 1s Vcc(reset) Figure 2. Simplified Block Diagram www.onsemi.com 4 NCP1239 Table 3. MAXIMUM RATINGS Rating Symbol Value Unit VCC −0.3 to 35 V −0.3 to 5.5 V VDRV −0.3 to 20 V HV −0.3 to 650 V Thermal Resistance Junction-to-Air Single Layer PCB 25 mm@, 2 Oz Cu Printed Circuit Copper Clad RθJ−A 250 °C/W Maximum Junction Temperature TJ(max) 150 °C Storage Temperature Range TSTG −60 to 150 °C ESDHBM ESDMM 4 200 kV V 1 kV Power Supply Voltage, VCC Pin, Continuous Voltage Maximum Voltage on Low Power Pins CS, FB and Fault Maximum Voltage on DRV Pin High Voltage Pin ESD Capability (Note 2) Human Body Model – All Pins Except HV Machine Model Charged-Device Model ESD Capability per JEDEC JESD22−C101E Moisture Sensitivity Level MSL 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per JEDEC JESD22−A114F ESD Machine Model tested per JEDEC JESD22−A115C Charged-Device Model ESD Capability tested per JEDEC JESD22−C101E Latch-up Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78 0V vDRV (t ) V1 V1,max = −0.75V, Tj = −25°C V1,max = −0.65V, Tj = −25°C V1,max = −0.3V, Tj = −125°C Worst-case V1 must stay below -0.3 V for an all-temperature operation -1 V 500 ns Figure 3. Negative Pulse for DRV Pin www.onsemi.com 5 NCP1239 Table 4. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Parameter Test Conditions Symbol Min Typ Max Unit Minimum Voltage for Current Source Operation IHV = 90% ISTART2, VCC = VCC(on) − 0.5 V VHV(min) − 25 60 V Current Flowing Out of VCC Pin VCC = 0 V ISTART1 0.2 0.5 0.8 mA Current Flowing Out of VCC Pin VCC = VCC(on) – 0.5 V ISTART2 1.5 3 4.5 mA HV Pin Leakage Current VHV = 325 V ILEAK1 − 8 20 mA Start-Up Threshold HV Current Source Stop Threshold VCC Increasing VCC(on) 11.0 12.0 13.0 V HV Current Source Restart Threshold VCC Decreasing VCC(min) 9.0 10.0 11.0 V Minimum Operating Voltage VCC Decreasing VCC(off) 8.0 8.8 9.4 V Operating Hysteresis VCC(on) = VCC(off) VCC(hys) 3.0 − − V VCC(inhibit) 0.7 1.2 1.7 V VCC(reset) 6.5 7 7.5 V START-UP SECTION SUPPLY SECTION VCC Level for ISTART1 to ISTART2 Transition VCC Level where Logic Functions are Reset VCC Decreasing Internal IC Consumption VFB = 3.2 V, FSW = 65 kHz and CL = 0 ICC1 − 1.4 2.2 mA Internal IC Consumption VFB = 3.2 V, FSW = 65 kHz and CL = 1 nF ICC2 − 2.1 3.0 mA Internal IC Consumption VFB = 3.2 V, FSW = 100 kHz and CL = 0 ICC1 − 1.7 2.5 mA Internal IC Consumption VFB = 3.2 V, FSW = 100 kHz and CL = 1 nF ICC2 − 3.1 4.0 mA Internal IC Consumption in Skip Cycle VCC = 12 V, VFB = 0.775 V Driving 8 A/600 V MOSFET ICC(stb) − 500 − mA Internal IC Consumption in Skip Cycle L, P and Q versions VCC = 12 V, VFB = 0.775 V Driving 8 A/600 V MOSFET ICC(stb) − 565 − mA Internal IC Consumption in Fault Mode Fault or Latch ICC3 − 400 − mA Internal IC Consumption in Fault Mode L, P and Q versions Fault or Latch ICC3 − 480 − mA Internal IC Consumption before Start-Up VCC(min) < VCC < VCC(on) ICC4 − 310 − mA Internal IC Consumption before Start-Up VCC < VCC(min) ICC5 − 20 − mA DRIVE OUTPUT Rise Time (10−90%) VDRV from 10 to 90% VCC = VCC(off) + 0.2 V, CL = 1 nF tR − 40 − ns Fall Time (90−10%) VDRV from 90 to 10% VCC = VCC(off) + 0.2 V, CL = 1 nF tF − 30 − ns Source Resistance ROH − 6 − W Sink Resistance ROL − 6 − W ISOURCE − 500 − mA Peak Source Current DRV High State, VDRV = 0 V (Note 1) VCC = VCC(off) + 0.2 V, CL = 1 nF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Guaranteed by design 2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off. www.onsemi.com 6 NCP1239 Table 4. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Parameter Test Conditions Symbol Min Typ Max Unit ISINK − 500 − mA VDRV(low) 8.8 − − V VDRV(clamp) 11.0 13.5 16.0 V IBIAS − 1 − mA VLIMIT1 0.752 0.800 0.848 V DRIVE OUTPUT Peak Sink Current DRV Low State, VDRV = VCC (Note 1) VCC = VCC(off) + 0.2 V, CL = 1 nF High State Voltage (Low VCC Level) VCC = 9 V, RDRV = 33 kW DRV High State High State Voltage (High VCC Level) VCC = VCC(OVP) – 0.2 V, DRV High State and Unloaded CURRENT COMPARATOR Input Pull-Up Current VCS = 0.7 V Maximum Internal Current Setpoint TJ from −40°C to +125°C (No OPP) Abnormal Over-Current Fault Threshold TJ = +25°C (No OPP) VLIMIT2 1.10 1.20 1.30 V Default Internal Voltage Set Point for Frequency Foldback Trip Point ~59% of VLIMIT VFOLD(CS) − 475 − mV Internal Peak Current Setpoint Freeze ~31% of VLIMIT VFREEZE(CS) − 250 − mV Propagation Delay from VLIMIT Detection to Gate Off-State DRV Output Unloaded tDEL − 50 100 ns Leading Edge Blanking Duration tLEB1 − 300 − ns Abnormal Over-Current Fault Blanking Duration for VLIMIT3 tLEB2 − 120 − ns tCOUNT − 4 − Number of Clock Cycles before Fault Confirmation Internal Soft-Start Duration Activated upon startup or auto−recovery A, B, C, D, E, G, H, J, K, P or Q versions F, I, L, M, N or R versions tSS ms − 8 − − 4 − INTERNAL OSCILLATOR Oscillation Frequency (65-kHz Version) fOSC 60 65 70 kHz Oscillation Frequency (100-kHz Version) fOSC 92 100 108 kHz Maximum Duty-Cycle DMAX 76 80 84 % fJITTER − ±5 − % fSWING − 240 − Hz Frequency Jittering In Percentage of fOSC – Jitter is Kept even in Foldback Mode Swing Frequency FEEDBACK SECTION Equivalent AC Resistor from FB to GND (Note 1) REQ − 25 − kW Internal Pull-Up Voltage on FB Pin FB open VFB(ref) 4.1 4.3 − V VFB to Current Setpoint Division Ratio Feedback Voltage below which the Peak Current is Frozen KFB − 4 − VFREEZE − 1.0 − V VFOLD − 1.90 − V FREQUENCY FOLDBACK Frequency Foldback Level on FB Pin ≈ 59% of Maximum Peak Current Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Guaranteed by design 2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off. www.onsemi.com 7 NCP1239 Table 4. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Parameter Test Conditions Symbol Min Typ Max Unit fTRANS 22 26 30 kHz VFOLD(end) − 1.50 − V VSKIP − 0.80 − V VSKIP(hyst) − 30 − mV S65 S100 − − −29 −45 − − mV/ms KOPP − 0.54 − mA/V FREQUENCY FOLDBACK Transition Frequency below which Skip-Cycle Occurs VFB = VSKIP + 0.5 V End of Frequency Foldback Feedback Level fSW = fMIN Skip-Cycle Level Voltage on FB Pin Hysteresis on the Skip Comparator (Note 1) INTERNAL RAMP COMPENSATION Compensation Ramp Slope FSW = 65 kHz, RUP = 30 kW FSW = 100 kHz, RUP = 30 kW OVERPOWER COMPENSATION (OPP) VHV to IOPP Conversion Ratio Current Flowing Out of CS Pin (Note 2) VHV = 125 V VHV = 162 V VHV = 328 V VHV = 365 V IOPP(125) IOPP(162) IOPP(328) IOPP(365) − − − 105 0 20 110 130 − − − 150 mA Current Flowing Out of CS Pin for L version (Note 2) VHV = 108 V VHV = 145 V VHV = 294 V VHV = 327 V IOPP(108) IOPP(145) IOPP(294) IOPP(327) − − − 105 0 20 110 130 − − − 150 mA Percentage of Applied OPP Current VFB < VFOLD IOPP1 − 0 − % Percentage of Applied OPP Current VFB > VFOLD + 0.7 V (VOPP) IOPP2 − 100 − % Clamped OPP Current VHV > 365 V IOPP3 105 130 150 mA tWD(OPP) − 32 − ms Watchdog Timer for DC Operation BROWN-OUT (BO) Brown-Out Thresholds (A,B,C,E & K versions) VHV Increasing VBO(on) 100 110 120 V Brown-Out Thresholds (A,B,C,E & K versions) VHV Decreasing VBO(off) 93 101 109 V Brown-Out Thresholds (D, I, J and R versions) VHV Increasing VBO(on) 92 101 110 V Brown-Out Thresholds (D, I, J and R versions) VHV Decreasing VBO(off) 87 95 103 V Brown-Out Thresholds (F version only) VHV Increasing VBO(on) 211 229 247 V Brown-Out Thresholds (F version only) VHV Decreasing VBO(off) 164 176 188 V Brown-Out Thresholds (G version only) VHV Increasing VBO(on) 86 95 104 V Brown-Out Thresholds (G version only) VHV Decreasing VBO(off) 79 86 93 V Brown-Out Thresholds (H, M and N versions) VHV Increasing VBO(on) 211 229 247 V Brown-Out Thresholds (H, M and N versions) VHV Decreasing VBO(off) 208 224 240 V Brown-Out Thresholds (L version only) VHV Increasing VBO(on) 74 82 90 V Brown-Out Thresholds (L version only) VHV Decreasing VBO(off) 70 77 84 V Brown−out thresholds (P and Q versions) VHV increasing VBO(on) 74 82 90 V Brown−out thresholds (P and Q versions) VHV decreasing VBO(off) 72 79 86 V Brown-Out Timer Duration (A, B, C, D, E, F, H, I, J, K, L, M, N, P and Q versions) VHV Decreasing tBO 54 68 82 ms Brown-Out Timer Duration (G version only) VHV Decreasing tBO 110 136 162 ms Brown-Out Timer Duration (R version only) VHV Decreasing tBO 216 272 324 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Guaranteed by design 2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off. www.onsemi.com 8 NCP1239 Table 4. ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max Values TJ = −40°C to +125°C, VHV = 125 V, VCC = 11 V unless otherwise noted) Parameter Test Conditions Symbol Min Typ Max Unit FAULT INPUT (OTP/OVP) Over-Voltage Protection Threshold VFAULT Increasing VFAULT(OVP) 2.8 3.0 3.2 V Over-Temperature Protection Threshold VFAULT Decreasing VFAULT(OTP) 0.37 0.40 0.43 V NTC Biasing Current VFAULT = 0 V IOTP 39 45 51 mA Additional NTC Biasing Current during Soft-Start Only VFAULT = 0 V − During Soft-Start Only IOTP_boost 38 44 50 mA Latch Clamping Voltage IFAULT = 0 mA VFAULT(clamp)0 1.1 1.35 1.6 V Latch Clamping Voltage IFAULT = 1 mA VFAULT(clamp)1 2.2 2.7 3.2 V Blanking Time after Drive Turn Off tLATCH(blank) − 1 − ms Number of Clock Cycles before Latch Confirmation tLATCH(count) − 4 − OVER-CURRENT PROTECTION (OCP) Internal OCP Timer Duration A, B, C, D, E, F, G, H and P versions tOCP 51 64 77 ms Internal OCP Timer Duration I, J, K, L, M, N, Q and R versions tOCP 102 128 154 ms tAUTOREC 0.85 1 1.35 s Auto-Recovery Timer VCC OVER-VOLTAGE (VCC OVP) Latched Over Voltage Protection on VCC Pin A, B, C, D, E, G, H, I, K, L, P, Q or R versions VCC(OVP) 24.0 25.5 27.0 V Latched Over Voltage Protection on VCC Pin F, J, M and N versions VCC(OVP) 30.0 32.0 34.0 V tOVP(delay) − 20 − ms Delay before OVP on VCC Confirmation THERMAL SHUTDOWN (TSD) Temperature Shutdown TJ Increasing (Note 1) TSHDN 135 150 165 °C Temperature Shutdown Hysteresis TJ Decreasing (Note 1) TSHDN(hys) − 20 − °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Guaranteed by design 2. CS pin source current is a sum of IBIAS and IOPP, thus at VHV = 125 V is observed the IBIAS only, because IOPC is switched off. www.onsemi.com 9 NCP1239 13.0 11.0 12.5 10.5 VCC(min) (V) VCC(on) (V) TYPICAL PERFORMANCE CHARACTERISTICS 12.0 11.5 11.0 −40 10.0 9.5 −20 0 20 40 60 80 100 9.0 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 4. VCC(on) vs. Junction Temperature Figure 5. VCC(min) vs. Junction Temperature 1.7 1.5 VCC(inhibit) (V) VCC(off) (V) 9.2 8.8 8.4 1.3 1.1 0.9 8.0 −40 −20 0 20 40 60 80 100 0.7 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 6. VCC(off) vs. Junction Temperature Figure 7. VCC(inhibit) vs. Junction Temperature 4.0 3.0 3.6 ICC2 (mA) ICC2 (mA) 2.6 2.2 3.2 2.8 2.4 1.8 2.0 1.4 −40 −20 0 20 40 60 80 100 1.6 −40 120 Temperature (5C) −20 0 20 40 60 80 100 120 Temperature (5C) Figure 8. ICC2 (65-kHz Version) vs. Junction Temperature Figure 9. ICC2 (100-kHz Version) vs. Junction Temperature www.onsemi.com 10 NCP1239 0.8 4.5 0.7 4.0 0.6 3.5 ISTART2 (mA) ISTART1 (mA) TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.4 0.3 0.2 −40 2.5 2.0 −20 0 20 40 60 80 100 1.5 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 10. ISTART1 vs. Junction Temperature Figure 11. ISTART2 vs. Junction Temperature 0.84 24 20 0.82 16 VLIMIT1 (V) ILEAK1 (mA) 3.0 12 8 0.80 0.78 4 0 −40 −20 0 20 40 60 80 100 0.76 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 12. ILEAK1 vs. Junction Temperature Figure 13. VLIMIT1 vs. Junction Temperature 40 1.30 35 30 tDEL (ns) VLIMIT2 (V) 1.25 1.20 25 20 1.15 15 1.10 −40 −20 0 20 40 60 80 100 10 −40 120 Temperature (5C) −20 0 20 40 60 80 100 Temperature (5C) Figure 14. VLIMIT2 vs. Junction Temperature Figure 15. tDEL vs. Junction Temperature www.onsemi.com 11 120 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS 380 120 340 tLEB2 (ns) tLEB1 (ns) 100 300 260 220 80 60 180 140 −40 −20 0 20 40 60 80 100 40 −40 120 60 80 100 120 Figure 17. tLEB2 vs. Junction Temperature 70 68 fOSC (kHz) tSS (ms) 40 Figure 16. tLEB1 vs. Junction Temperature 8 7 66 64 62 −20 0 20 40 60 80 100 60 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 18. tSS vs. Junction Temperature Figure 19. fOSC (65-kHz Version) vs. Junction Temperature 108 84 104 82 DMAX (%) fOSC (kHz) 20 Temperature (5C) 9 100 96 92 −40 0 Temperature (5C) 10 6 −40 −20 80 78 −20 0 20 40 60 80 100 76 −40 120 Temperature (5C) −20 0 20 40 60 80 100 120 Temperature (5C) Figure 20. fOSC (100-kHz Version) vs. Junction Temperature Figure 21. DMAX vs. Junction Temperature www.onsemi.com 12 NCP1239 TYPICAL PERFORMANCE CHARACTERISTICS 26 150 140 24 IOOP3 (mA) REQ (kW) 25 23 120 22 21 −40 −20 0 20 40 60 80 100 110 −40 120 0 20 40 60 80 100 120 Temperature (5C) Figure 22. REQ vs. Junction Temperature Figure 23. IOOP3 vs. Junction Temperature 109 116 105 VBO(off) (V) VBO(on) (V) −20 Temperature (5C) 120 112 108 101 97 104 100 −40 130 −20 0 20 40 60 80 100 93 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 24. VBO(on) vs. Junction Temperature Figure 25. VBO(off) vs. Junction Temperature 82 3.2 78 3.1 VFAULT(OVP) (V) tBO (ms) 74 70 66 62 3.0 2.9 58 54 −40 −20 0 20 40 60 80 100 2.8 −40 120 −20 0 20 40 60 80 100 120 Temperature (5C) Temperature (5C) Figure 26. tBO vs. Junction Temperature Figure 27. VFAULT(OVP) vs. Junction Temperature www.onsemi.com 13 NCP1239 0.43 51 0.42 49 0.41 47 IOTP (mA) VFAULT(OTP) (V) TYPICAL PERFORMANCE CHARACTERISTICS 0.40 0.39 43 0.38 41 0.37 −40 −20 0 20 40 60 80 100 39 −40 120 0 20 40 60 80 100 120 Temperature (5C) Figure 28. VFAULT(OTP) vs. Junction Temperature Figure 29. IOTP vs. Junction Temperature 1.3 1.2 tAUTOREC (s) 69 65 61 57 −40 1.1 1.0 0.9 −20 0 20 40 60 80 100 0.8 −40 120 0 20 40 60 80 100 120 Temperature (5C) Figure 30. tOCP vs. Junction Temperature Figure 31. tAUTOREC vs. Junction Temperature 26.5 26.0 25.5 25.0 24.5 24.0 −40 −20 Temperature (5C) 27.0 VCC(OVP) (V) −20 Temperature (5C) 73 tOCP (ms) 45 −20 0 20 40 60 80 100 120 Temperature (5C) Figure 32. VCC(OVP) vs. Junction Temperature www.onsemi.com 14 NCP1239 DEFINITION General Frequency Foldback Capability The NCP1239 implements a standard current mode architecture where the switch-off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part-count and cost effectiveness are the key parameters, particularly in low-cost ac-dc adapters, open-frame power supplies etc. The NCP1239 packs all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non-dissipative over power protection (OPP), a brown-out protection or HV start-up current source. A continuous flow of pulses is not compatible with no-load/light-load standby power requirements. To excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.9 V, the oscillator starts to reduce its switching frequency as the feedback level continues to decrease. When the feedback level reaches 1.5 V, the frequency hits its lower stop at 26 kHz. When the feedback pin goes further down and reaches 1.0 V, the peak current setpoint is internally frozen. Below this point, if the power continues to drop, the controller enters classical skip-cycle mode at a 31% frozen peak current. Current-Mode Operation with Internal Ramp Compensation Internal Soft-Start A soft-start precludes the main power switch from being stressed upon start-up. In this controller, the soft-start is internally fixed to 8 ms. Soft-start is activated when a new start-up sequence occurs or during an auto-recovery hiccup. Implementing peak current mode control operating at a 65 or 100-kHz switching frequency, the NCP1239 offers a fixed internal compensation ramp that can easily by summed up to the sensed current. The controller can be used in CCM applications with wide input voltage range thanks to its fixed ramp compensation that prevents the appearance of sub-harmonic oscillations Fault Input The NCP1239 includes a dedicated fault input accessible via its fault pin (pin 1). It can be used to sense an over-voltage condition on the adapter. The circuit can be latched off by pulling the pin above the upper fault threshold, VFAULT(OVP), typically 3.0 V. The controller is also disabled if the fault pin voltage, VFAULT, is pulled below the lower fault threshold, VFAULT(OTP), typically 0.4 V. The lower threshold is normally used for detecting an over-temperature fault (by the means of an NTC). Internal Brown-Out Protection A portion of the bulk voltage is internally sensed via the high-voltage pin monitoring (pin 8). When the voltage on this pin is too low, the part stops pulsing. No re-start attempt is made until the controller senses that the voltage is back within its normal range. When the brown-out comparator senses the voltage is acceptable, de-latch occurs and the controller authorizes a re-start synchronized with VCC(on). OVP Protection on VCC It is sometimes interesting to implement a circuit protection by sensing the VCC level. This is what this controller does by monitoring its VCC pin. When the voltage on this pin exceeds Vcc(ovp) threshold, the pulses are immediately stopped and the part enters in an endless hiccup or auto-recovery mode depending on controller options. Adjustable Overpower Compensation The high input voltage sensed on the HV pin is converted into a current. This current builds an offset superimposed on the current sense voltage which is proportional to the input voltage. By choosing the resistance value in series with the CS pin, the amount of compensation can be adjusted to the application. Short-Circuit/Overload Protection Short-circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). Here, every time the internal 0.8-V maximum peak current limit is activated, an error flag is asserted and a time period starts, thanks to the 64-ms timer. When the fault is validated, all pulses are stopped and the controller enters an auto-recovery burst mode, with a soft-start sequence at the beginning of each cycle. An internal timer keeps the pulses off for 1 s typically which, associated to the 64-ms pulsing re-try period, ensures a duty-cycle in fault mode less than 10%, independent from the line level. As soon as the fault disappears, the SMPS resumes operation. Please note that some version offers an auto-recovery mode as we just described, some do not and latch off in case of a short-circuit. High-Voltage Start-Up Low standby power results cannot be obtained with the classical resistive start-up network. In this part, a high-voltage current-source provides the necessary current at start-up and turns off afterwards. An option is available to activate the Dynamic Self−Supply (DSS). The start−up current source is turned on to supply the controller if the Vcc voltage drops below a certain level in light load. EMI Jittering An internal low-frequency modulation signal varies the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To improve the EMI signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). www.onsemi.com 15 NCP1239 HV CURRENT SOURCE PIN • Over Power Protection: HV Pin Voltage is Sensed to The NCP1239 HV circuitry provides three features: • Start-Up Current Source to Charge the VCC Capacitor • Determine the Amount of OPP Current Flowing Out the CS Pin at Power On Brown-Out Protection: when the HV Pin Voltage is below VBO(off) for the 68-ms Blanking Time (136 ms for G version), the NCP1239 Stops Operating and Recovers whenthe HV Pin Voltage Exceeds VBO(on) The HV pin can be connected either to the bulk capacitor or to the input line terminals through a diode. It is further recommended to implement one or two resistors (in the range of 2.2 kW) to reduce the noise that can be picked-up by the HV pin. START-UP SEQUENCE • Charge from VCC(inhibit) to VCC(min): The start-up time of a power supply largely depends on the time necessary to charge the VCC capacitor to the controller start-up threshold (VCC(on) which is 12 V typically). The NCP1239 high-voltage current-source provides the necessary current for a prompt start-up and turns off afterwards. The delivered current (ISTART1) is reduced to less than 0.5 mA when the VCC voltage is below VCC(inhibit) (1.2 V typically). This feature reduces the die stress if the VCC pin happens to be accidentally grounded. When VCC exceeds VCC(inhibit), a 3-mA current (ISTART2) is provided and charges the VCC capacitor. Please note that the internal IC consumption is increased from few mA to 310 mA (ICC4) when VCC crosses VCC(min) in order to have internal logic wake-up when VCC reaches VCC(on). The VCC charging time is then the total of the three following durations: • Charge from 0 V to VCC(inhibit): t START1 + V CC(inhibit) @ C V CC I START1 * ICC5 t START2 + ǒVCC(min) * VCC(inhibit)Ǔ @ CV CC I START2 * ICC5 • Charge from VCC(min) to VCC(on): t START3 + ǒVCC(on) * VCC(min)Ǔ @ CV CC I START2 * ICC4 t START1 + t START2 + (eq. 1) t START3 + 12 @ 22 u 500 u * 20 u + 55 ms (10 * 1.2) @ 22 u 3 m * 20 u (12 * 10) @ 22 u 3 m * 310 u + 65 ms + 16 ms Vcc(on) Vcc(min) Vcc(inhibit) tstart1 (eq. 3) Assuming a 22-mF VCC capacitor is selected and replacing ISTART1, ISTART2, ICC4, ICC5, VCC(inhibit) and VCC(on) by their typical values, it comes: t START + t START1 ) t START2 ) t START3 + 136 ms vcc(t) (eq. 2) tstart2 tstart3 Figure 33. The VCC at Start-Up is Made of Two Segments Given the Short-Circuit Protection Implemented on the HV Source www.onsemi.com 16 (eq. 4) (eq. 5) (eq. 6) (eq. 7) NCP1239 When the DSS mode is enable (NCP1239JD65), the VCC voltage is maintained between VCC(on) and VCC(min) by turning the HV start−up current source on and off. This function can be used only during transient load or in light load condition. The HV current source cannot supply the controller in Fixed−frequency operation otherwise the die will overheat. As a result, an auxiliary voltage source is needed to supply VCC during normal operation. If the VCC capacitor is first dimensioned to supply the controller for the traditional 5 to 50 ms until the auxiliary winding takes over, no-load standby requirements usually cause it to be larger. The HV start-up current source is then a key feature since it allows keeping short start-up times with large VCC capacitors (the total start-up sequence duration is often required to be less than 1 s). BROWN-OUT CIRCUITRY start-up threshold and an auto-recovery brown-out protection. Both levels are independent from the input voltage ripple. The brown-out thresholds are fixed (see levels in the electrical characteristics table), but they are designed to fit most of standard ac-dc converter applications. The simplified internal schematic appears in Figure 34 while typical operating waveforms are drawn in Figure 35 and Figure 36. For the vast majority of controllers, input line sensing is performed via a resistive network monitoring the bulk voltage or the incoming ac signal. When in the quest of low standby power, the external network adds a consumption burden and deteriorates the power supply standby power performance. Owing to its proprietary high-voltage technology, ON Semiconductor now offers onboard line sensing without using an external network. The system includes a 90-MW resistive network that brings a minimum Vbulk HV N L1 Rbo_H BO_OK EMI Filter Rbo_L GND VBO Figure 34. A Simplified View of the Brown-Out Circuitry When the HV pin voltage drops below the VBO(off) threshold, the brown-out protection trips: the controller stops generating DRV pulses once the BO timer elapses. VCC is discharged to VCC(min) by the controller consumption itself. When this level is reached, the HV current source is activated to lifts VCC up again. At new VCC(on), BO signal is again sensed. If VHV > VBO(on), the parts restarts. If the condition is not met, no drive pulse is delivered and internal IC consumption brings VCC down again. As a result, VCC operates in hiccup mode during a BO event. www.onsemi.com 17 NCP1239 BO_OK = "0" è Drive pulse stops vcc(t) Vcc(on) Vcc(min) Vcc hiccup waiting BO signal Vcc(off) vDRV(t) No pulse area t BO(t) BO_OK = "1" BO_OK = "1" BO_OK = "0" t Figure 35. BO Event during Normal Operation vcc(t) BO no OK è No drive pulse First drive pulse Vcc(on) Vcc(min) Vcc(off) Vcc hiccup waiting BO signal BO_OK = "1" è Wait the next Vcc(on) for fresh start-up sequence Vcc(inhibit) t BO(t) BO_OK = "1" BO_OK = "0" t Figure 36. BO Event before Start-Up www.onsemi.com 18 NCP1239 OVER POWER PROTECTION Over Power Protection (OPP) is a known means to limit the output power runaway at high mains. Several elements such as propagation delays and operating mode explain why a converter operated at high line delivers more power than at low line. NCP1239 senses the input voltage via HV pin. This line voltage is transformed into a current information further applied to the current sense pin (CS). A resistor Vbulk placed in series from the sense resistor to the CS pin will create an offset voltage proportional to the input voltage variation. An added current sink will ensure a zero OPP current at low line (125 V dc), leaving the converter power capability intact in the lowest operating voltage. Figure 37 presents the internal simplified architecture of this OPP circuitry. HV HV detection & sampling N HV sample EMI Filter L1 OPP current generation Vfb Iopp ROPP CS To CS comparator offset Rsense Figure 37. Over Power Protection is Provided via the Bulk Voltage Present on HV Pin The HV voltage will be transformed into a current equal to 67.5 mA when the HV pin is biased to 125 V. However, there is an internal fixed sink of 67.5 mA. Therefore, the net current flowing into ROPP is 0 at this low-voltage input (≤ 125 V dc), ensuring an almost non-compensated converter at low line: at a 115-V rms input (162 V dc), the current from the OTA block will induce a 87.5-mA current, turning into a 20-mA offset current flowing into ROPP. Now, assume a 260-V rms input voltage (365 V dc), the controller will generate an offset current of: 365 @ 0.54 u * 67.5 u + 130 mA 250 m 130 u + 192 kW (eq. 9) A small 100−220-pF capacitor closely connected between the CS and GND pins will form an effective noise filter and nicely improves the converter immunity. Now, with this 1.92-kW resistance, the low-line 20-mA offset current will incur a 38-mV drop, which, in relationship to a 800-mV maximum peak, generates a small 5% reduction. Assuming a full DCM operation, the power would be reduced by 0.952 or 9.75% only. Please note that the OPP current is clamped for a HV pin voltage greater than 365 V dc. Should you lift the pin above this voltage, there will be no increase of the OPP current. The offset voltage can affect the standby power performance by reducing the peak current setpoint in light-load conditions. For this reason, it is desirable to cancel (eq. 8) Assume we need to reduce the maximum peak current setpoint by 250 mV to limit the maximum power at the considered 260-V rms input. In that case, we will need to generate a 250-mV offset across ROPP. With a 130-mA current, ROPP should be equal to: www.onsemi.com 19 NCP1239 its action as soon as frequency folback occurs. A typical curve variation is shown in Figure 38. At low power, below the frequency folback starting point, 100% of the OPP current is internally absorbed and no offset is created through the CS pin. When feedback increases again and reaches the frequency foldback point, as the frequency goes up, OPP starts to build up and reaches its full value at VFOLD + 0.7 V. vFB(t) max Fsw increases Fsw decreases + 0.7 V Vfold t IOPP(%) 100 0 t Figure 38. The OPP Current is Applied when the Feedback Voltage Exceeds the Folback Point. It is 0 below it FAULT INPUT where VZ is the Zener diode Voltage. The NCP1239 includes a dedicated fault input accessible via the fault pin. Figure 39 shows the architecture of the fault input. The controller can be latched by pulling up the pin above the upper fault threshold, VFAULT(OVP), typically 3.0 V. An active clamp prevents the Fault pin voltage from reaching the VFAULT(OVP) if the pin is open. To reach the upper threshold, the external pull-up current has to be higher than the pull-down capability of the clamp. V FAULT(OVP) * V FAULT(clamp) R FAULT(clamp) + 3 V * 1.35 V 1.35 kW , The controller can also be latched off if the fault pin voltage, VFAULT, is pulled below the lower fault threshold, VFAULT(OTP), typically 0.4 V. This capability is normally used for detecting an over-temperature fault by means of an NTC thermistor. A pull up current source IOTP, (typically 45 mA) generates a voltage drop across the thermistor. The resistance of the NTC thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. The controller detects a fault once the thermistor voltage drops below VFAULT(OTP). The circuit detects an over-temperature situation when: (eq. 10) i.e. approximately 1.2 mA This function is typically used to detect a VCC or auxiliary winding over-voltage by means of a Zener diode generally in series with a small resistor (see Figure 39). Neglecting the resistor voltage drop, the OVP threshold is then: V AUX(OVP) + V Z ) V FAULT(OVP) R NTC @ I OTP + V FAULT(OTP) (eq. 12) Hence, the OTP protection trips when R NTC + (eq. 11) www.onsemi.com 20 V FAULT(OTP) I OTP + 8.9 kW (Typically) (eq. 13) NCP1239 The controller bias current is reduced during power up by disabling most of the circuit blocks including IFAULT(OTP). This current source is enabled once VCC reaches VCC(min). A bypass capacitor is usually connected between the Fault and GND pins. It will take some time for VFAULT to reach its steady state value once IOTP is enabled. Therefore, the lower fault comparator (i.e. over-temperature detection) is ignored during soft-start. In addition, in order to speed up this fault pin capacitor, OTP current is doubled during the soft-start period. Vaux 600 ns Time constant 1 ms Blanking Time DRV Falling edge IOTP Fault NTC 4 RST VFault(OVP) Vdd Up counter Latch S Q Q OVP/OTP gone R Rfault(clamp) Vfault(clamp) Power on reset VFault(OTP) Figure 39. Fault Detection Schematic OVP/OTP events occurred for 4 successive drive clock pulses before actually latching the part. When the part is latched-off, the drive is immediately turned off and VCC goes in endless hiccup mode. The power supply needs to be un-plugged to reset the part (VCC(reset) or BO event). Please note that this protection on the Fault pin is autorecovery for the E, K, M, P and Q versions. As a matter of fact, the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. Upper and lower fault detectors have blanking delays to prevent noise from triggering them. Both OVP and OTP comparator output are validated only if its high-state duration lasts a minimum of 600 ns. Below this value, the event is ignored. Then, a counter ensures that AUTO-RECOVERY SHORT-CIRCUIT PROTECTION In case of output short-circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. If the flag is asserted longer than the timer’s programmed value, the driving pulses are stopped and a 1-s auto-recovery timer starts. If VCC voltage is below VCC(min), HV current source is activated to build up the voltage to VCC(on). On the contrary, if VCC voltage is above VCC(min), HV current source is not activated, VCC falls down as the auxiliary pulses are missing and the controller waits that VCC(min) is crossed to enable the stat-up current source. During the timer count down, the controller purposely ignores the re-start when VCC crosses VCC(on) and waits for another VCC cycle. By lowering the duty cycle in fault condition, it naturally reduces the average input power and the rms current in the output cable. Illustration of such principle appears in Figure 40. Please note that soft-start is activated upon re-start attempt. www.onsemi.com 21 NCP1239 vcc(t) Overload on the output voltage Vcc(on) Vcc(min) OCP timer OCP timer Autorecovery timer Autorecovery timer Vcc(off) t vDRV(t) No pulse area t Figure 40. An Auto-Recovery Hiccup Mode is Entered in Case a Faulty Event Longer than 64 ms is Acknowledged by the Controller The hiccup is operating regardless of the brown-out level. However, when the internal comparator toggles indicating that the controller recovers from a brown-out situation (the input line was ok, then too low and back again to normal), the hiccup is interrupted and the controller re-starts to the next available VCC(on). Figure 41 displays the resulting waveform: the controller is protecting the converter against an overload. The mains suddenly went down, and then back again at a normal level. Right at this moment, the hiccup logic receives a reset signal and ignores the next hiccup to immediately initiate a re-start signal. vcc(t) Overload on the output voltage Vcc(on) Vcc(min) OCP timer Autorecovery timer Vcc(off) t vDRV(t) No pulse area t BO(t) BO_OK = "1" BO_OK = "1" BO_OK = "0" Figure 41. BO Event in Auto-Recovery or Latch Mode www.onsemi.com 22 t NCP1239 LATCHED SHORT CIRCUIT PROTECTION WITH PRE-SHORT In some applications, the controller must be fully latched in case of an output short circuit presence. When the error flag is asserted, meaning the controller is asked to deliver its full peak current, upon timer completion, the controller latches off: all pulses are immediately stopped and VCC hiccups between the two levels, VCC(on) and VCC(min). However, in presence of a small VCC capacitor, it can very well be the case where the stored energy does not give enough time to let the timer elapse before VCC touches the VCC(off). When this happens, the latch is not acknowledged since the timer countdown has been prematurely aborted. To avoid this problem, NCP1239 combines the error flag assertion together with the UVLO flag: upon start up, as maximum power is asked to increase VOUT, the error flag is temporarily raised until regulation is met. If during the time the flag is raised an UVLO event is detected, the part latches off immediately. When latched, VCC hiccups between the two levels, VCC(on) and VCC(min) until a reset occurs (Brown-out event or VCC cycled down below VCC(reset)). In normal operation, if a UVLO event is detected for any reason while the error flag is not asserted, the controller will naturally resume operations. Please also note that this pre-short protection is activated only during start-up sequence. In normal operation, even if an UVLO event occurs while the error flag is asserted, the controller will enters in auto-recovery mode. Details of this behavior are given in Figure 42. latched reset vcc(t) Fb OK resumed Vcc(on) Vcc(min) Vcc(off) New sequence vDRV(t) UVLO AND OCP flag at start−up Glitch or overload t t 1 OCP flag 0 t Figure 42. UVLO Event during Start-Up Sequence and in Normal Operation LATCHING OR AUTO-RECOVERY MODE The B, C, D, E, K, L, M, N, P, Q and R versions are auto-recovery. When an overload fault is detected, they stop generating drive pulses and VCC hiccups between VCC(min) and VCC(on) during the auto-recovery timer before initiate a fresh start-up sequence with soft-start. The A, F, G, H, I and J versions latch off when they detect an overload situation. In this condition, the circuit stops generating drive pulses and let VCC drop down. When VCC has reached 10-VCC(min) level, the circuit charged up VCC to VCC(on). The controller enters in an endless hiccup mode. The device cannot recover operation until VCC drops below VCC(reset) or brownout recovery signal is applied. Practically, the power supply must be unplugged to be reset (VCC < VCC(reset)). Please note that the controller always enters in auto-recovery mode when the UVLO event occurs without internal error flag signal (ie: without overload). www.onsemi.com 23 NCP1239 FREQUENCY FOLDBACK 1.5 V, the frequency is fixed and cannot go further down. The peak current setpoint is free to follow the feedback voltage from 3.2 V (full power) down to 1 V. At 1 V, as both frequency and peak current are frozen (250 mV or ≈31% of the maximum 0.8-V setpoint) the only way to further reduce the transmitted power is to enter skip cycle. This is what happens when the feedback voltage drops below 0.8 V typically. Figure 43 depicts the adopted scheme for the part. The reduction of no-load standby power associated with the need for improving the efficiency, requires to change the traditional fixed-frequency type of operation. This controller implements a switching frequency folback when the feedback voltage passes below a certain level, VFOLD, set at 1.9 V. At this point, the oscillator turns into a Voltage-Controlled Oscillator (VCO) and reduces switching frequency down to a feedback voltage of 1.5 V where switching frequency is 26 kHz typically. Below Frequency Peak current setpoint FSW VCS Vfold(end) FB max 65 kHz max 0.8 V [0.47 V min 26 kHz skip 0.8 V 1.5 V Vskip 1.9 V Vfold 3.2 V [0.25 V VFB min 0.8 V 1.0 V Vskip Vfreeze 1.9 V Vfold 3.2 V VFB Figure 43. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an Improved Performance at Light Load SLOPE COMPENSATION Slope compensation is a known means to fight sub-harmonic oscillations in peak-current mode controlled power converters (flyback in our case). By adding an artificial ramp to the current sense information or subtracting it from the feedback voltage, you implement slope compensation. How much compensation do you need? The simplest way is to consider the primary-side inductor downslope and apply 50% of its value for slope compensation. For instance, assume a 65-kHz/19-V output flyback converter whose transformer turns ratio 1:N is 1:0.25. The primary inductor is 600 mH. As such, assuming a 1-V forward drop of the output rectifier, the downslope is evaluated to: S OFF + V OUT ) V f NL p + 19 ) 1 0.25 @ 600 u + If we have a 0.33-W sense resistor, then the current downslope turns into a voltage downslope whose value is simply: S ȀOFF + S OFF @ R SENSE + (eq. 15) + 133 m @ 0.33 [ 44 mVńms 50% of this value is 22 mV/ms. The internal slope compensation level is typically 29 mV/ms (for the 65-kHz version) so it will nicely compensate this design example. What if my converter is under compensated? You can still add compensation ramp via a simple RC arrangement showed in Figure 44. Please look at AND8029 available from www.onsemi.com regarding calculation details of this configuration. (eq. 14) + 133 kAńs or 133 mAńms www.onsemi.com 24 NCP1239 DRV D1 1N4148 R1 C1 R4 CS R3 Rsense Figure 44. An Easy Means to Add Slope Compensation is by Using an Extra RC Network Building a Ramp from the Drive Signal A 2ND OVER-CURRENT COMPARATOR FOR ABNORMAL OVER-CURRENT FAULT DETECTION threshold of the comparator, VILIM2, typically 1.2 V, is set 50 % higher than VLIMIT1, to avoid interference with normal operation. Four consecutive abnormal over-current faults cause the controller to enter latch mode. The count to 4 provides noise immunity during surge testing. The counter is reset each time a DRV pulse occurs without activating the Fault Over-Current Comparator. Please note that abnormal over−current fault is following the timer−based short−circuit protection behavior (auto− recovery or latching off). A severe fault like a winding short-circuit can cause the switch current to increase very rapidly during the on-time. The current sense signal significantly exceeds VILIM1. But, because the current sense signal is blanked by the LEB circuit during the switch turn on, the power switch current can become huge causing system damage. The NCP1239 protects against this fault by adding an additional comparator for abnormal over-current fault detection. The current sense signal is blanked with a shorter LEB duration, tLEB2, typically 120 ns, before applying it to the abnormal over-current fault comparator. The voltage OVER-VOLTAGE PROTECTION ON VCC PIN VCC pin can be auto-recovery or latched. For latching-off versions, the part can be reset by cycling down its VCC, for instance by pulling off the power plug but also if a brown-out recovery is sensed by the controller. This technique offers a simple and cheap means to protect the converter against optocoupler. The NCP1239 hosts a dedicated comparator on the VCC pin. When the voltage on this pin exceeds 25.5 V typically (32.0 V for F, J, M and N versions) for more than 20 ms, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. Depending controller options, this OVP on PROTECTING FROM A FAILURE OF THE CURRENT SENSING voltage is low or if the CS pin is grounded. In this case, the OCP timer is activated. If the timer elapses, the controller enters in auto-recovery or endless hiccup mode depending on the controller option. This unexpected operation can lead to deep CCM with destructive consequences. A 1-mA (typically) pull-up current source, ICS, pulls up the CS pin to disable the controller if the pin is left open. In addition the maximum duty ratio limit (80% typically) avoids that the MOSFET stays permanently on if the switch current cannot reach the setpoint when for instance, the input www.onsemi.com 25 NCP1239 SOFT-START gradual increase of the power switch current during start-up. The soft-start duration (that is, the time necessary for the ramp to reach the VILIM1 steady state current limit), tSSTART, is typically 8 ms. Soft-start is achieved by ramping up an internal reference, VSSTART, and comparing it to current sense signal. VSSTART ramps up from 0 V once the controller powers up. The setpoint rise is then limited by the VSSTART ramp so that a DRIVER The NCP1239 maximum supply voltage, VCC(max), is 25.5 V (32.0 V for F and J versions). Typical high-voltage MOSFETs have a maximum gate-source voltage rating of 20 V. The DRV pin incorporates an active voltage clamp to limit the gate voltage on the external MOSFETs. The DRV voltage clamp, VDRV(high) is typically 13.5 V with a maximum limit of 16 V. THERMAL SHUTDOWN temperature drops below below TSHDN by the thermal shutdown hysteresis, TSHDN(HYS), typically 20_C. The thermal shutdown is also cleared if VCC drops below VCC(reset) or a brown-out fault is detected. A new power up sequences commences at the next VCC(on) once all the faults are removed. An internal thermal shutdown circuit monitors the junction temperature of the IC. The controller is disabled if the junction temperature exceeds the thermal shutdown threshold, TSHDN, typically 150_C. A continuous VCC hiccup is initiated after a thermal shutdown fault is detected. The controller restarts at the next VCC(on) once the IC Table 5. ORDERING INFORMATION OCP Protection VCC OVP Protection Fault Pin Protection BO Levels 65 kHz Latch Latch Latch 110/101 65 kHz Auto-Recovery Latch Latch 110/101 1239C065 65 kHz Auto-Recovery Auto-Recovery Latch 110/101 NCP1239DD65R2G 1239D065 65 kHz Auto-Recovery Latch Latch 101/95 NCP1239ED65R2G 1239E065 65 kHz Auto-Recovery Auto-Recovery Auto-Recovery 110/101 NCP1239FD65R2G 1239F065 65 kHz Latch Latch Latch 229/176 NCP1239HD65R2G 1239H065 65 kHz Latch Latch Latch 229/224 NCP1239ID65R2G 1239I065 65 kHz Latch Latch Latch 101/95 NCP1239JD65R2G 1239J065 65 kHz Latch Latch Latch 101/95 NCP1239KD65R2G 1239K065 65 kHz Auto-Recovery Auto-Recovery Auto-Recovery 110/101 NCP1239LD65R2G 1239L065 65 kHz Auto-Recovery Latch Latch 82/77 NCP1239MD65R2G 1239M065 65 kHz Auto-Recovery Auto-Recovery Auto-Recovery 229/224 NCP1239ND65R2G 1239N065 65 kHz Auto-Recovery Auto-Recovery Latch 229/224 NCP1239PD65R2G 1239P065 65 kHz Auto-Recovery Auto-Recovery Auto-Recovery 82/79 NCP1239QD65R2G 1239Q065 65 kHz Auto-Recovery Auto-Recovery Auto-Recovery 82/79 NCP1239RD65R2G 1239R065 65 kHz Auto-Recovery Latch Latch 101/95 NCP1239AD100R2G 1239A100 100 kHz Latch Latch Latch 110/101 NCP1239BD100R2G 1239B100 100 kHz Auto-Recovery Latch Latch 110/101 NCP1239DD100R2G 1239D100 100 kHz Auto-Recovery Latch Latch 110/95 NCP1239ED100R2G 1239E100 100 kHz Auto-Recovery Auto-Recovery Auto-Recovery 110/101 NCP1239GD100R2G 1239G100 100 kHz Latch Latch Latch 95/86 NCP1239LD100R2G 1239L100 100 kHz Auto-Recovery Latch Latch 82/77 Device Marking Freq. NCP1239AD65R2G 1239A065 NCP1239BD65R2G 1239B065 NCP1239CD65R2G Package Shipping† SOIC−7 (Pb-Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. www.onsemi.com 26 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U ISSUE E SCALE 1:1 DATE 20 OCT 2009 −A− 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B ARE DATUMS AND T IS A DATUM SURFACE. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5 −B− S 0.25 (0.010) B M M 1 4 G C R X 45 _ J −T− SEATING PLANE H 0.25 (0.010) K M D 7 PL M T B S A DIM A B C D G H J K M N S INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 S GENERIC MARKING DIAGRAM SOLDERING FOOTPRINT* 8 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 1 XXX A L Y W G 4.0 0.155 0.6 0.024 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 XXXXX ALYWX G mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the onsemi Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98AON12199D SOIC−7 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2023 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−7 CASE 751U ISSUE E STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. 7. NOT USED 8. EMITTER DATE 20 OCT 2009 STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. NOT USED 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. NOT USED 8. SOURCE, #1 STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. 6. 7. NOT USED 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. 7. NOT USED 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. NOT USED 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR (DIE 1) 2. BASE (DIE 1) 3. BASE (DIE 2) 4. COLLECTOR (DIE 2) 5. COLLECTOR (DIE 2) 6. EMITTER (DIE 2) 7. NOT USED 8. COLLECTOR (DIE 1) STYLE 9: PIN 1. EMITTER (COMMON) 2. COLLECTOR (DIE 1) 3. COLLECTOR (DIE 2) 4. EMITTER (COMMON) 5. EMITTER (COMMON) 6. BASE (DIE 2) 7. NOT USED 8. EMITTER (COMMON) STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. NOT USED 8. GROUND STYLE 11: PIN 1. SOURCE (DIE 1) 2. GATE (DIE 1) 3. SOURCE (DIE 2) 4. GATE (DIE 2) 5. DRAIN (DIE 2) 6. DRAIN (DIE 2) 7. NOT USED 8. DRAIN (DIE 1) STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. NOT USED 8. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98AON12199D SOIC−7 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2023 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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