NCP1351BDR2G

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Based on a fixed peak current technique (quasi-fixed TON), the controller decreases its switching frequency as the load becomes lighter. As a result, a power supply using the NCP1351 naturally offers excellent no-load power consumption, while optimizing the efficiency in other loading conditions. When the frequency decreases, the peak current is gradually reduced down to approximately 30% of the maximum peak current to prevent transformer mechanical resonance. The risk of acoustic noise is thus greatly diminished while keeping good standby power performance. An externally adjustable timer permanently monitors the feedback activity and protects the supply in presence of a short-circuit or an overload. Once the timer elapses, NCP1351 stops switching and stays latched for version A, and tries to restart for version B. Versions C and D include a dual overcurrent protection trip point, allowing the implementation of the controller in peak-power requirements applications such as printers and so on. When the fault is acknowledged, C version latches-off whereas D version auto-recovers. The internal structure features an optimized arrangement which allows one of the lowest available startup current, a fundamental parameter when designing low standby power supplies. The negative current sensing technique minimizes the impact of the switching noise on the controller operation and offers the user to select the maximum peak voltage across his current sense resistor. Its power dissipation can thus be application optimized. Finally, the bulk input ripple ensures a natural frequency smearing which smooths the EMI signature. http://onsemi.com MARKING DIAGRAMS 8 SOIC-8 D SUFFIX CASE 751 8 1 1 1 1 x A L, WL Y, YY W, WW G or G • • PIN CONNECTIONS November, 2007 - Rev. 3 FB 1 8 TIMER Ct 2 7 LATCH CS 3 6 VCC GND 4 5 DRV (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. Typical Applications • Auxiliary Power Supply • Printer, Game Stations, Low-Cost Adapters • Off-line Battery Charger Auto-Recovery, A & B Versions Dual Trip Point Overcurrent Protection, Latched or Auto-Recovery, C & D Versions These are Pb-Free Devices © Semiconductor Components Industries, LLC, 2007 = A, B, C, or D Options = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) Features •Quasi-fixed TON, Variable TOFF Current Mode Control •Extremely Low Current Consumption at Startup •Peak Current Compression Reduces Transformer Noise •Primary or Secondary Side Regulation •Dedicated Latch Input for OTP, OVP •Programmable Current Sense Resistor Peak Voltage •Natural Frequency Dithering for Improved EMI Signature •Easy External Over Power Protection (OPP) •Undervoltage Lockout •Very Low Standby Power via Off-time Expansion •SOIC-8 Package • Standard Overcurrent Protection, Latched or NCP1351x AWL YYWWG PDIP-8 P SUFFIX CASE 626 8 1351x ALYW G 1 Publication Order Number: NCP1351/D NCP1351 VOUT + NCP1351 LATCH + 85-265VAC *OPP 1 8 2 7 3 6 4 5 + GND *Optional Figure 1. Typical Application Circuit PIN FUNCTION DESCRIPTION Pin N° Pin Name Function Pin Description 1 FB Feedback Input Injecting Current in this Pin Reduces Frequency 2 Ct Oscillator Frequency A capacitor sets the maximum switching frequency at no feedback current 3 CS Current Sense Input Senses the Primary Current 4 GND – – 5 DRV Driver Output Driving Pulses to the Power MOSFET 6 VCC Supply Input Supplies the controller up to 28 V 7 Latch Latchoff Input A positive voltage above VLATCH fully latches off the controller 8 Timer Fault Timer Capacitor Sets the time duration before fault validation OVERCURRENT PROTECTION ON NCP1351 VERSIONS: NCP1351 Auto-recovery Latched A B x x C D Dual level x x x x http://onsemi.com 2 NCP1351 INTERNAL CIRCUIT ARCHITECTURE VDD 20 s Filter + VDD + VTIMER ITIMER FB TIMER UVLO Reset Fault = Low 40  + + - IP Flag VFault 20 s Filter VDD + ICt Ct LATCH + S VLATCH Q Q 45k R 4V Reset 1 s Pulse + VDD VCC Mngt VZENER VCCSTOP 1 = OK 0 = not OK VDD VOFFset UVLO Reset VCC Clamp + - ICS-dif* S ICS-dif* Q DRV Q CS ICS-min* R GND + Vth + *(ICS-diff = ICS-max -ICS-min) Figure 2. A Version (Latched Short-Circuit Protection) http://onsemi.com 3 NCP1351 VDD + VDD + S Q VITIMER ITIMER FB Q TIMER UVLO Reset Fault = Low R 40  + + - IP Flag VFault 20 s Filter VDD + ICt Ct LATCH + S VLATCH Q Q 45k R 4V Reset 1 s Pulse + VDD VCC Mngt VZENER VCCSTOP 1 = OK 0 = not OK VDD VOFFset UVLO Reset VCC Clamp + - ICS-dif* S ICS-dif* Q DRV Q CS ICS-min* R GND + Vth + *(ICS-diff = ICS-max -ICS-min) Figure 3. B Version (Auto-recovery Short-Circuit Protection) http://onsemi.com 4 NCP1351 VDD 20 s Filter + VDD + VTIMER ITIMER FB TIMER UVLO Reset Fault = Low 40  + + - D Q IP Flag VFault CLK VDD 20 s Filter + ICt Ct LATCH + S VLATCH Q Q 45k R 4V Reset 1 s Pulse + VDD VCC Mngt VZENER VCCSTOP 1 = OK 0 = not OK VDD VOFFset UVLO Reset VCC Clamp + - ICS-dif* S ICS-dif* Q DRV Q CS ICS-min* R GND + Vth + *(ICS-diff = ICS-max -ICS-min) Figure 4. C Version (Latched Short-Circuit Protection) http://onsemi.com 5 NCP1351 VDD + VDD + S Q VITIMER ITIMER FB Q TIMER UVLO Reset Fault = Low R 40  + + - D Q IP Flag VFault VDD 20 s Filter CLK + ICt Ct LATCH + S VLATCH Q Q 45k R 4V Reset 1 s Pulse + VDD VCC Mngt VZENER VCCSTOP 1 = OK 0 = not OK VDD VOFFset UVLO Reset VCC Clamp + - ICS-dif* S ICS-dif* Q DRV Q CS ICS-min* R GND + Vth + *(ICS-diff = ICS-max -ICS-min) Figure 5. D Version (Auto-recovery Short-Circuit Protection) http://onsemi.com 6 NCP1351 MAXIMUM RATINGS Value Unit VSUPPLY Symbol Maximum Supply on VCC Pin 6 Rating -0.3 to 28 V ISUPPLY Maximum Current in VCC Pin 6 20 mA VDRV Maximum Voltage on DRV Pin 5 -0.3 to 20 V IDRV Maximum Current in DRV Pin 5 $400 mA VMAX Supply Voltage on all pins, except Pin 6 (VCC), Pin 5 (DRV) -0.3 to 10 V IMAX Maximum Current in all Pins Except Pin 6 (VCC) and Pin 5 (DRV) $10 mA IFBmax Maximum Injected Current in Pin 1 (FB) 0.5 mA RGmin Minimum Resistive Load on DRV Pin 33 k RJA Thermal Resistance Junction-to-Air 142 176 °C/W 150 °C -60 to +150 °C 2 kV 200 V TJMAX PDIP-8 SOIC-8 Maximum Junction Temperature Storage Temperature Range ESD Capability, Human Body Model V per Mil-STD-883, Method 3015 ESD Capability, Machine Model Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78. http://onsemi.com 7 NCP1351 Electrical Characteristics (For typical values TJ = 25°C, for Min/Max Values TJ = -25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit VCC Increasing Level at Which Driving Pulses are Authorized 6 15 18 22 V VCCSTOP VCC Decreasing Level at Which Driving Pulses are Stopped 6 8.3 8.9 9.5 V VCCHYST Hysteresis VCCON - VCCSTOP 6 6 - - V Clamped VCC When Latched Off 6 - 6 - V ICC1 Startup Current 6 - - 10 A ICC2 Internal IC Consumption with IFB = 50 A, FSW = 65 kHz and CL = 0 6 - 1.0 1.8 mA ICC3 Internal IC Consumption with IFB = 50 A, FSW = 65 kHz and CL = 1 nF 6 - 1.6 2.5 mA ICC4 Internal IC Consumption in Auto-Recovery Latch-off Phase 6 - 600 - A Current Flowing into VCC pin that Keeps the Controller Latched 6 20 - - A SUPPLY SECTION AND VCC MANAGEMENT VCCON VZENER ICCLATCH CURRENT SENSE ICSmin Minimum Source Current (IFB = 90 A) TJ = 0°C to +125°C 3 61 70 75 A ICSmin Minimum Source Current (IFB = 90 A) TJ = -25°C to +125°C 3 58 70 75 A ICSmax Maximum Source Current (IFB = 50 A) TJ = 0°C to +125°C 3 251 270 289 A ICSmax Maximum Source Current (IFB = 50 A) TJ = -25°C to +125°C 3 242 270 289 A VTH Current Sense Comparator Threshold Voltage 3 10 20 35 mV tdelay Propagation Time Delay (CS Falling Edge to Gate Output) 3 - 160 300 ns TIMING CAPACITOR VOFFSET Minimum Voltage on CT Capacitor, IFB = 30 A 2 475 510 565 mV VCTMAX Voltage on CT Capacitor at IFB = 150 A 2 5 - - V 2 9.8 9.3 10.8 10.8 11.8 11.9 A - - 20 mV ICT Source Current (Ct Pin Grounded) TJ = 25°C TJ = -25°C to +125°C VCTMIN Minimum Voltage on CT, Discharge Switch Activated 2 TDISCH CT Capacitor Discharge Time (Activated at DRV Turn-on) 2 VFAULT CT Capacitor Level at Which Fault Timer Starts A and B Versions C and D Version 2 0.4 - 0.5 0.96 0.6 - KFAULT Factor Linking VOFFSET and VFAULT (Note 1) C and D Version - 1.67 1.86 2.05 1 - 0.7 - V 1 - 40 51 - A s 1 V FEEDBACK SECTION VFB FB Pin Voltage for an Injected Current of 200 A IFAULT FB Current Under Which a Fault is Detected IFBcomp FB Current at Which CS Compression Starts 1 - 60 - A FB Current at Which CS Compression is Finished 1 - 80 - A IFBred A and B Versions C and D Versions DRIVE OUTPUT Tr Output Voltage Rise-time @ CL = 1 nF, 10 - 90% of Output Signal 5 - 90 - ns Tf Output Voltage Fall-time @ CL = 1 nF, 10 - 90% of Output Signal 5 - 100 - ns ROH Source Resistance 5 - 80 -  ROL Sink Resistance 5 - 30 -  VDRVlow DRV Pin Level at VCC Close to VCCSTOP with a 33 k Resistor to GND 5 8.0 - - V VDRVhigh DRV Pin Level at VCC = 28 V with 33 k Resistor to GND 5 15 17 20 V Protection ITIMER Timing Capacitor Charging Current 8 10 11.5 13 A VTIMER Fault Voltage on Pin 8 8 4.5 5 5.5 V TTIMER Fault Timer Duration, CTIMER = 100 nF - - 42 - ms VLATCH Latching Voltage 7 4.5 5 5.5 V 1. Guaranteed by design. http://onsemi.com 8 NCP1351 • Extended VCC Range: By accepting VCC levels up to The NCP1351 implements a fixed peak current mode technique whose regulation scheme implements a variable switching frequency. As shown on the typical application diagram, the controller is designed to operate with a minimum number of external components. It incorporates the following features: • Frequency Foldback: Since the switching period increases when power demand decreases, the switching frequency naturally diminishes in light load conditions. This helps to minimize switching losses and offers good standby power performance. • Very Low Startup Current: The patented internal supply block is specially designed to offer a very low current consumption during startup. It allows the use of a very high value external startup resistor, greatly reducing dissipation, improving efficiency and minimizing standby power consumption. • Natural Frequency Dithering: The quasi-fixed tON mode of operation improves the EMI signature since the switching frequency varies with the natural bulk ripple voltage. • Peak Current Compression: As the load becomes lighter, the frequency decreases and can enter the audible range. To avoid exciting transformer mechanical resonances, hence generating acoustic noise, the NCP1351 includes a patented technique, which reduces the peak current as power goes down. As such, inexpensive transformer can be used without having noise problems. • Negative Primary Current Sensing: By sensing the total current, this technique does not modify the MOSFET driving voltage (VGS) while switching. Furthermore, the programming resistor, together with the pin capacitance, forms a residual noise filter which blanks spurious spikes. • Programmable Primary Current Sense: It offers a second peak current adjustment variable, which improves the design flexibility. • • • • • 28 V, the device offers added flexibility in presence of loosely coupled transformers. The gate drive is safely clamped below 20 V to avoid stressing the driven MOSFET. Easy OPP: Connecting a resistor from the CS pin to the auxiliary winding allows easy bulk voltage compensation. Secondary or Primary Regulation: The feedback loop arrangement allows simple secondary or primary side regulation without significant additional external components. Latch Input: If voltage on Pin 7 is externally brought above 5 V, the controller permanently latches off and stays latched until the user cycles VCC down, below 4 V typically. Fault Timer: In presence of badly coupled transformer, it can be quite difficult to detect an overload or a short-circuit on the primary side. When the feedback current disappears, a current source charges a capacitor connected to Pin 8. When the voltage on this pin reaches a certain level, all pulses are shut off and the VCC voltage is pulled down below the VCC(min) level. This protection is latched on the A version (the controller must be shut down and restart to resume normal operation), and auto-recovery on Version B (if the fault goes away, the controller automatically resumes operation). Dual Trip Point: in some applications, such as printer power supplies, it is necessary to let the power supply deliver more power on a transient event. If the event lasts longer than what the fault timer authorizes, then the NCP1351 either latches-off (C Version) or enters an auto-recovery mode (D Version). The level at which the timer starts is internally set to 55% of the maximum power capability. http://onsemi.com 9 NCP1351 APPLICATION INFORMATION The Negative Sensing Technique current increases. When the result reaches the threshold voltage (around 20 mV), the comparator toggles and resets the main latch. Figure 3 details how the voltage moves on the CS pin on a 1351 demoboard, whereas Figure 9 zooms on the sense resistor voltage captured by respect to the controller ground. The choice of these two elements is simple. Suppose you want to develop 1 V across the sense resistor. You would select the offset resistor via the following formula: Standard current-mode controllers use the positive sensing technique as portrayed by Figure 6. In this technique, the controller detects a positive voltage drop across the sense resistor, representative of the flowing current. Unfortunately, this solution suffers from the following drawbacks: 1. Difficulties to precisely adjust the peak current. If 1 V is the maximum sense level, you must combine low valued resistors to reach the exact limit you need. 2. The voltage developed across the sense resistor subtracts from the gate voltage. If your VCC(min) is 7 V, then the actual gate voltage at the end of the on time, assuming a full load condition, is 7 V – 1 V = 6 V. 3. The current in the sense resistor also includes the Ciss current at turn-on. This narrow spike often disturbs the controller and requires adequate treatment through a LEB circuitry for instance. Figure 7 represents the negative current sense technique. In this simplified example, the source directly connects to the controller ground. Hence, if VCC is 8 V, the effective gate-source voltage is very close to 8 V: no sense resistor drop. How does the controller detect a negative excursion? In lack of primary current, the voltage on the CS pin reaches Roffset x ICS. Let us assume that these elements lead to have 1 V on this pin. Now, when the power MOSFET activates, the current flows via the sense resistor and develop a negative voltage by respect to the controller ground. The voltage seen on the CS is nothing else than a positive voltage (Roffset x ICS) plus the voltage across the sense resistor which is negative. Thus, the CS pin voltage goes low as the primary ILp Roffset + 1 1 + + 3.7k 270 ICS (eq. 1) If you need a peak current of 2 A, then, simply apply the ohm law to obtain the sense resistor value: Rsense + 1 Ipeak_max + 1 + 0.5 2 (eq. 2) Due to the circuit flexibility, suppose you only have access to a 0.33  resistor. In that case, the peak current will exceed the 2 A limit. Why not changing the offset resistor value then? To obtain 2 A from the 0.33  resistor, you should develop: The offset resistor is thus derived by: Vsense + RsenseIpeak_max + 0.33 2 + 660mV (eq. 3) Roffset + 0.66 + ICS 0.66 + 2.44k 270 (eq. 4) If reducing the sense resistor is of good practice to improve the efficiency, we recommend to adopt sense values between 0.5 V and 1 V. Reducing the voltage below these levels will degrade the noise immunity. LP LP DRV DRV VDD + + Vgs CBulk CS ILp Reset CBulk ILp - + - ILp ICS CS ILp Peak Setpoint Rsense Voffset Vsense Reset GND ILp + Roffset + Vth GND ILp Vsense Figure 6. Positive Current-Sense Technique Figure 7. A Simplified Circuit of the Negative Sense Implementation http://onsemi.com 10 NCP1351 Current Sense Resistor Current Sense Pin Figure 8. The Voltage on the Current Sense Pin Figure 9. The Voltage Across the Sense Resistor in this NCP1351 for simplicity and ease of implementation. Thus, once the peak current has been selected, the feedback loop automatically reacts to satisfy Equations 5 and 6. The external capacitor that you connect between pin 2 and ground (again, place it close to the controller pins) sets the maximum frequency you authorize the converter to operate up to. Normalized values for this timing capacitor are 270 pF (65 kHz) and 180 pF (100 kHz). Of course, different combinations can be tried to design at higher or lower frequencies. Please note that changing the capacitor value does not affect the operating frequency at nominal line and load conditions. Again, the operating frequency is selected by the feedback loop to cope with Equations 5 and 6 definitions. The feedback current controls the frequency by changing the timing capacitor end of charge voltage, as illustrated by Figure 10. The timing capacitor ending voltage can be precisely computed using the following formula: Below are a few recommendations concerning the wiring and the PCB layout: • A small 22 pF capacitor can be placed between the CS pin and the controller ground. Place it as close as possible to the controller. • Do not place the offset resistor in the vicinity of the sense element, but put it close to the controller as well. • Regulation by frequency • The power a flyback converter can deliver relates to the energy stored in the primary inductance Lp and obeys the following formulae: 1 Pout_DCM +  LPIpeak2FSW 2 Pout_CCM + 12LP(Ipeak2 * Ivalley2)FSW (eq. 5) (eq. 6) Where:  (eta) is the converter efficiency Ipeak is the peak inductor current reached at the on time termination Ivalley represents the current at the end of the off time. It equals zero in DCM. FSW is the operating frequency. Thus, to control the delivered power, we can either play on the peak current setpoint (classical peak current mode control) or adjust the switching frequency by keeping the peak current constant. We have chosen the second scheme V C + 45k(I FB * 40u) ) 500m t (eq. 7) Where IFB represents the injected current inside the FB pin (pin 1). The 40u term corresponds to a 40  offset current purposely placed to force a minimum current injection when the loop is closed. This allows the controller to detect a short-circuit condition as the feedback current drops to zero in that condition. http://onsemi.com 11 NCP1351 VCt Controlled by the FB Current Minimum Frequency ICt = 10 A Pout Decreases Pout Increases Maximum Frequency Figure 10. The Current Injected into the Feedback Loop Adjusts the Switching Frequency Ct Voltage Ct Voltage Figure 11. In Light Load Conditions, the Oscillator Further Delays the Restart Time Figure 12. Ct Voltage Swing at a Moderate Loading In light load conditions, the frequency can go down to a few hundred Hz without any problem. The internal circuitry naturally blocks the oscillator and softly shifts the restart time as shown on Figure 11 scope shot. power supply can deliver at low line. This discrepancy relates to the propagation delay from the point where the peak is detected to the MOSFET gate effective pulldown. It naturally includes the controller reaction time, but also the driver capability to pull the gate down. If the MOSFET Qg is too large, then this parameter will greatly affect your overpower parameter. Sometimes, the small PNP can help and we recommend it if you use a large Qg MOSFET: Delays The Restart Time In lack of feedback current, for instance during a startup sequence or a short circuit, the oscillator frequency is pushed to the limit set by the timing capacitor. In this case, the lower threshold imposed to the timing capacitor is blocked to 500 mV (parameter Vfault). This is the maximum power the converter can deliver. To the opposite, as you inject current via the optocoupler in the feedback pin, the off time expands and the power delivery reduces. The maximum threshold level in standby conditions is set to 6 V. D1 1N4148 DRV Q1 2N2907 GND Over Power Protection As any universal-mains operated converters, the output power slightly increases at high line compared to what the Figure 13. A Low-Cost PNP Improves the Drive Capability at Turn-off http://onsemi.com 12 NCP1351 Over power protection can be done without power dissipation penalty by arranging components around the auxiliary as suggested by Figure 14. On this schematic, the diode anode swings negative during the on time. This negative level directly depends on the input voltage and offsets the current sense pin via the ROPP resistor. A small integration is necessary to reduce the OPP action in light load conditions. However, depending on the compensation level, the standby power can be affected. Again, the resistor ROPP should be placed as close as possible to the CS pin. The 22 pF can help to circumvent any picked-up noise and D2 prevents the positive loading of the 270 pF capacitor during the flyback swing. We have put a typical 100 k OPP resistor but a tweak is required depending on your application. LP DRV DRV + CS Daux VCC CBulk C4 22p ILp + CVCC Roffset Laux D2 1N4148 Rsense R1 150k C3 270p ROPP 100k Figure 14. The OPP is Relatively Easy to Implement and It Does not Waste Power Suppose you would need to reduce the peak current by 15% in high-line conditions. The turn-ratio between the auxiliary winding and the primary winding is Naux. Assume its value is 0.15. Thus, the voltage on Daux cathode swings negative during the on time to a level of: Vaux_peak + -Vin_maxNaux + -375 Typically, we measured around –4 V on our 50 W prototype. By calculation, we want to decrease the peak current by 15%. Compared to the internal 270 A source, we need to derive: Ioffset + -0.15 0.15 + -56V (eq. 8) 270 + 1V ROPP + (eq. 9) VC3 + R1C3 +- 3 150k 56 270p + -4.2V 4 + 98k 40.5 (eq. 12) After experimental measurements, the resistor was normalized down to 100 k. The small RC network made of R1 and C3, purposely limits the voltage excursion on D2 anode. Assume the primary inductance value gives an on time of 3 s at high-line. The voltage across C3 thus swings down to: tonVaux_peak (eq. 11) Thus, from the –4 V excursion, the ROPP resistor is derived by: If we selected a 3.7 k resistor for Roffset, then the maximum sense voltage being developed is: Vsense + 3.7k 270 + -40.5A Feedback Unlike other controllers, the feedback in the NCP1351 works in current rather than voltage. Figure 15 details the internal circuitry of this particular section. The optocoupler injects a current into the FB pin in relationship with the input/output conditions. (eq. 10) http://onsemi.com 13 NCP1351 VCC ICt 10 Ct Ct 270p VCC Reset FB IFB Voffset 500mV IFB - Clock + + C1 100n IFB DFB R1 2.5k RFB 45k VCC C3 22pF ICSmin Idiff Idiff CS Idiff = ICSmax - ICSmin f(IFB) Roffset 3.9k to Rsense Figure 15. The Feedback Section Inside the NCP1351 load conditions, the feedback current is weak and all the current flowing through the external offset resistor is: The FB pin can actually be seen as a diode, forward biased by the optocoupler current. The feedback current, IFB on Figure 15, enter an internal 45 k resistor which develops a voltage. This voltage becomes the variable threshold point for the capacitor charge, as indicated by Figure 10. Thus, in lack of feedback current (start-up or short-circuit), there is no voltage across the 45 k and the series offset of 500 mV clamps the capacitor swing. If a 270 pF capacitor is used, the maximum switching frequency is 65 kHz. Folding the frequency back at a rather high peak current can obviously generate audible noise. For this reason, the NCP1351 uses a patented current compression technique which reduces the peak current in lighter load conditions. By design, the peak current changes from 100% of its full load value, to 30% of this value in light load conditions. This is the block placed on the lower left corner of Figure 15. In full ICS + ICS_min ) Idif + ICS_max * ICS_min ) ICS_min + ICS_max (eq. 13) As the load goes lighter, the feedback current increases and starts to steal current away from the generators. Equation 12 can thus be updated by: ICS + ICS_max * kIFB (eq. 14) Equation 13 testifies for the current reduction on the offset generator, k represents an internal coefficient. When the feedback current equals Idif, the offset becomes: ICS + ICS_min http://onsemi.com 14 (eq. 15) NCP1351 Fault detection At this point, the current is fully compressed and remains frozen. To further decrease the transmitted power, the frequency does not have other choice than going down. The fault detection circuitry permanently observes the FB current, as shown on Figure 19. When the feedback current decreases below 40 A, an external capacitor is charged by a 11.7 A source. As the voltage rises, a comparator detects when it reaches 5 V typical. Upon detection, there can be two different scenarios: 1. A version: the circuit immediately latches-off and remains latched until the voltage on the current into the VCC pin drops below a few A. The latch is made via an internal SCR circuit who holds VCC to around 6 V when fired. As long as the current flowing through this latch is above a few A, the circuit remains locked-out. When the user unplugs the converter, the VCC current falls down and resets the latch. 2. B version: the circuit stops its output pulses and the auxiliary VCC decreases via the controller own consumption (≈600 A). When it touches the VCC(min) point, the circuit re-starts and attempts to crank the power supply. If it fails again, an hiccup mode takes place (Figure 18). 3. C version: this version includes the dual Over Current Protection (OCP) level. When the switching frequency imposed by the feedback loop reaches around 50% of the maximum value set by the Ct capacitor, the timer starts to count down. If the fault disappears, the timer is reset. When the fault is finally confirmed, the controller latches off as the A version. 4. D version: this version includes the dual Over Current Protection (OCP) level. When the switching frequency imposed by the feedback loop reaches around 50% of the maximum value set by the Ct capacitor, the timer starts to count down. If the fault disappears, the timer is reset. When the fault is finally confirmed, the controller enters auto-recovery mode, as with the B version. CS Current 270 A 70 A FAULT (A, B versions) 40 A 60 A 80 A FB Current Figure 16. The NCP1351 Peak Current Compression Scheme Looking to the data-sheet specifications, the maximum peak current is set to 270 A whereas the compressed current goes down to 70 A. The NCP1351 can thus be considered as a multi operating mode circuit: • Real fixed peak current / variable frequency mode for FB current below 60 A. • Then maximum peak current decreases to ICS,min over a narrow linear range of IFB (to avoid instability created by a discrete jump from ICS,max to ICS,min), between 60 A and 80 A. • Then if IFB keeps on increasing, in a real fixed peak current/variable frequency mode with reduced peak current For biasing purposes and noise immunity improvements, we recommend to wire a pulldown resistor and a capacitor in parallel from the FB pin to the controller ground (Figure 17). Please keep these elements as close as possible to the circuit. The pulldown resistor increases the optocoupler current but also plays a role in standby. We found that a 2.5 k resistor was giving a good tradeoff between optocoupler operating current (internal pole position) and standby power. VCC VCC Vdrv FB R1 2.5k C1 100nF Figure 18. Hiccup Occurs with the B Version Only, the A Version Being Latched The duty-burst in fault is around 7% in this particular case. Figure 17. The Recommended Feedback Arrangement Around the FB Pin http://onsemi.com 15 NCP1351 VCC Itimer 10 Timer Ctimer 100nF + VCC R1 2.5k C1 100n 20s Filter + - Pon Reset IFB DFB CVCC + ICC Laux S Vtimer 5 FB Daux VCC Q Q to DRV Stage R IFB IFB + + IFB < 40 A ? = Low Else = High VCC == VCC(min) ? Reset DRV Pulses Auto-Recovery - B Version VCC Itimer 10 20s Filter Timer Ctimer 100nF + - + CVCC ICC + Laux 6V Vtimer 5 VCC Pon Reset FB C1 100n Daux VCC R1 2.5k IFB DFB IFB IFB + + SCR Delatches When ISCR < ICClatch (Few A) IFB < 40 A ? = Low Else = High Latched - A Version Figure 19. The Internal Fault Management Differs Depending on the Considered Version designer select a 100 kHz maximum switching frequency, then the error flag would raise and start the timer for an operating frequency above ≈ 50 kHz. Below 50 kHz, the timer pin remains grounded. If we consider a DCM operation at full load, as the inductor peak current is kept constant, these 50 kHz correspond to 50% of the maximum delivered power. If the load stays between 50% and 100% of its nominal value, the timer continues to charge until it reaches the final level. In that case, the circuit latches off (C) or enters auto-recovery (D). This behavior is particularly well suited for applications where the converter delivers a moderate average power but is subjected to sudden peak loading conditions. For instance, a power supply is designed to permanently deliver 20 W but is sized to deliver 80 W in peak conditions. During these 80 W power excursions, the timer will react but will not shut down the power supply. On the contrary, if a short-circuit appends or if the transient overload lasts too long, the timer will immediately start to further shutdown the controller in order to protect both the application and downstream load. Knowing both the ending voltage and the charge current, we can easily calculate the timer capacitor value for a given delay. Suppose we need 40 ms. In that case, the capacitor is simply: 11.7 40m I T Ctimer + timer + + 94nF 5 Vtimer (eq. 16) Select a 100 nF value. To let the designer understand the behavior behind the four different options (A, B, C and D), we have graphed important signals during a fault condition. In versions A and B, an internal error flag is raised as soon the controller hits the maximum operating frequency. At this moment, the external timer capacitor charge begins. If the fault persists, the timer capacitor hits the fault level and the circuit is either latched (A) or enters auto-recovery burst mode (B). If the fault disappears, the timer capacitor is simply reset to 0 V by an internal switch. On version C and D, the error flag is asserted as soon as the current feedback imposes a switching frequency roughly equal to half of the maximum limit. For instance, should the http://onsemi.com 16 NCP1351 The figures below details circuits operation for the various controller options. Depending on the design conditions (DCM or CCM), the error flag assertion will correspond to either 50% of the maximum power (full load DCM design) or a value above this number if the converter operates in CCM at full load and remains in CCM at half the switching frequency. Vcc VccON Pulldown SCR action ICC1 IFB ICC1 Vzener ICC < 20 μA fault FB reacts Vccstop Latched state User reset ok ok 40 μA Vtimer Vtimer startup DRV A version, latched Figure 20. The A Version Latches-off in Presence of a Fault Vcc Vcc ON Pulses stopped Vcc stop Fault still present ICC4 ICC1 IFB ICC1 Vzener fault Auto-recovery FB reacts ok 40 μA Vtimer Vtimer startup DRV B version, auto-recovery Figure 21. The B Version Enters an Auto-Recovery Burst Mode in Presence of a Fault http://onsemi.com 17 NCP1351 Vcc Pulldown SCR action User reset Latched state ICC1 VccON Vccstop Vzener Pout ICC < 20 μA Pout>50% Pout>50% 100% Pout 50% Pout IFB overload overload 51 μA Vtimer Vtimer startup DRV C version, latched dual OCP level Figure 22. The C Version Latches if the Power Excursion Exceeds 50% of the Maximum Power Too Long (DCM Full Load Operation) Vcc VccON Pulses stopped Vccstop ICC4 ICC1 Vzener Pout 100% Pout Pout>50% Pout>50% 50% Pout IFB overload overload 51 μA Vtimer Vtimer startup DRV D version, auto-recovery dual OCP level Figure 23. The D Version Enters Auto-Recovery Burst Mode if the Power Excursion Exceeds 50% of the Maximum Power (DCM Full Load Operation) http://onsemi.com 18 NCP1351 Latch Input VCC The NCP1351 features a patented circuitry which prevents the FB input to be of low impedance before the VCC reaches the VCCON level. As such, the circuit can work in a primary regulation scheme. Capitalizing on this typical option, Figure 24 shows how to insert a zener diode in series with the optocoupler emitter pin. In that way, the current biases the zener diode and offers a nice reference voltage, appearing at the loop closure (e.g. when the output reaches the target). Yes, you can use this reference voltage to supply a NTC and form a cheap OTP protection. OVP D2 5V C2 100n FB R1 2.5k Latch C1 100nF C3 100nF Rpulldown Figure 24. The Latch Input Offers Everything Needed to Implement an OTP Circuit. Another Zener Can Help combining an OVP Circuit if Necessary VCC VCC OUT Aux + CVCC 20F R4 2.2k Laux CVCC 22F + Sec U1B U1A Latch Rpulldown ROVP C3 100nF D2 1N4937 C4 100n Latch D4 C1 100nF C5 1n Figure 25. You can either directly observe the VCC level or add a small RC filter to reduce the leakage inductance contribution. The best is to directly sense the output voltage and reacts if it runs away, as offered on the right side. Vds_max + 600 Design Example, a 19 V / 3 A A Universal Mains Power Supply Designing a Switch-Mode Power Supply using the NCP1351 does not differ from a fixed frequency design. What changes, however, is the regulation method via frequency variations. In other words, all the calculations must be carried at the lowest line input where the frequency will hit the maximum value set by the Ct capacitor. Let us follow the steps: Vin min = 100 Vdc (bulk valley in low-line conditions) Vin max = 375 Vdc Vout = 19 V Iout = 3 A Operating mode is CCM  = 0.8 Fsw = 65 kHz 1. Turn Ratio. This is the first parameter to consider. The MOSFET BVdss actually dictates the amount of reflected voltage you need. If we consider a 600 V MOSFET and a 15% derating factor, we must limit the maximum drain voltage to: 0.85 + 510V (eq. 17) Knowing a maximum bulk voltage of 375 V, the clamp voltage must be set to: Vclamp + 510 * 375 + 135V (eq. 18) Based on the above level, we decide to adopt a headroom between the reflected voltage and the clamp level of 50 V. If this headroom is too small, a high dissipation will occur on the RDC clamp network and efficiency will suffer. A leakage inductance of around 1% of the magnetizing value should give good results with this choice (kc = 1.6). The turn ratio between primary and secondary is simply: ǒVout ) VfǓ N + Vclamp (eq. 19) kc Solving for N gives: N+ kCǒVout ) VfǓ 1.6 Ns + + Np Vclamp + 0.234 http://onsemi.com 19 (19 ) 0.8) 135 (eq. 20) NCP1351 Let us round it to 0.25 or 1/N = 4 From Equation 17, a K factor of 0.8 (40% ripple) ensures a good operation over universal mains. It leads to an inductance of: L+ Ipeak I1 65k IL + IL 43)2 (100 0.8 72 + 493H Vin_mind max 100 + 493u LFSW (eq. 23) 0.43 (eq. 24) 65k + 1.34Apeak-to-peak Ivalley The peak current can be evaluated to be: Pout 19 + 0.8 Vin_min Iin_avg + Iavg Ipeak + t 19 (Vin_mind max)2 (eq. 26) (eq. 27) (eq. 28) 4. Based on the above numbers, we can now evaluate the RMS current circulating in the MOSFET and the sense resistor: Ǹ1 ) 1 ǒILǓ2 3 2I1 + 1.65 0.65 Ǹ1 ) 1 ǒ 19 4 + 0.43 4 ) 100 Id_rms + II Ǹd (eq. 21) In this equation, the CCM duty-cycle does not exceed 50%. The design should thus be free of subharmonic oscillations in steady-state conditions. If necessary, negative ramp compensation is however feasible by the auxiliary winding. 3. To obtain the primary inductance, we can use the following equation which expresses the inductance in relationship to a coefficient k. This coefficient actually dictates the depth of the CCM operation. If it goes to 2, then we are in DCM. L+ 1.34 IL + 2.33 * + 1.65A 2 2 Ivalley + Ipeak * IL + 2.33 * 1.34 + 1.0A 2. Calculate the maximum operating duty-cycle for this flyback converter operated in CCM: + 0.712 1.34 IL + ) + 2.33A 2 0.43 2 The valley current is also found to be: Figure 26. Primary Inductance Current Evolution in CCM VoutńN ) Vin_min ) II + Ipeak * TSW VoutńN d (eq. 25) On Figure 26, I1 can also be calculated: DTSW d max + Iavg 3 + 712mA 100 Ǔ 1.34 2 3 2 1.65 (eq. 29) + 1.1A 5. The current peaks to 2.33 A. Selecting a 1 V drop across the sense resistor, we can compute its value: Rsense + 1 1 + + 0.4 2.5 Ipeak (eq. 30) To generate 1 V, the offset resistor will be 3.7 k, as already explained. Using Equation 29, the power dissipated in the sense element reaches: (eq. 22) FSWKPin Psense + RsenseId_rms2 + 0.4 where K = IL/II and defines the amount of ripple we want in CCM (see Figure 26). • Small K: deep CCM, implying a large primary inductance, a low bandwidth and a large leakage inductance. • Large K: approaching BCM where the RMS losses are the worse, but smaller inductance, leading to a better leakage inductance. 1.12 + 484mW (eq. 31) 6. To switch at 65 kHz, the Ct capacitor connected to pin 2 will be selected to 180 pF. 7. As the load changes, the operating frequency will automatically adjust to satisfy either equation 5 (high power, CCM) or equation 6 in lighter load conditions (DCM). Figure 27 portrays a possible application schematic implementing what we discussed in the above lines. http://onsemi.com 20 NCP1351 R3 47k HV-Bulk R4 22 C2 10n 400V R13 47k R7 1M LP = 500H NP:NS = 1:0.25 NP:Naux = 0.18 D5 MBR20200 R2 1M U1B C12 + 100F 400V R15 3.7k C15 22p D2 MUR 160 U2 1 8 2 7 3 6 4 5 OVP Option C5a 1.2mF 25V D3 1N4937 D6 1N4148 R6 0.4 C9 100n C13 2.2nF Type = Y1 C8 270pF + VOUT 19V/3A GND R8 1k R12 4k 25V R16 10 R1 2.2k C7 220F 25V + T1 R10 62k U1A C10 0.1 R14 2.2k C6 100n + R18 47k R5 2.5k + L2 2.2 6A/600V M1 NCP1351B C4 100n C5b 1.2mF 25V C17 100 + R9 10k IC2 TL431 C3 C1 4.7 100nF 25V GND Figure 27. The 19 V Adapter Featuring the Elements Calculated Above 88 On this circuit, the VCC capacitor is split in two parts, a low value capacitor (4.7 F) and a bigger one (100 F). The 4.7 F capacitor ensures a low startup time, whereas the second capacitor keeps the VCC alive in standby mode (where the switching frequency can be low). Due to D6, it does not hamper startup time. 86 Vin = 230 Vac EFFICIENCY (%) 84 Application Results We assembled a board with component values close to what is described on Figure 27. Here are the obtained results: Pin @ no-load = 152 mW, Vin = 230 Vac Pin @ no-load = 164 mW, Vin = 100 Vac The efficiency stays flat to above 80%, and keeps good even at low output levels. It clearly shows the benefit of the variable frequency implemented in the NCP1351. Vin = 100 Vac 82 80 78 76 74 72 0 0.5 1 1.5 2 Iout (A) 2.5 3 3.5 Figure 28. Efficiency Measured at Various Operating Points http://onsemi.com 21 NCP1351 Another benefit of the variable frequency lies in the low ripple operation at no-load. This is what confirms Figure 29. Finally, the power supply was tested for its transient response, from 100 mA to 3 A, high and low line, with a slew-rate of 1 A/s (Figure 31). Results appear in Figures 31 and 32 and confirm the stability of the board. Vds 200 V/div Vds 200 V/div Vout 1.0 mV/div Vout 1.0 mV/div Figure 29. No-Load Output Ripple (Vin = 230 Vac) Figure 30. Same Conditions, Pout = 5 W Vout 50 mV/div Vout 50 mV/div Figure 31. Transient Step, Low Line Figure 32. Transient Step, High Line http://onsemi.com 22 NCP1351 20 9.1 19 9 VCCmin (V) VCCON (V) CHARACTERIZATION CURVES 18 17 16 -25 8.9 8.8 0 25 50 75 100 125 8.7 -25 0 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 33. VCCON Level versus Junction Temperature Figure 34. VCCmin Level versus Junction Temperature 71 274 270 ICSmax (A) 69.5 ICSmin (A) 25 68 266 262 66.5 258 65 -25 0 25 50 75 100 125 254 -25 0 Figure 35. ICSmin versus Junction Temperature 75 100 125 Figure 36. ICSmax versus Junction Temperature 517 11 515 10.8 ICT (A) VOFFset (mV) 50 TEMPERATURE (°C) TEMPERATURE (°C) 513 10.6 10.4 511 509 -25 25 0 25 50 75 100 125 10.2 -25 TEMPERATURE (°C) 0 25 50 75 100 125 TEMPERATURE (°C) Figure 37. Oscillator Offset Voltage versus Junction Temperature Figure 38. Timing Capacitor Charge-Current Variation versus Junction Temperature http://onsemi.com 23 NCP1351 534 990 980 531 VFAULT (mV) VFAULT (mV) 970 528 960 950 525 940 522 -25 0 25 50 75 100 930 -25 125 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 39. Fault Voltage Variations versus Junction Temperature (A and B Versions) Figure 40. Fault Voltage Variations versus Junction Temperature (C and D Versions) 2.05 53 2 52.5 1.95 52 IFAULT 1.85 1.8 51.5 51 50.5 1.75 50 1.7 1.65 -25 0 25 50 75 100 49.5 -25 125 0 25 Figure 41. KFAULT Variations versus Junction Temperature 75 100 Figure 42. IFAULT Current Variation versus Junction Temperature (Versions C and D) 5.2 5.1 5 4.9 4.8 4.7 -25 50 TEMPERATURE (°C) TEMPERATURE (°C) VLATCH (V) KFAULT 1.9 0 25 50 75 100 125 TEMPERATURE (°C) Figure 43. Latch Level Evolution versus Junction Temperature http://onsemi.com 24 12 NCP1351 ORDERING INFORMATION Device Package Type Shipping† NCP1351ADR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel NCP1351BDR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel NCP1351CDR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel NCP1351DDR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel NCP1351APG PDIP-8 (Pb-Free) 50 Units / Rail NCP1351BPG PDIP-8 (Pb-Free) 50 Units / Rail NCP1351CPG PDIP-8 (Pb-Free) 50 Units / Rail NCP1351DPG PDIP-8 (Pb-Free) 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 25 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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