NCP1381

NCP1381 Low−Standby High Performance PWM Controller Housed in a SO−14 package, the NCP1381 includes everything needed to build rugged and efficient Quasi−Resonant (QR) Switching Power Supplies. When powered by a front−end Power Factor Correction circuitry, the NCP1381 automatically disconnects the PFC controller in low output loading conditions (with an adjustable level), thus improving the standby power. This is particularly well suited for medium to high power offline applications, e.g. notebook adapters. When the current setpoint falls below a given value, e.g. the output power demand diminishes, the IC automatically enters the so−called skip cycle mode and provides excellent efficiency at light loads. Because this occurs at an adjustable low peak current together with a proprietary Soft−Skipt technique, no acoustic noise takes place. Skip cycle also offers the ability to easily select the maximum switching frequency at which foldback and standby take place. The NCP1381 also features several efficient protection options like a) a short−circuit / overload detection independent of the auxiliary voltage b) an auto−recovery brown−out detection and c) an input to externally latch the circuit in case of Overvoltage Protection or Over Temperature Protection. Features http://onsemi.com HIGH PERFORMANCE QR CONTROLLER FEATURING PFC SHUTDOWN MARKING DIAGRAM 14 14 1 SOIC−14 D SUFFIX CASE 751A 1 NCP1381G = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package NCP1381G AWLYWW • • • • • • • • • • • • • • • • • • Current−Mode Quasi−Resonant Operation Adjustable Line Over Power Protection Extremely Low Startup Current of 15 mA Maximum Soft−Skip Cycle Capability at Adjustable Peak Currents Plateau Sensing Overvoltage Brown−Out Protection Maximum tON Limitation Overpower Protection by current Sense Offset Internal 5 ms Soft−Start Management Short−Circuit Protection Independent from Auxiliary Level External Latch Input Pin for an OTP Signal Go−To−Standby Signal for the PFC Front Stage True Frequency (tON + tOFF) Clamp Circuit Low and Noiseless, No−Load Standby Power Internal Leading Edge Blanking +500 mA / −800 mA Peak Current Drive Capability 5 V / 10 mA Reference Voltage This is a Pb−Free Device ADJ_GTS BO DMG Timer Skip/OVP FB CS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc nc Ref GTS VCC DRV GND ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. Typical Applications • High Power AC/DC Adapters for Notebooks, etc • Offline Battery Chargers • Set−Top Boxes Power Supplies, TV, Monitors, etc © Semiconductor Components Industries, LLC, 2006 1 July, 2006 − Rev. 3 Publication Order Number: NCP1381/D NCP1381 TYPICAL APPLICATION EXAMPLE HV + PFC Stage + To PFC’s VCC OVP BO DMG GTS_ADJ 1 2 3 4 5 6 7 NCP1381 14 13 12 11 10 9 8 + Vref Vout + Skip GTS_ADJ OPP Figure 1. Typical Application Example PIN FUNCTION DESCRIPTION Pin# 1 2 3 4 5 6 7 8 9 10 11 Symbol GTS_ADJ BO DMG Timer Skip/OVP FB CS GND DRV VCC GTS GTS Level Adjustment Brown−out Detects the Zero Voltage Crossing Point Fault Timer Adjust the Skip Level Feedback Signal Current Sense Pin The IC Ground The Driver Output VCC Input Directly Powers the PFC Frontend Stage Reference Voltage − − Description An internal comparator senses the signal applied to this pin (typically a portion of FB signal) to detect the standby condition for GTS. By connecting this pin to a resistive divider, the controller ensures operation at a safe mains level. This pin detects the core reset event but also permanently senses the Flyback plateau, offering a clean OVP detection. Connecting a capacitor to this pin adjusts the fault timer. This pin alters the default skip cycle level and offers a mean to latchoff the controller when externally brought above 4 V. An optocoupler collector pulls this pin down to regulate. When the current setpoint falls below an adjustable level, the controller skips cycles. This pin cumulates two different functions: the standard sense function plus an adjustable offset voltage providing the adequate level of Overpower Protection. − With a drive capability of $500 mA/800 mA, the NCP1381 can drive large Qg MOSFETs. The controller accepts voltages up to 20 V and features an UVLO of 10 V typical. This pin directly powers the PFC controller by routing the PWM VCC to the PFC VCC. In standby (defined by GTS_ADJ), fault and BO conditions, this pin is open and the PFC is no longer supplied. This pin offers a 5 V reference voltage sourcing up to 10 mA. Not Connected Not Connected 12 13 14 Reference NC NC http://onsemi.com 2 NCP1381 INTERNAL CIRCUIT ARCHITECTURE 5 mA VDD ADJ_GTS 1 ADJ_GTS Section + 250 mV − + RST Timer + − + BOComp. 240 mV/ 500 mV VDD VCC Management UVLO, Latchoff + − 8 ms No DMG Timeout 4 ms Delayed 1 Shot VlatchDem + − + DMG 3 to Latch S CLK Q Q UVLO 12 + R Prioritary Reset VDD DRV 1 Shot shot DRV VDD tON + tOFF=8 ms Max Fsw Clamping + − + tON > 45 ms? Fault /4 Timer 4 SS Skip Fault / Startup 9 Skip/ OVP LEB OPP Offset I/V 85 mS − FB 6 30 mA VDD + Skip Section S Q Q 25 k Latchoff CS 7 + − + Vlatch 4 V Reset Plateau Sensing Soft−Skip Soft−Start SSCap R Switches are Kept Closed until NOR Output Goes Low VDD 8 GND IP Flag GTS + Soft−Start Ended − + + Timer − VTimFault VDD SSCap VTimSS + Drv + Timer 10 VCC BO 11 GTS Vref Ref + Timer IP Flag BO BO 2 S CLK Q Q R DRV 3 ms 1 Shot DRV − + + Vth GTS Conf. ? + − VDD − + IPFlag 5 Figure 2. Internal Circuit Architecture http://onsemi.com 3 NCP1381 MAXIMUM RATINGS TABLE Symbol Vsupply Rating Maximum Power Supply Voltage on Pin 10 (VCC), Pin 9 (DRV), and Pin 11 (GTS) Maximum Current in Pin 10 (VCC) Maximum Current in Pin 11 (GTS) Maximum Current in Pin 9 (DRV) Power Supply Voltage on all Other Pins Except Pin 10 (VCC), Pin 9 (DRV), Pin 3 (DMG) and Pin 11 (GTS) Maximum Current Into All Other Pins Except Pin 10 (VCC), Pin 9 (DRV) and Pin 11 (GTS) Idem RqJ−A Maximum Current in Pin 3 (DMG), When 10 V ESD Zener is Activated Thermal Resistance Junction−to−Air, SO−14 Maximum Junction Temperature Storage Temperature Range ESD Capability, Human Body Model per MIL−STD−883, Method 3015 (All Pins Except Ref) ESD Capability, Human Body Model per MIL−STD−883, Method 3015 (Ref Pin) ESD Capability, Machine Model Value 20 "30 "20 "1 −0.3 to 5 "10 +3 / −3 150 150 −60 to +150 2 1.8 200 Unit V mA mA A V mA mA °C/W °C °C kV kV V TJMAX NOTE: This device contains latchup protection and exceeds 100 mA per JEDEC standard JESD78. Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, VCC = 12 V unless otherwise noted) Symbol SUPPLY SECTION VCCON VCCOFF VCClatch VCCreset Istartup ICC1 ICC2 ICC3 Turn−on Threshold Level, VCC Going Up Minimum Operating Voltage After Turn−on VCC Decreasing Level at Which the Latchoff Phase Ends VCC Level at Which the Internal Logic Gets Reset Startup Current (VCC < VCCON) Internal IC Consumption, No Output Load on Pin 9, FSW = 60 kHz Internal IC Consumption, 1 nF Output Load on Pin 9, FSW = 60 kHz Internal IC Consumption, Latchoff Phase 10 10 10 10 10 10 10 10 13 9 − − − − − − 15 10 7 4 2 1.4 2.1 1.4 17.9 11 − − 15 1.8 2.6 − V V V V mA mA mA mA Rating Pin Min Typ Max Unit DRIVE OUTPUT Tr Tf ROH ROL Output Voltage Rise−Time @ CL = 1 nF, 10−90% of Output Signal Output Voltage Fall−Time @ CL = 1 nF, 10−90% of Output Signal Source Resistance Sink Resistance 9 9 9 9 − − − − 15 15 9 8 − − − − ns ns W W CURRENT COMPARATOR IIB ILimit Gm TDELCS TLEB SStart Input Bias Current @ 1 V Input Level on Pin 7 Maximum Internal Current Setpoint at VBO = 0 Transconductance Amplifier Offsetting CS at VBO = 2 V Propagation Delay from CS Detected to Gate Turned off (Pin 9 Loaded by 1 nF) Leading Edge Blanking Duration Typical Internal Soft−start Period at Startup 7 7 7 7 7 − − 0.75 70 − 300 2.5 0.02 0.8 85 90 370 4.0 − 0.85 100 − − 6.0 mA V mS ns ns ms http://onsemi.com 4 NCP1381 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, VCC = 12 V unless otherwise noted) Symbol CURRENT COMPARATOR Sskip Typical Internal Soft−start period when Leaving Skip − 100 175 250 ms Rating Pin Min Typ Max Unit GO−TO−STANDBY RGTS Rskip Vskip Hyst_ratio ADJ_GTS Ihyst Pin 11 Output Impedance (or Rdson between Pin 10 and Pin 11 when SW is Closed) Skip Adjustment Output Impedance Default Skip Cycle Level Ratio Between the Skip Level and the Skip Comparator Hysteresis Threshold of the ADJ_GTS Comparator Internal Current Source that Creates an Adjustable Hysteresis to the ADJ_GTS Comparator 11 5 5 − 1 1 − 17 − − 220 4.0 15 25 800 3.4 250 5.0 − 35 − − 280 6.0 W kW mV − mV mA DEMAGNETIZATION DETECTION BLOCK Vth VH VCH VCL Tdem Cpar Rdown Tblank Tsw−(min) Input Threshold Voltage (Vpin 3 Decreasing) Hysteresis (Vpin 3 Increasing) Input Clamp Voltage High State (Ipin 3 = 3.0 mA) Low State (Ipin 3 = −3.0 mA) DMG Propagation Delay Internal Input Capacitance at Vpin 3 = 1 V Internal Pulldown Resistor Internal Blanking Delay after TON Frequency Clamp, Minimum (TON + TOFF) 3 3 3 3 3 3 3 3 − 30 − 9 −0.9 − − 20 − 7.0 50 30 10 −0.7 200 10 30 3.5 8.0 80 − 12 −0.5 − − 45 − 9.0 mV mV V V ns pF kW ms ms FEEDBACK SECTION Rup Iratio Ref Iref Internal Pullup Resistor Pin 6 to Current Setpoint Division Ratio (Maximum VFB = 5 V) Voltage Reference, Iload = 1 mA Reference Maximum Output Current 6 − 12 12 7.5 − 4.75 10 10 4.0 5.0 − 12.5 − 5.25 − V mA kW PROTECTIONS Vzenlatch MaxtON Itimer Vtimfault Tdelay Vlatchdem Tsamp Vlatch TDELLATCH VBOhigh VBOlow IBO TSD TSDhyst VCC Limitation in Latched Fault Mode Maximum On Time Duration Timer Charging Current Timer Fault Validation Level Timeout Before Validating Short−circuit or GTS, Ct = 0.22 mF Latching Level On the Demagnetization Input Sampling Time for Vlatchdem Detection after the End of the TON Latchoff Level On the Skip Adjustment Pin Propagation Delay from Latch Detected to Gate Turned Off (Pin 9 Loaded by 1 nF) Brown−out Level High Brown−out Level Low Brown−out Pin Input Bias Current Temperature Shutdown, Maximum Value Hysteresis While in Temperature Shutdown 10 9 4 4 − 3 3 5 − 2 2 2 − − − − 7.0 3.5 − 3.7 − 3.15 − 0.45 0.21 − 140 − 6.0 45 10 4.0 90 4.1 4.0 3.5 220 0.5 0.24 0.04 − 30 − − 13 4.5 − 4.5 − 3.85 − 0.55 0.275 − − − V ms mA V ms V ms V ns V V mA °C °C http://onsemi.com 5 NCP1381 APPLICATION INFORMATION The NCP1381 includes all necessary features to help building a rugged and safe switching power supply featuring an extremely low standby power. The below bullets detail the benefits brought by implementing the NCP1381 controller. • Current−mode operation with Quasi−Resonant Operation: Implementing peak current mode control, the NCP1381 waits until the drain−source voltage crosses a minimum level. This is the quasi−resonance approach, minimizing both EMI radiations and capacitive losses. • Over Power Protection: Using a voltage image of the bulk level, via the brown−out divider, the designer can select a resistor which, placed in series with the current sense information, provides an efficient line compensation method. • Frequency Clamp: The controller monitors the sum of ton and toff, providing a real frequency clamp. Also the ton maximum duration is safely limited to 50 ms in case the peak current information is lost. If the maximum ton limit is reached, then the controller stops all pulses and enters a safe auto−recovery burst mode. • Blanking Time: To prevent false tripping with energetic leakage spikes, the controllers includes a 3 ms blanking time after the toff event. • Go−to−Standby Signal for PFC Front Stage: The NCP1381 includes an internal low impedance switch connected between Pin 10 (VCC) and Pin 11 (GTS). The signal delivered by Pin 11 being of low impedance, it becomes possible to connect PFC’s VCC directly to this pin and thus avoid any complicated interface circuitry between the PWM controller and the PFC front−end section. In normal operation, Pin 11 routes the PWM auxiliary VCC to the PFC circuit which is directly supplied by the auxiliary winding. When the SMPS enters skip−cycle at low output power levels, the controller detects and confirms the presence of the skip activity by monitoring the signal applied on its pin ADJ_GTS (typically FB signal) and opens Pin 11, shutting down the front−end PFC stage. When this signal level increases, e.g. when the SMPS goes back to a normal output power, Pin 11 immediately (without delay) goes back to a low impedance state. Finally, in short−circuit conditions, the PFC is disabled to lower the stress applied to the PWM main switch. • Low Startup−Current: Reaching a low no−load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. Due to a novel silicon architecture, the startup current is guaranteed to be less than 15 mA maximum, helping the designer to reach a low standby power level. • Skip−cycle Capability: A continuous flow of pulses in not compatible with no−load standby power requirements. Slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. Due to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. This is further strengthened by ON Semiconductor’s Soft−Skip technique, which forces the peak current in skip to gradually increase. In case the default skip value would be too large, connecting a resistor to the Pin 6 will reduce or increase the skip cycle level. Adjusting the skip level also adjusts the maximum switching frequency before skip occurs. Soft−Start: A circuitry provides a soft−start sequence which precludes the main power switch from being stressed upon startup. This soft−start is internal and reaches 5 ms typical. Overvoltage Protection: By sensing the plateau level after the power switch has opened, the controller can detect an overvoltage condition through the auxiliary reflection of the output voltage. If an OVP is sensed, the controller stops all pulses and permanently stays latched until the VCC is cycled down below 4.0 V. External Latch Input: By permanently monitoring Pin 5, the controller detects when its level rises above 3.5 V, e.g. in presence of a fault condition like an OTP. This fault is permanently latched−off and needs the VCC to go down below 4.0 V to reset, for instance when the user unplugs the SMPS. Brown−out Detection: By monitoring the level on Pin 2 during normal operation, the controller protects the SMPS against low mains condition. When the Pin 2 level falls below 240 mV, the controllers stops pulsing until this level goes back to 500 mV to prevent any instability. During brown−out conditions, the PFC is not activated. Short−cir cuit Protection: Short−circuit and especially overload protection are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding level does not properly collapse in presence of an output short). Here, every time the internal 0.8 V maximum peak current limit is activated, an error flag is asserted and a time period starts, due to an external timing capacitor. If the voltage on the capacitor reaches 4.0 V (after 90 ms for a 220 nF capacitor) while the error flag is still present, the controller stops the pulses and goes into a latch−off phase, operating in a low−frequency burst−mode. As soon as the fault disappears, the SMPS resumes its operation. The latchoff phase can also be initiated, more classically, when VCC drops below VCCOFF (10 V typical). • • • • • http://onsemi.com 6 NCP1381 Startup sequence When the power supply is first connected to the mains outlet, the NCP1381 starts to consume current. However, due to a novel architecture, the internal startup current is kept very low, below 15 mA as a maximum value. The current delivered by the startup resistor also feeds the VCC capacitor and its voltage rises. When the voltage on this capacitor reaches the VCCON level (typically 15 V), the controller delivers pulses and increases its consumption. At this time, the VCC capacitor alone supplies the controller: the auxiliary supply is supposed to take over before VCC collapses below VCCOFF. Figure 3 shows the internal arrangement of this structure: High Voltage Itotal Rstartup Istartup 10 UVLO + − + + Auxiliary Winding VCCON VCCOFF 8 CVCC Figure 3. The Startup Resistor Brings VCC Above 15 V HV Rstartup VCC VCC Management 10 As soon as VCC reaches 15 V (VCCON), driving pulses are delivered on Pin 9 and the auxiliary winding grows up the VCC pin. Because the output voltage is below the target (the SMPS is starting up), the controller smoothly pushes the peak current to Imax (0.8 V / Rsense) which is reached after 5 ms (typical internal soft−start period). After soft−start completion, the peak current setpoint reaches its maximum (during the startup period but also anytime a short−circuit occurs), an internal error flag is asserted, IP Flag, testifying that the system is pushed to the maximum power (IP = IP maximum). This flag is used to detect a faulty condition, where the converter asks for the maximum peak capability longer than what has been programmed by the designer. The duration of the faulty condition is actually set up by a capacitor connected to Pin 4. Figure 4 shows a portion of this internal arrangement. If the fault comparator acknowledges for a problem, the controller stops all driving pulses and turns−on the internal ICC3 current−source. This source serves for the latch−off phase creation, that is to say, forcing the VCC to go down, despite the presence of the startup current still flowing via the startup resistor. Therefore, ICC3 should be greater than Itotal to ensure proper operation. When VCC reaches a level of 7 V, ICC3 turns to zero and the startup current can lift VCC up again. When VCC reaches 15 V, a new attempt is made. If the fault is still there, pulses last either the timer duration or are prematurely stopped if a VCCOFF condition occurs sooner, and a new latchoff phase takes place. If the fault has gone, the converter resumes operation. Figure 5 portrays the waveforms obtained during a startup sequence followed by a fault. One can see the action of the ICC3 source which creates the latchoff phase and the various resets events on the timer capacitor in presence of the soft−start end or an aborted fault sequence. Knowing that Itimer equals 10 mA, we can calculate the capacitor needed to reach 4 V in a typical time period. Suppose we would like a 100 ms fault duration, therefore: Ctimer = 10 m x 100 m / 4 = 250 nF, select a 0.22 mF. Latchoff ICC3 + CVCC VDD Itimer Fault Confirmed + − 4 + 4.0 V Ctimer Soft−Start Soft−Burst SW Reset IP Flag Figure 4. The Timer Section Uses a Current Source to Charge Up the Capacitor http://onsemi.com 7 NCP1381 Figure 5. A Typical Startup Sequence Followed by a Faulty Condition Startup Resistor Calculation For the sake of the example, we will go through the calculation of the startup element. Suppose that we have the following information: VCCON = 15 V. VCCOFF = 10 V. ICC2 = 4 mA, given by the selected MOSFET Qg. Startup duration below 2 s at minimum input voltage. Input voltage from 85 VAC to 265 VAC. Standby power below 500 mW. 1. From a startup DV of 15 − 10 = 5 V and a 4 mA total consumption, we can obtain the necessary VCC capacitor to keep enough voltage, assuming the feedback loop is closed within 10ms: CVCC = 4 m x 10 m / 5 = 8 mF or 22 mF for the normalized value if we account for the natural dispersion. 2. If we want a startup below 2 s, then the charging current flowing inside the VCC capacitor must be above: Icharge > 15 x 22 u / 2 > 165 mA. If we add the 15 mA of ICC1, the total startup current shall be above 180 mA. 3. The minimum input voltage is 85 x 1.414 = 120 V. Then, Rstartup should be below (120 − 15) / 180 m < 580 kW. 4. From this value, we can calculate the dissipated power at high line: Pstartup = (265 x 1.414)2 / 580 k = 242 mW. In latched mode, an internal zener diode is activated and clamps VCC to around 6 V. When VCC goes below 4 V, this zener is relaxed and the circuit can startup again. Please note that in fault mode the VCC comparator has the priority and stops the pulses anytime VCC falls below its minimum operating level VCCOFF. http://onsemi.com 8 NCP1381 VCC VCCON VCCOFF tOFF TW DRV Leakage Ringing 1st Valley tON Figure 7. Typical Quasi−Resonance Waveform 100 ms Bunch Length Given by Timer < 100 ms Bunch Length Given by VCCOFF Ipeak V s ON + in LP s OFF + N @ (V out ) V f) LP If VCC drops below VCCOFF during a portion where the timer counts, pulses are immediately stopped and the latchoff phase is entered. Here, in this example, the timer was set to 100 ms. Figure 6. ON OFF IP = 0 Quasi−Resonance Operation Quasi−Resonance (QR) implies that the controller permanently monitors the transformer core flux activity and ensures Borderline Conduction Mode (BCM) operation. That is to say, when the switch closes, the current ramps up in the magnetizing inductance LP until it reaches a setpoint imposed by the feedback loop. At this point, the power switch opens and the energy transfers from the primary side to the secondary (isolated) portion. The secondary diode is now biased and the output voltage “flies back” to the primary side, now demagnetizing the primary inductance LP. When this current reaches zero, the transformer core is said to be “reset” (ö = 0). At this time, we can turn the MOSFET on again to create a new cycle. Figure 7 and 8 portray the typical waveforms with their associated captions. If a delay TW is introduced further to the core reset detection and before biasing the power MOSFET, the drain signal Vds(t) has the time to go through a minimum, also called valley. Therefore, when we will finally reactivate the power MOSFET, its drain−to−source voltage will be minimum, reducing capacitive losses but also its gate−charge value, since the Miller effect gets diminished at low Vds. 0 TW Figure 8. Magnetizing Inductance Current Waveforms The flux activity monitoring is actually made via an auxiliary winding, obeying the law, Vaux = N . dö / dt. Figure 9 describes how the detection is made, since the signal obtained on the auxiliary winding is centered to zero. Let’s split the events with their associated circuitry: tON The D flip−flop output is high, the MOSFET is enhanced and current grows−up in the primary winding. This is the on portion of Figure 8, left side of the triangle. When the driver output went high, its rising edge triggered a 8 ms timer. This 8 ms timer provides a true frequency clamp by driving the D−input of the flip−flop. Now, when the peak current reaches the level imposed by the feedback loop, a reset occurs and the flip−flop output comes low. If for any reason the controller keeps the gate high (DRVout) implying a tON longer than 50 ms, then all pulses are stopped and the controller enters a safe, autorecovery, restart mode. This condition can occur if the current sense pin does not receive any signal from the sense resistor or if a short−circuit brings the CS pin to ground for instance. http://onsemi.com 9 NCP1381 tOFF As one can see from Figure 7, a parasitic ringing takes place at the switch opening: this is the leakage inductance contribution. Unfortunately, this leakage can be detected as a core reset event if no precaution is taken. This explains the presence of the 3 ms blanking timer that prevents any restart before the completion of this circuit. After leakage, the voltage applied over the primary winding is an image of the output voltage: this is the flyback level, or plateau level, equal to N(Vout + Vf), with N the turn ratio between the primary and the secondary, Vout the output voltage and Vf, the secondary diode forward drop. We are on the right portion of Figure 8, OFF portion, the secondary current ramping down. If we now observe the voltage on the auxiliary winding, we will see something like what Figure 10 shows where the plateau lasts until the core is reset. At this reset event, a natural ringing takes place whose amplitude depends on the ratio N and Vout. A comparator observes this activity and detects when the voltage drops below ground, actually below 45 mV typically. In Figure 9, one can see the ESD protection arrangement which introduces a small capacitive component to Pin 3 input. This capacitive component associated with the demagnetization resistor can thus realize the necessary above TW delay. The comparator output now propagates to the clock input of a D flip−flop. Hence, the demagnetization is edge triggered. At the beginning of the cycle (the rising edge of the ON time), the 8 ms timer was started. The output of this timer goes to the D−input of the D flip−flop. Thus, if the demagnetization comparator attempts to trip the D flip−flop when the 8 ms timer has not been completed, the restart is ignored until a new demagnetization signal comes in. This offers the benefit to clamp the maximum switching frequency to 8 ms or 125 kHz. Please note that the 8 ms timer clamps tON + tOFF. If everything is met, then the flip−flop output goes high and a new switching cycle occurs. Several events can alter this behavior, as described below: 1. The converter is in light load conditions and the theoretical frequency is above 125 kHz. There, the D−input is not validated and the reset event is ignored. The flip−flop waits for another wave to appear. If outside of the 8 ms window, i.e. Fswitching below 125 kHz, the event is acknowledged and a new cycle occurs. Note that wave skipping will always occur in the drain−source valley. 2. We are skipping cycle at moderate power and the skip comparators dictates its law. In that case, if the flip−flop is permanently reset, it naturally ignores all demagnetization restart attempts, provided that the drain oscillations are still there. When the flip−flop reset is released, the controller acknowledges the incoming demagnetization order and drives the output high. Again, skip cycles events always take place in the valley. 3. The controller skips cycles at low power and the order appears in a fully damped drain−source portion. In that case, the 8 ms timeout generator will give the signal in place of the demagnetization comparator. This timeout generator is reset everytime waves appear but starts to count down when there is no sufficient amplitude on the drain. At the end of the 8 ms, if no wave has appeared, it goes high, indicating that the controller is ready to restart anytime a skip order takes place. See skip section for more details. http://onsemi.com 10 NCP1381 VDD S D Q + + − VDD CLK Q R 3 ms Blanking Demag 2 + − + D Prioritary Reset S Q DRV DRV CLK Q R 45 mV DRV One Shot VDD Skip ILimit Reset Reset VDD + − + + + − Fault Figure 9. Internal QR Architecture Skipping Cycle Mode 7.00 DEMAG SIGNAL (V) 5.00 Possible Restart 3.00 1.00 0V 45 mV −1.00 The NCP1381 automatically skips switching cycles when the output power demand drops below a given level. This is accomplished by monitoring the FB pin. In normal operation, pin 6 imposes a peak current accordingly to the load value. If the load demand decreases, the internal loop asks for less peak current. When this setpoint reaches a determined level, the IC prevents the current from decreasing further down and starts to blank the output pulses: the IC enters the so−called skip cycle mode, also named controlled burst operation. The power transfer now depends upon the width of the pulse bunches (Figure 11) and follows the following formula: 1@L @I 2@F @D PP sw burst 2 (eq. 1) Figure 10. Core Reset Detection is Done Through the Monitoring of a Dedicated Auxiliary Winding with LP = Primary Inductance Fsw = Switching Frequency Within the Burst IP = Peak Current at which Skip Cycle Occurs Dburst = Burst Width/Burst Recurrence http://onsemi.com 11 NCP1381 Figure 12 depicts the internal comparator arrangement. The FB pin level is permanently compared to a fixed level, Vskip, also available on Pin 5 for adjustment. As a result, the user can wire a resistor to ground and alter the skip level in case of noise problems. When the FB pin is above Vskip, the comparator is transparent to the operation. When the load becomes lighter, the FB level goes down too. When it reaches Vskip, the comparator goes high and resets the internal flip−flop: the driving pulses are stopped. As a result, Vout starts to also decrease since no energy transfer is ensured. Detecting a decay in the output voltage, the FB loop will react by increasing its level. When the level crosses Vskip plus a slight hysteresis, pulses restart again: a ripple occurs on the FB pin. Please note that the soft−start will be activated every time the skip comparator asks to restart. Therefore, instead of having sharp skip transitions, a smooth current rampup can be observed on the current envelope. This option significantly decreases the acoustical noise. Figure 13 shows a typical shot and Figure 15 portrays several skip cycles. CURRENT SENSE SIGNAL (mV) Maximum Peak Current 200 Skip Cycle Current Limit 100 VDD 6 VDD 30 mA Vskip 5 R 8 25 k Soft−Start Activation − + Reset Hysteresis = 50 mV Figure 12. A Resistor to GND can Adjust the Skip Level 0 Width Recurrence Figure 11. The Skip Cycle Takes Place at Low Peak Currents Which Guaranties Noise Free Operation As soon as the feedback voltage goes up again, there can be two situations as we have seen before: in normal operating conditions, e.g. when the drain oscillations are generous, the demagnetization comparator can detect the 45 mV crossing and gives the “green light”, alone, to reactive the power switch. However, when skip cycle takes place (e.g. at low output power demands), the restart event slides along the drain ringing waveforms (actually the valley locations) which decays more or less quickly, depending on the Lprimary−Cparasitic network damping factor. The situation can thus quickly occur where the ringing becomes too weak to be detected by the demagnetization comparator: it then permanently stays locked in a given position and can no longer deliver the “green light” to the controller. To help in this situation, the NCP1381 implements a 8 ms timeout generator: each time the 45 mV crossing occurs, the timeout is reset. So, as long as the ringing becomes too low, the timeout generator starts to count and after 8 ms, it delivers its “green light”. If the skip signal is already present then the controller restarts; otherwise the logic waits for it to release the reset input and set the drive output high. Figure 14 depicts these two different situations: http://onsemi.com 12 NCP1381 Figure 13. The Soft−start Starts During Skip Mode and Smooths the Current Signature DRAIN SIGNAL Figure 15. The Internal Soft−start is Activated During Each Skipped Cycles Overpower Compensation A FLYBACK converter operating in Borderline Conduction Mode (BCM) transfers energy from primary to secondary according to the following law: P Pin + out + 1 @ LP @ IP 2 @ F SW h 2 (eq. 2) Timeout Signal Demag Restart Therefore, we can see that for various switching frequency values (dependent on the input condition if the output demand is fixed), the converter will permanently adjust the peak current IP to keep the output power constant. By manipulating the slope definitions SON and SOFF (see Figure 8), we can show that the peak current is defined by: IP + 2 @ Pout @ N @ (Vout ) VF) ) Vin h @ Vin @ N @ (Vout ) VF) (eq. 3) Current Sense and Timeout Restart DRAIN SIGNAL 8 ms 8 ms where h is the converter’s efficiency, Vin the input voltage, Vout the output voltage. Feeding a math processor lets us graph the peak variation with the input voltage, as depicted by Figure 16 for a 90 W converter operating on universal mains and featuring the following parameters: Vout = 19 V @ 4.7 A, NP:NS = 1:0.166, Rsense = 0.25 W, 200 VDC − 400 VDC Input Voltage, tP (Propagation Delay) = 100 ns, LP = 700 mH, h = 0.85 and VF = 0.8 V Note that these elements were selected to design for a 100 W value, giving us design margin. Timeout Signal Figure 14. The 8 ms Timeout Helps to Restart the Controller http://onsemi.com 13 NCP1381 3.2 3.1 3.0 IP(Vin) (A) IP(PO) 2.9 2.8 2.7 2.6 2.5 200 0 250 300 Vin, VOLTAGE (V) 350 400 0 20 40 PO 60 80 100 Required IPmax 2 3 4 1 Figure 16. Peak Current Evolution with Input Voltage in a QR Converter at Constant Output Power (100 W) Figure 17. IP Evolution with Output Power As a result, we will probably calculate our sense resistor to let the converter bring the peak current up to 3.15 A at low mains (200 VDC in follower−boost configuration). Unfortunately, in high mains conditions, where the PFC delivers up to 400 VDC, the controller will also allow the same 3.15 A maximum peak current (even a little more with the propagation delay) and the power will dramatically increase. In these conditions, the maximum power shall absolutely be clamped in order to avoid lethal runaways in presence of a fault. If overpower compensation via a resistor to the bulk capacitor offers a possible way, it suffers from the lack of precision and good repeatability in production. It also degrades the standby consumption. Since our controller integrates a brown−out (BO) protection that permanently senses the bulk capacitor, we naturally have a voltage image of the bulk voltage. By converting the BO level into a current, then routing this current in the current sense (CS) pin, we can easily create a 130 125 120 IP(Vin) (A) 115 110 105 100 200 250 300 Vin, VOLTAGE (V) 350 400 variable offset that will compensate the maximum output power. This would result in a variable IPmax as exemplified by the dashed line on Figure 16. From the peak current definition, we can extract the output power variation, with a fixed peak current (the maximum peak the controller will authorize is 0.8 / Rsense) and thus quantify the difference between low and high line: Pnc(Vin) :+ 0.8 RS ) Lin @ tP P V 2 (h@(Vin@(Vout)VF))) @ Vout ) VF ) Vin N (eq. 4) where tP is the propagation delay (100 ns typically). If we enter our previous parameters into the noncompensated output power definition and plot the result versus the input voltage, then we obtain the following graph, Figure 18: IP LL 0.8 V 0.64 V t Figure 19. A Possible Way to Compensate the Current Excursion Lies in Offsetting the Current Floor Figure 18. Output Power Evolution with the Input Voltage (No Compensation) http://onsemi.com 14 NCP1381 As one can observe, the output power runs out of the initial 100 W specification when we enter the high line region. To cope with this problem, we need to compensate the controller in such a way that its peak capability gets reduced at higher input voltages. How much do we need to compensate the peak excursion? We can find the answer by calculating DIP = IPLL − IPHL, with VinLL = 200 V and VinHL = 400 V. With our previous numbers, DIP = 588 mA. We therefore need to instruct the controller to reduce its peak excursion by 588 mA at high line. Otherwise speaking, if we think in voltages, the CS pin excursion shall drop from 0.8 V (at low line, the maximum peak is 0.8 / RS) to (3.2 − 0.588). Vbulk G1 80 mS 105 − BO + 100 PO(Vin) (V) CS Roffset 90 Rsense To CS Comp. 200 250 300 350 400 Vin, VOLTAGE (V) 0.8 RS 0.25 = 653 mV at high line. Figure 19 shows the situation at both line levels. A possible solution lies in offsetting the current floor by the necessary value, which is, in our case, 0.8 − 0.653 = 147 mV. The traditional way of doing this goes through the wiring of a high value resistor to the bulk capacitor. This unfortunately dissipates heat. The NCP1381 offers a more elegant option since it transforms the voltage available from the Brown−out pin into a fixed current, routed to the CS pin. That way, we can calculate a resistor value which, once inserted in series with current sense voltage image, will create our necessary offset. Figure 20 shows this internal connection: To BO Comp. 95 Figure 20. A Transconductance Amplifiers Transforms the BO Voltage into a Current Figure 21. The Compensated Converter Output Power Response to Input Variations We can now calculate our Roffset resistor to generate the necessary static voltage. Suppose that the BO network divides the bulk voltage by 400 (VBO = a . Vin = 0.0025 x Vin). Therefore, in presence of a 400 V input voltage, we will have 1 V on the BO pin. due to the transconductance amplifier of a 80 mS gm, it will turn into a 80 mA offset current. To get our 147 mV, we just divide it by 80 mA: Roffset = Voffset / VinHL x a . gm = 1.8 kW. We can now update Equation 4 with Equation 5, where the peak current is affected by the variable offset: PO(Vin) :+ ) Vin LP were originally shooting for and the total power excursion is now kept within 15 W. Overvoltage Protection @ tP * Vin @ a @ gm @ Roffset 2 (h@(Vin@(Vout)VF))) @ Vout ) VF ) Vin N (eq. 5) If we now plot the compensated curve, we obtain Figure 21 graph. The output power is slightly above what we The NCP1381 features an overvoltage protection made by sensing the plateau voltage at the switch turn−off. However, a sampling delay is introduced to avoid considering the leakage inductance. When the demagnetization pin goes above Vdemlatch, the comparator goes high. If this condition is maintained when the sampling pulse arrives, then a fault is latched. Figure 22 shows the arrangement and Figure 23 portrays a typical waveform. Once latched, the controller stops all driving pulses and VCC is clamped to 6 V. Reset occurs when the user unplugs the converter from the mains and VCC reduces below 4 V. http://onsemi.com 15 NCP1381 Demag To Demag Comp. 700 + 500 IP(Vin) (A) 1 Shot Timer Latch Input −100 58.5 62.5 66.5 TIME (mS) DRV 70.4 74.4 + Vlatchdem Figure 22. Plateau Sensing Overvoltage Protection External Latchoff By lifting up Pin 5 above Vlatch (3.5 V typical), the circuit is permanently latched. That is to say, Pin 9 goes low, the GTS pin no longer supplies the PFC and the VCC is clamped to 6 V. The latch reset occurs when VCC falls below 4 V, e.g. OVP Skip Latch Latch + + Vlatch + Vmax < 5 V! Figure 24. Wiring a PNP Transistor on the Skip Cycle Input Pin will Latch the Circuit. Keep in mind that the 5 V maximum limit on all low voltage pins implies some precaution when triggering the latch voltage. The cheapest option is obtained when wiring a simple zener diode in series with the monitored line. Care must be taken to limit the excursion of the skip pin before fully latching the controller. http://onsemi.com 16 − − Vref Skip + 300 100 Tsamp Figure 23. Typical Sensed Waveforms when the user unplugs the converter from the mains. Figure 24 shows several options on how to connect a PNP to implement an OVP or Overtemperature Protection (OTP). OVP Vref Skip NTC − Vlatch Go−To−Standby detection The PFC front−end stage delivers an elevated voltage to the Flyback converter and keeps the mains power factor close to unity. However, in standby, this PFC stage is no longer needed and must be turned off to save watts and thus reduce the no−load standby power. To detect when the converter enters standby, the controller observes the voltage available on Pin 1: typically, a portion of the feedback voltage will be used. In higher power conditions, this level NCP1381 is high, in low power conditions, this voltage is low. Unfortunately, the situation complicates with QR converters since the input voltage plays a significant role in the feedback voltage evolution. A case can happen where the converter is supplied by a 400 V rail and suddenly enters standby: the PFC turns off and the bulk voltage goes low, let’s say 120 VDC (Vin = 85 VAC). At this time, the power transfer changes, the propagation delay plays a smaller role and the feedback voltage naturally goes up again. If a sufficient hysteresis is not built, there are possibilities to see hiccup on the PFC VCC, which is not a desirable feature. Therefore, hysteresis is mandatory on top of the Go−To−Standby (GTS) detection level. For this reason it is possible to increase the hysteresis of the ADJ_GTS comparator due to an internal 5 mA current source that can create an offset to the input signal if a series resistor is inserted. The ADJ_GTS detection level is also adjustable by tuning the portion of the external signal applied to Pin 1 (the reference of the internal comparator is 250 mV). Again, to check how we manage the feedback variations, we can plot these variations without compensation for a given power, and with the offset resistor connected to the CS pin. In the first case, the FB voltage dependency on Vin can be expressed by: 0.35 FB(Vin) :+ 2 @ PO @ N @ (Vout ) VF) ) Vin V * in @ tP h @ Vin @ N @ (Vout ) VF) LP (eq. 6) @ RS @ FBCS Where FBCS is the ratio between the FB level and the current setpoint. In our controller, this ratio is 4. If we now incorporate our offset voltage generated by the Roffset resistor and the input voltage, the compensated FB variation expression becomes: FBComp(Vin) :+ 2 @ PO @ N @ (Vout ) VF) ) Vin h @ Vin @ N @ (Vout @ VF) (eq. 7) V * in @ tP] @ RS ) Vin @ a @ gm @ Roffset] LP @ FBCS with a the BO divider ratio (0.00414 in our example), gm the transconductance slope of 80 mS and Roffset, the selected offset resistor. If now plot Equation 6 and Equation 7 for a 8 W output power, we will obtain Figures 25 and 26: 0.75 0.7 FBComp(Vin) (V) 100 150 200 250 300 350 400 0.65 0.6 0.55 0.5 0.45 100 0.3 FB(Vin) (V) 0.25 0.2 0.15 0.1 Vin, VOLTAGE (V) 150 200 250 300 350 400 Vin, VOLTAGE (V) Figure 25. Uncompensated FB Variations for Pout = 8 W Figure 26. Compensated FB variations Pout = 8 W As one can see on Figure 26, the FB level now falls down when the PFC is shut off. It now goes in the right direction (FB growing up with Vin) and this plays in our favor to not cross again the upper comparison level, as it could be the case in Figure 25. However, we must check that the offset programmed by Roffset (147 mV in our example) multiplied by 4, is still below our skip cycle level, otherwise the converter will never enter skip at high line (the permanent offset at high line will force a higher feedback): 0.147 @ 4 + 588 mV t 0.75 V (eq. 8) This is okay. The drawback of Figure 26 is the higher forced level for lower power outputs. In our example, a 90 W adapter, the PFC will be shutdown at Pout = 8 W, or a bit less than 10% of the nominal power. If the designer needs to increase or decrease this value, it can adjust the ADJ_GTS level, still keeping in mind Equation 8 relationship. To avoid a false tripping, the timer (90 ms with Pin 4 capacitor of 220 nF) will be started every time the GTS signal goes high. If at the end of the 90 ms the GTS signal is still high, the standby is confirmed and the SW switch between Pins 11 and 10 opens. To the opposite, when the output power is needed, there is no delay and the SW switch turns on immediately. Figure 27 zooms on the internal circuitry whereas Figure 28 shows typical signal evolutions: http://onsemi.com 17 NCP1381 VDD Ext, SIgnal (FB, AUX) 5 mA To PFC VCC GTS VCC CVCC ADJ_GTS + Rhyst − 250 mV + + Timer VDD Figure 27. The SW Switch is Turned Off After the Timer Confirms the Presence of a Standby During the startup sequence, the PFC is disabled (in short−circuits too) and runs as soon as the IP Flag goes down. When the standby is detected, the timer runs and confirms the standby mode. When the mode is left, there is no delay and the PFC is turned−on immediately. Figure 28. http://onsemi.com 18 − + NCP1381 During the startup sequence, the converter starts by itself, the PFC is in off mode (SW switch is open). However, when the IP Flag is down, without delay, the PFC is turned on. In short−circuit mode, the IP Flag is constantly high during startup attempts and the PFC never turns on. This option reduces the stress on all the elements. The PFC is also in off mode when in presence of a brown−out detection. In brown−out conditions, the PFC is turned−off. When the level on Pin 2 is back to normal conditions, then a clean startup sequence takes place as Figure 28 depicts and the PFC turns on after the IP Flag release. The bullets below summarize what we have described: 1. On startup, the PFC is turned on immediately after the IP Flag has disappeared (converter is stabilized). There is no delay. 2. If a short−circuit occurs, a delay takes place before shutting off the driving pulses. When the delay is elapsed, pulses are turned off and the PFC goes in the off mode. The controller starts to hiccup. 3. In short−circuit hiccup mode, as IP Flag always stays high (in short−circuit, there is no FB signal), the PFC is never activated. 4. if a VCCOFF condition occurs, all pulses are immediately shutdown and the PFC VCC goes low as well. 5. if a brown−out condition is sensed, all pulses are immediately shut down and the PFC VCC goes low as well. The freedom is given to the designer to use an other signal than the FB to detect the standby mode and shutdown the PFC (the voltage from the auxiliary winding, or the average of the DRV signal for instance). Brown−Out Protection HV BOK OPP Rupper Figure 29. A Way to Implement a BOK Detector on Pin 2 Also called “Bulk OK” signal (BOK), the brown−out (BO) protection prevents the power supply from being adversely destroyed in case the mains drops to a very low value. When this occurs, the controller no longer pulses and waits until the bulk voltage goes back to its normal level. A certain amount of hysteresis needs to be provided since the bulk capacitor is affected by some ripple, especially at low input levels. For that reason, when the BO comparator toggles, the internal reference voltage changes from 500 mV to 250 mV. This effect is not latched: that is to say, when the bulk capacitor is below the target, the controller does not deliver pulses. As soon as the input voltage grows−up and reaches the level imposed by the resistive divider, pulses are passed to the internal driver and activate the MOSFET. Figure 29 offers a way to connect the elements around Pin 2 to create a brown−out detection. Please note that this technique does not use a current source for the hysteresis but rather a capacitor. It offers a way to freely select the resistive bridge impedance. The calculation procedure for Rupper and Rlower requires a few lines of algebra. In this configuration, the first level transition is always clean: the SMPS is not working during the startup sequence and no ripple exists superimposed on Cbulk. Supposed we want to start the operation at Vbulk = Vtrip = 120 VDC (VinAC = 85 V). 1. Fix a Bridge Current Ib Compatible with Your standby Requirements, for Instance an Ib of 50 mA 2. Then Evaluate Rlower by: Rlower = 0.5 / Ib = 10 kW 3. Calculate Rupper by: (Vtrip − 0.5 V) / Ib = (120 − 0.5) / 50 m = 2.39 MW The second threshold, the level at which the power supply stops (Vstop), depends on the capacitor Cfil but also on the selected bulk capacitor. Furthermore, when the load varies, the ripple also does and increases as Vin drops. If Cfil allows too much ripple, then chances exist to prematurely stop the converter. By increasing Cfil, you have the ability to select the amount of hysteresis you want to apply. The less ripple appears on Pin 2, the larger the gap between Vtrip and Vstop (the maximum being Vstop = Vtrip / 2). The best way to assess the right value of Cfil, is to use a simple simulation sketch as the one depicted by Figure 30. A behavioral source loads the rectified DC line and adjusts itself to draw a given amount of power, actually the power of your converter (35 W in our example). The equation associated to Bload instructs the simulator to not draw current until the brown−out converter gives the order, just like what the real converter will do. As a result, Vbulk is free of ripple until the node CMP goes high, giving the green light to switch pulses. The input line is modulated by the “timing” node which ramps up and down to simulate a slow startup / turn−off sequence. Then, by adjusting the Cfil value, it becomes possible to select the right turn off AC voltage. Figure 31 portrays the typical signal you can expect from the simulator. We measured a turn on voltage of 85 VAC whereas the turn−off voltage is 72 VAC. Further increasing Cfil lowers this level (e.g. a 1 mF gives 65 VAC in the example). http://onsemi.com 19 + − + 2 250 mV/ 500 mV Rlower 8 NCP1381 Bulk V (line) D V (timing) + 2 B1 Voltage 3 Bulk Line + Timing Rupper V1 + V2 Cfil 220 n + − + TiCMP Brown Out 5 Bbrown Voltage V (CMP) u 3 ? 250 m : 500 m P Spice : EB brown Value + {IF (V(CMP) u 3, 250 m, 0)} IN − + Cbulk 47 mF IC = 40 Vload Bload Current 35 V(CMP) u 3 ? :0 V(bulk) P Spice : EB load Value + IF (V(CMP) u 3, 35 V(bulk) , 0) Rlower V1 Timing 0 PWL 0 0.2 3s 1 7s 1 10s 0.2 V2 Line 0 SIN 150 50 Figure 30. A Simple Simulation Configuration Helps to Tailor the Right Value for Cfil 200 16 Turn−off Voltage Occurs at: VinRMS = 72.3 V 100 12 0 8 −100 4 Vbrown−out −200 0 8.156 8.175 8.195 8.215 8.235 Figure 31. Typical Signals Obtained from the Simulator Brown−out internal circuit Given the low startup current and the weak overall consumption of the controller, a circuit needs to be found in order to create a hiccup mode when there is not enough mains detected on Pin 2. Figure 32 portrays the solution based on a 1mA current source, solely activated when the VCC is going low and the BOK has not authorized the controller to pulse. This 1 mA actually discharges the VCC capacitor to make VCC reach 10 V. At this point, the source goes to zero and the startup resistor replenishes the VCC capacitor. When we reach 15 V, the logic checks whether the BOK gives the green light. If not, VCC goes low via the 1 mA. The logic arrangement is made in such a way that if the mains comes back asynchronously to VCC (e.g. in the downslope or in the upslope), we always restart at VCC = 15 V. Figure 33 shows a simulated behavior with a mains going up and down. Figure 34 and 35 confirm the good restart synchronization with the 15 V level. http://onsemi.com 20 NCP1381 IP Flag GTS SS Activated During Fault Only One Shot Reset VDD Vbulk + − + Rstartup VCCON VCClatch + − + VCCON VCCOFF + − + 2 4 Ctimer 11 + CVCC 8 ICC3 8 + − S One Shot Fault R Q Q Simplified Timer for BOK and Fault Only Fault S Q Q S&R are Positive Edge Triggered OK to Pulse R Figure 32. The Internal Brown−out Circuit Figure 32 also includes the short−circuit latch−off phase generation. The difference between behaviors in BO or short−circuit, is the lack of latch−off phase in brown−out conditions: VCC ramps up and down between VCCON and VCCOFF in BO, whereas it goes down to 7 V and up to 15 V in short−circuit conditions. Figure 36 shows how VCC moves when a short−circuit is detected. In BO conditions, the PFC is disabled as in UVLO conditions. http://onsemi.com 21 NCP1381 200 160 120 80 40 35 25 15 5.0 −5.0 Plot1 Vin (V) Bulk Voltage Plot2 2 VCC (V) VCC Plot3 3 6.5 4.5 2.5 500m −1.5 VOK (V) Internal OK Signal 10.0m 30.0m 50.0m TIME (s) 70.0m 90.0m The mains goes up and down, the bottom signal stops pulses at low mains but reactivates them when VCC = 15 V. Figure 33. 35.0 25.0 15.0 5.00 −5.00 6.5 4.5 2.5 500m −1.5 14 10 6.0 2.0 −2.0 VCCin (V) Plot2 VCC VOK (V) Plot3 PON Reset BOK (V) Plot1 BOK 41.3m 41.8m 42.4m TIME (s) 42.9m 43.5m The BOK comes back in the descent but the logic waits until the UVOL circuitry detects 15 V to restart the controller. Figure 34. http://onsemi.com 22 NCP1381 35 25 15 5.0 −5.0 6.5 4.5 2.5 500m −1.5 14 10 6.0 2.0 −2.0 VCCin (V) Plot2 VCC 41.3m VOK (V) Plot3 41.8m 42.4m 42.9m 43.5m PON Reset 41.3m BOK (V) Plot1 BOK 41.8m 42.4m 42.9m 43.5m 42.4m 42.9m 43.5m TIME (s) The BOK comes back in the upslope but the logic 2 waits until UVOL circuitry detects 15 V to restart the Controller. 41.3m 41.8m Figure 35. 8.50 18.0 6.50 VCCin (V) 14.0 VCC 15 V VOKin (V) 4.50 10.0 Plot1 2.50 6.00 500m 2.00 VOK 20.0m 60.0m 100m TIME (s) 140m 180m In short−circuit, the VCC drops to VCClatch and goes up to 15 V. The blue trace corresponds to the “ok to pulse” signal whose duration is given by the fault timer (purposely reduced on this simulation). Should a VCCOFF condition be detected, or a BOK fault, the duration would be accordingly truncated. Figure 36. http://onsemi.com 23 NCP1381 VCCON VCC VCCOFF VCClatch Timer Vin BO Interruption Short−Circuit Interruption Pulse OK UVLO Interruption BOK Comp. 50.0m 150m 250m 350m 450m A mix of conditions, BO, short−circuit and UVLO fault are represented on this diagram. In BO, the pulses (pulse ok signal) are started at VCC = 15 V and there is no latch−off phase. In short−circuit, pulses are stopped by the timer and finally, in a UVLO conditions (not a short−circuit), there is a latch−off phase but the timer is flat since there is no short−circuit. Figure 37. PFC Behavior During BO Conditions During brown−out, the PFC is disabled; otherwise the PFC controller consumption would prevent the charging of the VCC capacitor. The PFC will be shutdown until BO comes back and a clean startup sequence has properly ended. Soft−start VCC 15 V The NCP1381 features a soft−start activated during the power on sequence (PON) and in short−circuit conditions to lower the acoustical noise in the transformer. As soon as VCC reaches 15 V, the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 0.8 V / Rsense). Every restart attempt is followed by a soft−start activation. A shorter soft−start is also activated during the skip cycle condition to implement our soft−burst. This Soft−Skip is cancelled whenever a fault condition appears, in order not to degrade the transient behavior in case of load transients when the controller is initially in skip mode. 0 V (Fresh PON) or VCClatch Current Sense Max IP 5 ms Figure 38. Soft−Start is Activated During a Startup Sequence or an OCP Condition http://onsemi.com 24 NCP1381 ORDERING INFORMATION Device NCP1381DR2G Package SOIC−14 (Pb−Free) Shipping † 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 25 NCP1381 PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 1 7 G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). This device is covered by the following patents: 5,073,850 (Restart Timer), 6,362,067 (Self−aligned Resistors), 6,385,060 (Reduced Energy Transfer During Fault). US Patent Pending ONS00657 (Lower Power Voltage Detection Circuit) and ONS00698 (Power Supply Controller and Method). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 26 NCP1381/D