NCP1573

NCP1573 Low Voltage Synchronous Buck Controller The NCP1573 is a low voltage buck controller. It provides the control for a DC−DC power solution producing an output voltage as low as 0.980 V over a wide current range. The NCP1573−based solution is powered from 12 V with the output derived from a 2−7 V supply. It contains all required circuitry for a synchronous NFET buck regulator using the V2™ control method to achieve the fastest possible transient response and best overall regulation. NCP1573 operates at a fixed internal 200 kHz frequency and is packaged in an SO−8. This device provides Power Good with delay and built−in adaptive non−overlap. http://onsemi.com 8 1 SO−8 D SUFFIX CASE 751 • • • • • • • • • • • • Features 0.980 V ± 1.0% Reference Voltage V2 Control Topology 200 ns Transient Response Power Good Programmable Power Good Delay 40 ns Gate Rise and Fall Times (3.3 nF Load) Adaptive FET Non−Overlap Time Fixed 200 kHz Oscillator Frequency On/Off Control Through Use of the COMP Pin Overvoltage Protection through Synchronous MOSFETs Synchronous N−Channel Buck Design Dual Supply, 12 V Control, 2−7 V Power Source PIN CONNECTIONS AND MARKING DIAGRAM VCC PWRGD PGDELAY COMP A L Y W 1 1573 ALYW 8 GND VFB GATE(L) GATE(H) = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device NCP1573D NCP1573DR2 Package SO−8 SO−8 Shipping 98 Units/Rail 2500 Tape & Reel © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 4 1 Publication Order Number NCP1573/D NCP1573 12 V PWRGD VLOGIC R1 50 k GND 5.0 V 33 μF/8.0 V/1.6 Arms C1 NTD4302 Q1 GND VFB 2.7 μH 100 pF C6 L1 + + + + + + C4 0.47 μF C2 + C3 R4 10 2.5 V/10 A VCC PWRGD NCP1573 PGDELAY COMP C13 0.1 μF GATE(L) GATE(H) NTD4302 Q2 R5 3.3 k 5.1 k R3 C8 C9 C10 C11 GND C12 0.01 μF 56 μF/4.0 V/1.6 Arms SP−CAP 40 mΩ Figure 1. Applications Circuit MAXIMUM RATINGS* Rating Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Lead Temperature Soldering: Moisture Sensitivity Level Package Thermal Resistance, SO−8 Junction−to−Case, RθJC Junction−to−Ambient, RθJA 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. Reflow: (Note 1) Value 150 −65 to 150 2.0 230 peak 2 48 165 Unit °C °C kV °C − °C/W °C/W MAXIMUM RATINGS Pin Name IC Power Input Compensation Capacitor Voltage Feedback Input Power Good Output Power Good Delay High−Side FET Driver Low−Side FET Driver Ground Pin Symbol VCC COMP VFB PWRGD PGDELAY GATE(H) GATE(L) GND VMAX 15 V 6.0 V 6.0 V 15 V 6.0 V 15 V 15 V 0.5 V VMIN −0.5 V −0.5 V −0.5 V −0.5 V −0.5 V −0.5 V −2.0 V for 50 ns −0.5 V −2.0 V for 50 ns −0.5 V ISOURCE N/A 10 mA 1.0 mA 1.0 mA 1.0 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC 1.5 A Peak 450 mA DC ISINK 1.5 A Peak 450 mA DC 10 mA 1.0 mA 20 mA 10 mA 1.5 A Peak 200 mA DC 1.5 A Peak 200 mA DC N/A http://onsemi.com 2 NCP1573 ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 μF, CCOMP = 0.1 μF; unless otherwise specified.) Characteristic Error Amplifier VFB Bias Current COMP Source Current COMP Sink Current Reference Voltage COMP Max Voltage COMP Min Voltage Open Loop Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Output Transconductance Output Impedance GATE(H) and GATE(L) Rise Time Fall Time GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay Minimum Pulse Width High Voltage (AC) 1.0 V < GATE(L), GATE(H) < VCC − 2.0 V VCC − 2.0 V < GATE(L), GATE(H) < 1.0 V GATE(H) < 2.0 V, GATE(L) > 2.0 V GATE(L) < 2.0 V, GATE(H) > 2.0 V GATE(X) = 4.0 V Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2. Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2. Resistance to GND. Note 2. − − 40 40 − VCC − 0.5 40 40 60 60 250 VCC 80 80 100 100 − − ns ns ns ns ns V VFB = 0 V COMP = 1.5 V, VFB = 0.8 V COMP = 1.5 V, VFB = 1.2 V COMP = VFB TJ < 25°C VFB = 0.8 V VFB = 1.2 V − − − − − − 15 15 0.970 0.965 2.4 − − − − − − 0.2 30 30 0.980 0.980 2.7 0.1 98 20 70 32 2.5 2.0 60 60 0.990 0.995 − 0.2 − − − − − μA μA μA V V V V dB kHz dB mmho MΩ Test Conditions Min Typ Max Unit Low Voltage (AC) − 0 0.5 V GATE(H)/(L) Pull−Down Power Good Lower Threshold, VO Rising Lower Threshold, VO Falling PWRGD Low Voltage Delay Charge Current Delay Clamp Voltage Delay Charge Threshold “Good” Signal Delay 20 50 115 kΩ TJ < 25°C TJ < 25°C ISINK = 1.0 mA, VFB = 0 V PGDELAY = 2.0 V − Ramp PGDELAY, Monitor PWRGD With 0.01 μF. Note 2. 0.852 0.847 0.663 0.658 − 7.0 3.45 3.1 1.0 0.882 0.882 0.685 0.685 0.15 12 4.0 3.3 3.0 0.912 0.917 0.709 0.714 0.4 18 4.3 3.5 5.0 V V V V V μA V V ms 2. Guaranteed by design. Not tested in production. http://onsemi.com 3 NCP1573 ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 μF, CCOMP = 0.1 μF; unless otherwise specified.) Characteristic PWM Comparator PWM Comparator Offset Ramp Max Duty Cycle Artificial Ramp Transient Response VFB Input Range Oscillator Switching Frequency General Electrical Specifications VCC Supply Current COMP = 0 V (No Switching) − 10 15 mA − 150 200 250 kHz Duty Cycle = 50% COMP = 1.5 V, VFB 20 mV Overdrive. Note 3 Note 3 VFB = 0 V, Increase COMP Until GATE(H) Starts Switching − 0.475 − 15 − 0 0.525 80 25 200 − 0.575 − 35 300 1.4 V % mV ns V Test Conditions Min Typ Max Unit 3. Guaranteed by design. Not tested in production. PACKAGE PIN DESCRIPTION PACKAGE PIN # 1 2 3 4 5 6 7 8 PIN SYMBOL VCC PWRGD PGDELAY COMP GATE(H) GATE(L) VFB GND Power supply input. Open collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA. External capacitor programs PWRGD low−to−high transition delay. Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensation. Pulling pin < 0.475 V locks gate outputs to a zero percent duty cycle state. High−side switch FET driver pin. Capable of delivering peak currents of 1.5 A. Low−side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A. Error amplifier and PWM comparator input. Power supply return. FUNCTION http://onsemi.com 4 NCP1573 GND VCC VFB − + + − 0.980 V S Reset Dominant COMP 0.525 V −+ Σ Art Ramp 80%, 200 kHz 0.25 V + − OSC Error Amp − + PWM COMP PWM Latch R Q Non Overlap GATE(L) GATE(H) VCC + − 12 μA PGDELAY − + + − 0.88 V/0.69 V PGDELAY Latch S Q + − − + 3.3 V PWRGD R Set Dominant Figure 2. Block Diagram http://onsemi.com 5 NCP1573 TYPICAL PERFORMANCE CHARACTERISTICS 10 Oscillator Frequency (kHz) 20 40 60 80 Temperature (°C) 100 120 9 216 214 212 210 208 206 204 202 0 20 40 60 80 Temperature (°C) 100 120 ICC (mA) 8 7 6 5 0 Figure 3. Supply Current vs. Temperature Figure 4. Oscillator Frequency vs. Temperature 0.984 0.983 Reference Voltage (V) Ramp Amplitude (mV) 0 20 40 60 80 Temperature (°C) 100 120 0.982 0.981 0.980 0.979 0.978 0.977 0.976 27 26 25 24 23 22 21 20 0 20 40 60 80 Temperature (°C) 100 120 Figure 5. Reference Voltage vs. Temperature Figure 6. Artificial Ramp Amplitude vs. Temperature (50% Duty Cycle) 540 0.60 PWM Offset Voltage (mV) 535 Bias Current (μA) 0 0.55 530 0.50 525 0.45 520 20 40 60 80 Temperature (°C) 100 120 0.40 0 20 40 60 80 Temperature (°C) 100 120 Figure 7. PWM Offset Voltage vs. Temperature Figure 8. VFB Bias Current vs. Temperature http://onsemi.com 6 NCP1573 TYPICAL PERFORMANCE CHARACTERISTICS 31 30 Output Current (μA) Sink Current COMP Voltages (V) 29 28 27 Source Current 26 25 24 0 20 40 60 80 Temperature (°C) 100 120 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 COMP Fault Threshold Voltage 60 80 Temperature (°C) 100 120 COMP Minimum Voltage COMP Maximum Voltage Figure 9. Error Amp Output Currents vs. Temperature Figure 10. COMP Voltages vs. Temperature 38 Gate Non−Overlap Time (ns) 36 GATE Rise/Fall Times (ns) 34 32 30 28 26 24 22 20 0 20 40 60 80 Temperature (°C) 100 120 GATEL Fall Time GATEL Rise Time GATEH Fall Time GATEH Rise Time 55 50 GATEH to GATEL Delay Time 45 40 35 30 GATEL to GATEH Delay Time 0 20 40 60 80 Temperature (°C) 100 120 Figure 11. GATE Output Rise and Fall Times vs. Temperature Figure 12. GATE Non−Overlap Times vs. Temperature 1000 PWRGD Threshold Voltages (mV) PWRGD Low Voltage (mV) 120 Turn−On Threshold, VFB Rising 70 65 60 55 50 45 40 900 800 700 Turn−Off Threshold, VFB Falling 600 0 20 40 60 80 Temperature (°C) 100 0 20 40 60 80 Temperature (°C) 100 120 Figure 13. PWRGD Thresholds vs. Temperature Figure 14. PWRGD Output Low Voltage vs. Temperature http://onsemi.com 7 NCP1573 TYPICAL PERFORMANCE CHARACTERISTICS 13.4 13.1 12.8 12.5 12.2 11.9 11.6 PGDELAY Discharge Current (mA) 0 20 40 60 80 Temperature (°C) 100 120 PGDELAY Charge Current (μA) 1.45 1.40 1.35 1.30 1.25 1.20 1.15 0 20 40 60 80 Temperature (°C) 100 120 Figure 15. PGDELAY Charge Current vs. Temperature Figure 16. PGDELAY Discharge Current vs. Temperature 259 Discharge Threshold Voltage (mV) 4.00 3.90 PGDELAY Max Voltage 257 PGDELAY Voltages (V) 3.80 3.70 3.60 3.50 3.40 3.30 255 253 PGDELAY Upper Threshold Voltage 251 0 20 40 60 80 Temperature (°C) 100 120 3.20 0 20 40 60 80 Temperature (°C) 100 120 Figure 17. PGDELAY Discharge Threshold Voltage vs. Temperature Figure 18. PGDELAY Voltages vs. Temperature http://onsemi.com 8 NCP1573 APPLICATION INFORMATION THEORY OF OPERATION The NCP1573 is a simple, synchronous, fixed−frequency, low−voltage buck controller using the V2 control method. It provides a programmable−delay Power Good function to indicate when the output voltage is out of regulation. The V2 control method uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current. − + VIN VCOMP 0.5 V VFB V2 Control Method GATE(H) STARTUP NORMAL OPERATION tS Figure 20. Idealized Waveforms PWM GATE(H) GATE(L) RAMP Slope Compensation COMP Error Signal Output Voltage Error Amplifier − + VFB Reference Voltage Figure 19. V2 Control with Slope Compensation The V2 control method is illustrated in Figure 19. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch from 0% to 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage http://onsemi.com 9 NCP1573 to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity, particularly at duty cycles above 50%. Start Up PWRGD High The NCP1573 features a programmable Soft Start function, which is implemented through the error amplifier and the external compensation capacitor. This feature prevents stress to the power components and limits output voltage overshoot during start−up. As power is applied to the regulator, the compensation capacitor connected to the COMP pin is charged by a 30 μA current source. When the capacitor voltage exceeds the 0.525 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated, turning on the upper MOSFET. The current ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the 0.525 V PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse. Normal Operation Low VOUT 70% 90% Percent of Designed VOUT Figure 21. PWRGD Assertion Overvoltage Protection During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation. Input Supplies Overvoltage protection is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage, preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases. Power Good The NCP1573 can be used in applications where a 12 V supply is available along with a lower voltage supply. Often the lower voltage supply is 5 V, but it can be any voltage less than the 12 V supply minus the required gate drive voltage of the top MOSFET. The greater the difference between the two voltages, the better the efficiency due to increasing VGS available to turn on the upper MOSFET. In order to maintain power supply stability, the lower supply voltage should be at least 1.5 times the desired voltage. A lower supply voltage between 2−7 V is recommended. Gate Charge Effect on Switching Times The PWRGD pin is asserted when the output voltage is within regulation limits. Sensing for the PWRGD pin is achieved through the VFB pin. When the output voltage is rising, PWRGD goes high at 90% of the designed output voltage. When the output voltage is falling, PWRGD goes low at 70% of the designed output voltage. PWRGD is an open−collector output and should be externally pulled to logic high through a resistor to limit current to no more than 20 mA. Figure 21 shows the hysteretic nature of the PWRGD pin’s operation. CONVERTER DESIGN Selection of the Output Capacitors When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading. Transient Response The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse−by−pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, several high frequency and bulk output capacitors are usually used. These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: DVOUT + DIOUT ESL ) ESR ) tTR Dt COUT http://onsemi.com 10 NCP1573 where: ΔIOUT / Δt = load current slew rate; ΔIOUT = load transient; Δt = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula: DVESR ESRMAX + DIOUT bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore: LIN + DV (dI dt)MAX where: LIN = input inductor value; ΔV = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double−pole network with a slope of −2.0, a roll−off rate of −40 dB/dec, and a corner frequency: fC + 1 2p LC where: ΔVESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: Number of capacitors + ESRCAP ESRMAX where: L = input inductor; C = input capacitor(s). Selection of the Output Inductor where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: DVESR + DIOUT ESRMAX Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX + DVESL DI Dt Selection of the Input Inductor A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input There are many factors to consider when choosing the output inductor. Maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. However, the most important consideration may be the effect inductor value has on transient response. The amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor ESR. Choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice−versa. In the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade−off of ripple current vs. transient response. In order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. Most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify VIN(MAX) or VIN(MIN), it is possible to use the nominal value of VIN in these calculations with little error. Current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current. IL + ILOAD ) IRIPPLE The ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch FET on−time and the inductor value. FET on−time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of VOUT to VIN. Thus, http://onsemi.com 11 NCP1573 IRIPPLE + (VIN * VOUT)VOUT (fOSC)(L)(VIN) Ra for an inductor designed to conduct 20 A to 30 A is approximately 45°C/W. The inductor temperature is given as: T(inductor) + DT(inductor) ) Tambient VCC Bypass Filtering Peak inductor current is defined as the load current plus half of the peak current. Peak current must be less than the maximum rated FET switch current, and must also be less than the inductor saturation current. Thus, the maximum output current can be defined as: IOUT(MAX) + ISWITCH(MAX) * VIN(MAX) * VOUT VOUT 2 fOSC L VIN(MAX) Since the maximum output current must be less than the maximum switch current, the minimum inductance required can be determined. L(MIN) + (VIN(MIN) * VOUT)VOUT (fOSC)(ISWITCH(MAX))(VIN(MIN)) A small RC filter should be added between module VCC and the VCC input to the IC. A 10 Ω resistor and a 0.47 μF capacitor should be sufficient to ensure the controller IC does not operate erratically due to injected noise, and will also supply reserve charge for the onboard gate drivers. Input Filter Capacitors The input filter capacitors provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch FETs. These capacitors must be chosen primarily for ripple current rating. VIN LIN IIN(AVE) IRMS(CIN) CIN CONTROL INPUT This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. Some value larger than the minimum inductance must be used to ensure the converter does not sink current. Choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing ISWITCH(MAX) with a desired value of IRIPPLE: (VIN(MIN) * VOUT)VOUT L(RIPPLE) + (fOSC)(IRIPPLE)(VIN(MIN)) LOUT VOUT COUT Figure 22. Consider the schematic shown in Figure 22. The average current flowing in the input inductor LIN for any given output current is: IIN(AVE) + IOUT VOUT VIN However, reducing the ripple current will cause transient response times to increase. The response times for both increasing and decreasing current steps are shown below. TRESPONSE(INCREASING) + (L)(DIOUT) (VIN * VOUT) (L)(DIOUT) (VOUT) TRESPONSE(DECREASING) + Inductor value selection also depends on how much output ripple voltage the system can tolerate. Output ripple voltage is defined as the product of the output ripple current and the output filter capacitor ESR. Thus, output ripple voltage can be calculated as: VRIPPLE + ESRC IRIPPLE + ESRC VIN * VOUT VOUT fOSC L VIN Input capacitor current is positive into the capacitor when the switch FETs are off, and negative out of the capacitor when the switch FETs are on. When the switches are off, IIN(AVE) flows into the capacitor. When the switches are on, capacitor current is equal to the per−phase output current minus IIN(AVE). If we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. We can then calculate the RMS input capacitor ripple current: IRMS(CIN) + VOUT I2 IN(AVE) ) V IN IOUT per phase * IIN(AVE) 2 * I 2 IN(AVE) Finally, we should consider power dissipation in the output inductors. Power dissipation is proportional to the square of inductor current: PD + (I 2)(ESRL) L The temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient: DT(inductor) + (Ra)(PD) The input capacitance must be designed to conduct the worst case input ripple current. This will require several capacitors in parallel. In addition to the worst case current, attention must be paid to the capacitor manufacturer’s derating for operation over temperature. As an example, let us define the input capacitance for a 5 V to 3.3 V conversion at 10 A at an ambient temperature of 60°C. Efficiency of 80% is assumed. Average input current in the input filter inductor is: http://onsemi.com 12 NCP1573 IIN(AVE) + (10 A)(3.3 V 5 V) + 6.6 A PON(BOTTOM) + RDS(ON)(BOTTOM) IRMS(BOTTOM) 2 number of bottom−side FETs Input capacitor RMS ripple current is then IIN(RMS) + 6.62 ) 3.3 V 5V [(10 A * 6.6 A)2 * 6.6 A2] + 4.74 A where: n = number of phases. Note that RDS(ON) increases with temperature. It is good practice to use the value of RDS(ON) at the FET’s maximum junction temperature in the calculations shown above. IRMS(TOP) + I 2 * (IPK)(IRIPPLE) ) D I 2 PK 3 RIPPLE (1 * D) 2 I RIPPLE 3 If we consider a Rubycon MBZ series capacitor, the ripple current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at 100 kHz and 105°C. We determine the number of input capacitors by dividing the ripple current by the per−capacitor current rating: Number of capacitors + 4.74 A 2.0 A + 2.3 IRMS(BOTTOM) + I 2 * (IPKIRIPPLE) ) PK A total of at least 3 capacitors in parallel must be used to meet the input capacitor ripple current requirements. Output Switch FETs Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The NCP1573 system is designed assuming that n−channel FETs will be used. The FET characteristics of most concern are the gate charge/gate−source threshold voltage, gate capacitance, on−resistance, current rating and the thermal capability of the package. The onboard FET driver has a limited drive capability. If the switch FET has a high gate charge, the amount of time the FET stays in its ohmic region during the turn−on and turn−off transitions is larger than that of a low gate charge FET, with the result that the high gate charge FET will consume more power. Similarly, a low on−resistance FET will dissipate less power than will a higher on−resistance FET at a given current. Thus, low gate charge and low RDS(ON) will result in higher efficiency and will reduce generated heat. It can be advantageous to use multiple switch FETs to reduce power consumption. By placing a number of FETs in parallel, the effective RDS(ON) is reduced, thus reducing the ohmic power loss. However, placing FETs in parallel increases the gate capacitance so that switching losses increase. As long as adding another parallel FET reduces the ohmic power loss more than the switching losses increase, there is some advantage to doing so. However, at some point the law of diminishing returns will take hold, and a marginal increase in efficiency may not be worth the board area required to add the extra FET. Additionally, as more FETs are used, the limited drive capability of the FET driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. This will affect the amount of time the FET operates in its ohmic region and will increase power dissipation. The following equations can be used to calculate power dissipation in the switch FETs. For ohmic power losses due to RDS(ON): PON(TOP) + (RDS(ON)(TOP))(IRMS(TOP))2 (number of topside FETs) http://onsemi.com 13 NCP1573 IRIPPLE + (VIN * VOUT)(VOUT) (fOSC)(L)(VIN) I I I IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE 2 3 2 where: D = Duty cycle. For switching power losses: PD + nCV2(fOSC) where: n = number of switch FETs (either top or bottom), C = FET gate capacitance, V = maximum gate drive voltage (usually VCC), fOSC = switching frequency. System Considerations for the NCP1573 The NCP1573 controller is optimized for converter designs where the power supply for the controller IC has very short turn−on and turn−off times. Such systems can be found providing power to graphics cards or memory where standby power is also provided. The key features of the NCP1573 are that undervoltage lockout and soft start resetting are not included. These features must be absent to allow the NCP1573 to interface in a glitch−free manner with back−up power supplies. A schematic showing a possible system implementation using the NCP1573 is included in Figure 23. Note that an PWRGD 12 V GND external p−channel FET gates the 12 V supply to the IC. The signal also controls an alternate supply that drives a linear regulator. The linear regulator provides back−up power for the load during low−power operation. In this case, the 12 V supply turn−on and turn−off is so fast that the controller does not charge or discharge the output capacitance significantly during the transition intervals. This minimizes glitching during the transitions. Also, note that a resistor divider and a diode connect the logic signal to the COMP pin of the NCP1573. The divider and diode network serve to hold the COMP voltage up when the IC is powered down. When the power management state changes and the IC powers back up, having the COMP voltage at its correct level further reduces glitching. The correct COMP level is determined to be the IC reference voltage (0.98 V) plus the channel start−up offset of the controller (0.525 V), plus about 10 mV to account for artificial ramp amplitude (total of 1.615 V). The divider voltage must be about 100 mV higher to allow for the diode forward voltage. Note that very little current is assumed to flow through the diode since only capacitor leakage current should be present. There will always be some small voltage adjustment during transitions due to manufacturing tolerances. Having the COMP voltage slightly low will result in a temporary sag in the output voltage as the linear regulator turns off and the switching supply turns on. Similarly, a positive change in VOUT will occur if the COMP voltage is slightly too high. 5V 3 U2 CS5201 VIN VOUT ADJUST R8 1.25 k R9 1.25 k Q4 NTMS10P02R2 2.5 V 1 R11 10 k Q3 NTMS10P02R2 R1 47 k U1 1 2 3 VCC PWRGD GND VFB 8 7 6 5 VFB LDO_ON_3.3 R5 16.9 k D1 1N5817 R7 16.2 k C6 100 pF 2 Rubycon MBZ C1 + 1800 μF C2 + 1800 μF R10 10 k R3 10 C4 0.1 μF Q5 MGSF1N02ELT1 Q1 MTB1306 SWN L1 2.7 μH 5V PGDELAY GATEL COMP GATEH R4 Q2 5.1 k MTB1306 R6 3.3 k + C12 0.01 μF C13 0.1 μF 4 C8 + 1800 μF C9 1800 μF NCP1573 Rubycon MBZ Q6 MGSF1N02ELT1 Figure 23. http://onsemi.com 14 NCP1573 Providing fast turn−on and turn−off edges to the IC power is very important in minimizing glitching because there is no undervoltage lockout circuitry. For example, if the switcher were powered up and regulating, and the supply began to decrease slowly, the GATE outputs of the IC would continue to switch until the driver circuitry ran out of headroom (when VCC reaches approximately 5 V). When the drivers collapse, an on−chip resistor from the GATE pins to ground will bottom the external n−channel FETs and the switch node becomes disconnected from the DC−DC converter. Until this happens, it is entirely possible that the bottom FET may have a large duty cycle and be trying to discharge the VOUT capacitance. Additionally, as the bias circuitry in the IC collapses, the reference voltage to the error amplifier may change and result in false regulation. The circuit in Figure 23 will operate properly with turn−on and turn−off times on the order of 500 μs or faster. 12 V VCC 12 V VCC VOUT COMP VOUT COMP Figure 24. Output Transient with COMP Voltage Positioned 100 mV Too High Figure 25. Output Transient with COMP Voltage Positioned 100 mV Too Low http://onsemi.com 15 NCP1573 Layout Considerations 1. The fast response time of V2 technology increases the IC’s sensitivity to noise on the VFB line. Fortunately, a simple RC filter, formed by the feedback network and a small capacitor (100 pF works well, shown below as C6) placed between VFB and GND, filters out most noise and provides a system practically immune to jitter. This capacitor should be located as close as possible to the IC. 2. The COMP capacitor (shown below as C13) should be connected via its own path to the IC ground. The COMP capacitor is sensitive to the intermittent ground drops caused by switching currents. A separate ground path will reduce the potential for jitter. 3. The VCC bypass capacitor (0.1 μF or greater, shown below as C4) should be located as close as possible to the IC. This capacitor’s connection to GND must be as short as possible. The 10 Ω resistor (shown below as R3) should be placed close to the VCC pin. 4. The IC should not be placed in the path of switching currents. If a ground plane is used, care should be taken by the designer to ensure that the IC is not located over a ground or other current return path. R4 VOUT R6 C6 C4 R3 U1 R1 GND 12 V PWRGD C13 C12 5V Figure 26. http://onsemi.com 16 NCP1573 PACKAGE DIMENSIONS SO−8 D SUFFIX CASE 751−07 ISSUE W −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S V2 is a trademark of Switch Power, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 17 NCP1573/D