NCP1581
High Frequency Synchronous
Step Down PWM Controller
for Tracking Applications
The NCP1581 controller IC is designed to provide a simple
synchronous buck regulator for on−board DC to DC applications in a
14−pin SOIC. The NCP1581 is designed specifically for tracking
applications by providing the track input.
The NCP1581 operates at a fixed internal 400 kHz switching
frequency allowing the use of small external components. The device
features a programmable soft start set by an external capacitor,
under−voltage lockout and output under−voltage detection that latches
off the device when an output short is detected.
Features
•
•
•
•
•
•
•
Power up Sequencing / Tracking
Enable Input
Internal 400 kHz Oscillator
Programmable Soft−Start
Fixed Frequency Voltage Mode
Voltage Mode Adaptive Deadtime
This is a Pb−Free Device
14
1
A
WL
Y
WW
G
MARKING
DIAGRAM
SOIC−14
D SUFFIX
CASE 751A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
NCP1581G
AWLYWW
1
PIN CONNECTIONS
FB
Applications
•
•
•
•
•
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Tracking Applications
Game Consoles
Computing Peripheral Voltage Regulators
Graphics Cards
General DC to DC Converters
1
NC
VP
SS
NC
COMP
VCC
NC
NC
VC
LDRV
HDRV
GND
PGND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
NCP1581
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 0
1
Publication Order Number:
NCP1581/D
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2
Figure 2. Simplified Block Diagram
COMP
FB
VP/EN
SS
GND
VCC
2 2 uA
25k
25k
V BIAS
POR
Error Amp
64uA Max
0.65V
VP/EN
POR
V CC UVLO
0.4V
Error
Comparator
CT
Oscillator
R
S
Q
S
R
Reset Dom
POR
POR
Q
POR
PWM
2V
SS
FAULT
FAULT
Delay
2V
2V
Delay
VCC
PGND
LDRV
HDRV
VC
NCP1581
Circuit Description:
Block Diagram
NCP1581
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Description
1
FB
Inverting input to the error amplifier. This pin is connected to the output of the regulator via resistor divider
to set the output voltage and provide feedback to the error amplifier.
2
VP/EN
3
NC
4
VCC
5
NC
6
LDRV
Output driver for low side MOSFET.
7
GND
IC ground for internal control circuitry.
8
PGND
Power Ground. This pin serves as a separate ground for the MOSFET drivers and should be connected to
the system’s power ground plane.
9
HDRV
Output driver for high side MOSFET. The negative voltage at this pin may cause instability for the gate
drive circuit. To prevent this, a low forward voltage drop diode (e.g. BAT54 or 1N4148) is required
between this pin and Power Ground.
10
VC
This pin powers the high side driver.
11
NC
No Connect
12
COMP
13
SS
Soft start. This pin provides user programmable soft−start function. Connect an external capacitor from
this pin to ground to set the start up time of the output voltage.
14
NC
No Connect
Dual function pin. Non inverting input to the error amplifier. Enable input.
No Connect
This pin provides power for the internal blocks of the IC as well as powers the low side driver. A minimum
of 0.1 mF, high frequency capacitor must be connected from this pin to power ground.
No Connect
Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to
ground to provide loop compensation.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Main Supply Voltage Input
Main Supply Voltage Input
200 ns wide spikes, 400 kHz
Supply Voltage for the High side driver
Supply Voltage for the High side driver 200 ns wide spikes, 400 kHz
VP/EN pin Voltage
FB pin Voltage
Rating
Symbol
min
max
Unit
VCC
−0.3
20
V
VCC_SPK
−0.3
22
V
VC
−0.3
20
V
VC_SPK
−0.3
22
V
VP/EN
−0.3
10 or VCC (Note 1)
V
VFB
−0.3
10 or VCC (Note 1)
V
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient (Note 2)
Rthja
90
K/W
Storage Temperature Range
Tstg
−65 to 150
°C
Junction Operating Temperature
TJ
0 to 150
°C
ESD Withstand Voltage (Note 3)
Human Body Model
Machine Model
VESD
2.0
200
kV
V
Moisture Sensitivity Level
MSL
JEDEC Level 1 @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: All voltages are referenced to GND pin unless otherwise stated.
1. Maximum = 10 V or VCC, whichever is lower.
2. JEDEC High−K model
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115
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NCP1581
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
Definition
Min
Max
Units
VCC
Supply Voltage
7
20
V
VC
Supply Voltage
Converter Voltage + 5 V, (Note 4)
20
V
TJ
Junction Temperature
0
125
°C
NOTE: All voltages are referenced to GND pin.
4. Depend on high side MOSFET VGS
Table 4. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0°C < TJ < 125°C
Parameter
Symbol
Test Condition
ICC(Static)
Min
Typ
Max
Units
VP/EN = 0 V, No Switching
1.5
3
mA
ICC(Dynamic)
fSW = 400 kHz, CL = 1.5 nF
10
15
mA
IC(Static)
VP/EN = 0 V, No Switching
0.05
0.1
mA
IC(Dynamic)
fSW = 400 kHz, CL = 1.5 nF
9
15
mA
VCC−Start−Threshold
VCC UVLO (R)
Supply voltage Rising
6.3
6.6
7.0
V
VCC−Stop−Threshold
VCC UVLO (F)
Supply voltage Falling
6.0
6.3
6.6
V
VCC (Hyst)
Supply ramping up and down
0.2
0.3
0.4
V
Enable−Start−Threshold
VP/EN UVLO (R)
Supply voltage Rising
0.6
0.65
0.7
V
Enable−Stop−Threshold
VP/EN UVLO (F)
Supply voltage Falling
0.56
0.6
0.66
VP/EN (Hyst)
Supply ramping up and down
VFB UVLO
FB ramping down
SUPPLY CURRENT
VCC Supply Current (Static)
VCC Supply Current (Dynamic)
VC Supply Current (Static)
VC Supply Current (Dynamic)
UNDER VOLTAGE LOCKOUT
VCC−Hysteresis
Enable−Hysteresis
FB UVLO
40
V
mV
0.3
0.4
0.5
V
370
400
430
kHz
OSCILLATOR
Frequency
Ramp Amplitude
fSW
VRAMP
(Note 5)
Min Duty Cycle
DMIN
VFB =1V, VP/EN = 0.8 V
Max Duty Cycle
DMAX
fSW = 400 kHz, VFB = 0.6 V, VP/EN = 0.8 V
FB Input Bias Current
IFB1
FB Input Bias current
1.25
V
0
%
85
95
%
VSS = 3 V
−0.1
−0.5
mA
IFB2
VSS = 0 V
64
IVP/EN
VSS = 3 V
−0.1
83
ERROR AMPLIFIER
VP/EN Input Bias Current
Transconductance
gm
Input Offset Voltage
VOS
VP/EN = 0.8 V, VCOMP = 2.0 V
−6
VCOMN
(Note 5)
0.6
VP/EN Common Mode Range
440
0
mA
−0.5
mA
1300
mmho
+6
mV
1.5
V
ERROR AMPLIFIER DESIGN SPECIFICATIONS
OTA output current
IOTA (SINK)
VFB = 1.2 V, VP/EN = 1.0 V,
VCOMP = 2.0 V, (Note 5)
100
mA
OTA output current
IOTA (SOURCE)
VFB = 0.8 V, VP/EN = 1.0 V,
VCOMP = 2.0 V, (Note 5)
100
mA
5. Guaranteed by Design but not tested in production.
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NCP1581
Table 5. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0°C < TJ < 125°C
Symbol
Test Condition
Min
Typ
Max
Units
Soft Start Current
ISS
VSS = 0 V
12
22
32
mA
Soft Start Turn On
SS (on)
1.8
2
2.2
V
Parameter
SOFT START
OUTPUT DRIVERS
LO Drive Rise Time
tr(Lo)
CL = 1.5 nF (See Figure 3)
20
50
ns
HI Drive Rise Time
tr(Hi)
CL = 1.5 nF (See Figure 3)
30
60
ns
LO Drive Fall Time
tf(Lo)
CL = 1.5 nF (See Figure 3)
20
50
ns
HI Drive Fall Time
tf(Hi)
CL = 1.5 nF (See Figure 3)
30
60
ns
Dead Band Time
tDEAD
(See Figure 3)
45
90
ns
Adaptive DBT Level
VADT
tr(Hi)
35
2.0
tf(Hi)
9V
High Side Driver
(HDRV)
tDEAD
tDEAD
2V
tr(Lo)
tf(Lo)
9V
Low Side Driver
(LDRV)
2V
Figure 3. Definition of Rise/Fall Time and Deadband Time
TYPICAL CHARACTERISTICS
7.00
6.90
6.80
VCC (V)
6.70
Rising
6.60
6.50
6.40
6.30
Falling
6.20
6.10
6.00
0
20
40
60
80
TEMPERATURE (°C)
Figure 4. VCC UVLO
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5
100
120
V
NCP1581
TYPICAL CHARACTERISTICS
0.50
0.70
0.48
0.68
0.46
Rising
0.44
0.64
VFB (V)
VP/EN (V)
0.66
Falling
0.62
0
20
40
60
80
100
0.32
0.30
120
40
60
80
Figure 5. VP/EN UVLO
Figure 6. FB UVLO
440
93
430
100
120
100
120
420
fSW (kHz)
89
87
85
410
400
390
380
83
370
0
20
40
60
80
100
360
120
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Maximum Duty Cycle
Figure 8. Switching Frequency
1300
90
1200
80
1100
70
1000
t (ns)
900
800
Low to High
60
High to Low
50
700
600
40
500
400
20
TEMPERATURE (°C)
95
81
0
TEMPERATURE (°C)
91
DMAX (%)
0.38
0.34
0.58
gm (mmho)
0.40
0.36
0.60
0.56
0.42
0
20
40
60
80
100
30
120
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Error Amplifier Transconductance
Figure 10. Deadtime
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100
120
NCP1581
Detailed Description
Introduction
The value of the output capacitor should be calculated
using the following equation:
The NCP1581 is voltage mode PWM synchronous
controller designated to drive two external N-channel
MOSFETs. Switching frequency is fixed at 400 kHz. Output
voltage is determined by feedback resistor divider and
external reference voltage. Reference voltage input can be
used to enabling and disabling operation and for tracking
function.
C OUT w
The undervoltage lockout circuit ensures that the IC does
not start and work until VCC and VP/EN are over set
thresholds. If these conditions are not fulfilled output drivers
are in the off state.
Input Capacitor Selection
The input capacitor is used to supply current pulses while
the high side MOSFET is on. When the MOSFET is off, the
input capacitor is being charged. The value of this capacitor
can be selected with the Equation (4):
Disable Function
The output voltage can be disabled by pulling the VP/EN
pin below 0.6 V. At this time are output drivers in the off
state.
I OUT @
C IN w
Output Voltage
Ǔ
(eq. 1)
Ǔǒ
1*
V OUT
V INmax
Ǔ
Ǔ
VOUT
VIN
(eq. 4)
Ǹ
ǒ
Ǔ
VOUT
V IN
(eq. 5)
V IN
Power MOSFET Selection
The NCP1581 uses two N-channel MOSFETs. They can
be primarily selected according to RDS(ON), maximum drain
to source voltage, and gate charge. RDS(ON) impacts
conductive losses and gate charge impacts switching losses.
The low side MOSFET is selected primarily for conduction
losses, and the high side MOSFET is selected to reduce
switching losses especially when the output voltage is less
than 30% of the input voltage. The drain to source
breakdown voltage must be higher than the maximum input
voltage. Conductive power losses can be calculated using
the following Equations (6) and (7):
The inductor selection is based on the output power,
frequency, input and output voltages, and efficiency
requirements. High inductor values cause low current
ripple, slower transient response, higher efficiency and
increased size. Inductor design can be reduced to desired
maximum current ripple in the inductor. It is good to have
current ripple (DILmax) between 20% and 50% of the output
current.
For a buck converter, the inductor should be chosen
according to Equation (2).
V OUT
f SW @ DI Lmax
ǒ
@ 1*
f SW @ DV IN
I RMS + I OUT @
Inductor Selection
ǒ
VIN
V OUT @ 1 *
where VP/EN is the external reference voltage at VP/EN pin
that is connected to noninverting input of error amplifier. R1
and R2 resistors create voltage divider from output to FB pin
that is connected to inverting input of error amplifier.
Absolute values of resistors R1 and R2 depend on the
compensation network type. See discussion of
compensation description for details.
L+
VOUT
where DVIN is the input voltage ripple and the
recommended value is about 2–5% of VIN. The input
capacitor must be able to handle the input ripple current. Its
value should be calculated using Equation (5):
Output voltage can be set by an external resistor divider
and external reference voltage at VP/EN pin according to
Equation (1):
ǒ
(eq. 3)
For a higher switching frequency, it is suitable to use a
multilayer ceramic capacitor (MLCC) with very low ESR.
The advantages are small size, low output voltage ripple and
fast transient response. The disadvantage of the MLCC type
is the requirement to use a Type III compensation network.
Under-Voltage Lockout
V OUT + V PńEN @ 1 ) R1
R2
DI L
8 @ f SW @ (DV OUT * DI L @ ESR)
P COND−HIGHFET + I OUT 2 @ R DS(ON) @
ǒ
P COND−LOWFET + I OUT 2 @ R DS(ON) @ 1 *
(eq. 2)
V OUT
(eq. 6)
V IN
Ǔ
V OUT
V IN
(eq. 7)
Switching losses are dependent on the drain to source
voltage at turn-off state, output current, and switch-on and
switch-off times, as is shown by Equation (8).
Output Capacitor Selection
The output voltage ripple and transient requirements
determine the output capacitor type and value. The
important parameter for the selection of the output capacitor
is equivalent serial resistance (ESR). If the capacitor has low
ESR, it often has sufficient capacity for filtering as well as
an adequate RMS current rating.
P SW +
V DS(OFF)
2
@ (t ON ) t OFF) @ f SW @ I OUT
(eq. 8)
tON and tOFF times are dependent on the transistor gate
charge.
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NCP1581
that of the body diode, and reverse recovery time (trr) should
be lower then that of the body diode. The Schottky diode’s
capacitance loss can be calculated as shown in
Equation (11).
The MOSFET output capacitance loss is caused by the
charging and discharging during the switching process and
can be computed using Equation (9).
P COSS +
C OSS @ V IN 2 @ f SW
2
(eq. 9)
P C(schottky) +
where COSS = CDS + CGS.
Some power dissipation is caused by the reverse recovery
charge in the low side MOSFET body diode, which conducts
at dead time. This charge is needed to close the diode. The
current from the input power supply flows through the high
side MOSFET to the low side MOSFET body diode. This
power dissipation can be calculated using the following
Equation (10):
P QRR + Q RR @ V IN @ f SW
C schottky @ V IN 2 @ f SW
2
(eq. 11)
Adaptive Deadtime
The NCP1581 includes voltage mode adaptive dead time
feature. This block waits for full turn off of the one of
MOSFETs before the second one can be turned on.
Detection is based on driver voltage, when this voltage drops
below VADT second driver can be turned on. There is fixed
time tDEAD between turn off detection and internal logical
turn on signal that increase safety. There can’t be used
additional gate resistors due to voltage base detection,
because these resistors would create voltage divider with
driver’s pull down transistor and correct turn off detection
is impossible. Gate resistors may be used only if MOSFETs
turn off time is at all operation conditions shorter than
tDEAD. MOSFETs’ timing diagram can be seen at Figure 11.
(eq. 10)
QRR is the diode recovery charge as given in the
manufacturer’s datasheet. For some types of MOSFETs, this
dissipation may be dominant at high input voltages. It is
necessary to take care when selecting a MOSFET. An
external Schottky diode across the low side MOSFET can be
used to eliminate the reverse recovery charge power loss.
The Schottky diode’s forward voltage should be lower than
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NCP1581
tDEAD
tDEAD
High Side
Logic
Signal
Low Side
Logic
Signal
HDRV
VADT
LDRV
VADT
t d (on )
tf
R DSmax
High Side
MOSFET
R DS
R DS (ON )min
tr
t d (off )
tf
tr
R DSmax
Low Side
MOSFET
R DS
R DS (ON )min
t d (on )
t d (off)
Figure 11. MOSFETs Timing Diagram
Soft Start
means that the NCP1581 is in a shutdown state. The SS pin
voltage (0 V to 2 V) controls the internal current source
(64 mA to 0 mA) with a negative linear characteristic. This
current source injects current into the resistor (25 kW)
connected between the FB pin and the negative input of the
error amplifier and into the external feedback resistor
network. Voltage drop on these resistors is over 1.6 V, which
is enough to force the error amplifier into a negative
saturation state and to block switching.
The soft start time is set by a capacitor connected between
the SS pin and ground. This function is used for controlling
the output voltage slope and limiting start-up currents. The
start-up sequence initiates when the Power On Ready (POR)
internal signal rises to logic level high. That means the
supply voltage and VP/EN voltage are over the set thresholds.
The soft start capacitor is charged by a 22 mA current source.
If POR is low, the SS pin is internally pulled to GND, which
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NCP1581
The soft start time must be at least 10 times longer than the
time needed to charge the compensation network from the
output of the error amplifier. If the soft start time is not long
enough, the soft start sequence would be faster than the
charging compensation network and the IC would start
without slowly increasing the output voltage. The soft start
capacitance can be calculated using Equation 12:
When the soft start pin reaches around 1.2 V (exact value
depends on feedback and compensation network and on the
soft start capacitor; a larger soft start capacitor and a lower
compensation capacity decrease this level), the IC starts
switching. The impact of the controlled current source
decreases and the output voltage starts to rise. When the soft
start capacitor voltage reaches 2 V, the output voltage is at
nominal value.
C SS + 22 @ 10 −6 @ T SS
(eq. 12)
VCC = VC
VIN
VP_EN
POR
3V
2V
VSS
1V
0V
VOUT
64 mA
Internal IFB
Vneg_error_amp
>1.6 V
VP/EN
VP/EN
VFB
0V
Figure 12. Start-up Sequence
Start to Pre-biased Output
The NCP1581 is able to start up into a pre-biased output
capacitor. The low side MOSFET does not turn on before the
output voltage is at set value. During this time, the energy is
not discharged by the low side MOSFET (current flows
through low side MOSFET body diode) until the soft start
sequence ends.
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NCP1581
Vout
3V
VSS
2V
1V
VLDRV
VHDRV
Figure 13. Start-up to Pre-biased Output
Short Circuit Protection
pin is comparator that compares FB voltage to 0.4 V. If FB
voltage is below 0.4 V then IC goes to latch state and switch
output drivers to off state. Latch state can be released by
decrease VCC or VP/EN voltage below threshold.
The output of convertor with NCP1581 is protected
against short circuit conditions. This protection is sensing
output voltage through feedback divider on FB pin. On this
VCC or
VP/EN
Threshold
Vout
Output
shorted
VSS
VLDRV
VHDRV
Figure 14. Short Circuit Protection (Start Up,
Short, Latch, Latch Release and New Start-up)
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NCP1581
Compensation Circuit
One zero of this LC filter is given by the output
capacitance and output capacitor ESR. Its value can be
calculated using the following equation:
The NCP1581 is a voltage mode buck converter with a
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°).
The transfer function of the power stage (the output LC
filter) is a double pole system. The resonance frequency of
this filter is expressed as follows:
f PO +
1
2 @ p @ ǸL @ C OUT
f Z0 +
1
2 @ p @ C OUT @ ESR
(eq. 14)
The next parameter that must be chosen is the zero
crossover frequency f0. It can be chosen to be 1/10–1/5 of the
switching frequency. These three parameters show the
necessary type of compensation that can be selected from
Table 6.
(eq. 13)
Table 6. COMPENSATION TYPES
Zero Crossover Frequency Condition
Compensation Type
Typical Output Capacitor Type
fP0 < fZ0< f0 < fSW/2
Type II (PI)
Electrolytic, Tantalum
fP0 < f0< fZ0 < fSW/2
Type III (PID) Method I
Tantalum, Ceramic
fP0 < f0 < fSW/2 < fZ0
Type III (PID) Method II
Ceramic
Compensation Type II (PI)
Compensation Type III (PID)
This compensation is suitable for low-cost electrolytic
capacitors. The zero created by the capacitor’s ESR is a few
kHz, and the zero crossover frequency is chosen to be 1/10
of the switching frequency. Components of the PI
compensation (Figure 15) network can be specified by the
following equations:
Tantalum and ceramic capacitors have lower ESR than
electrolytic capacitors, so the zero of the output LC filter
goes to a higher frequency above the zero crossover
frequency. This situation needs to be compensated by the
PID compensation network that is shown in Figure 16.
VOUT
VOUT
CC2
RFB1
R1
−
+
CFB1
RC1
CC1
CC2*
R2
1
0.75 @ 2 @ p @ f P0 @ R C1
C C2 +
1
p @ R C1 @ f SW
V OUT * V PńEN
V PńEN
−
OTA
+
There are two methods to select the zeros and poles of the
compensation network. The first one (method I) is usable for
tantalum output capacitors, which have a higher ESR than
ceramics, and its zeros and poles can be calculated as shown
below:
2 @ p @ f 0 @ L @ V RAMP @ V OUT
R C1 +
ESR @ V IN @ V PńEN @ gm
C C1 +
VP/EN
CC1
Figure 16. PID Compensation (Type III)
Figure 15. PI compensation (Type II)
R1 +
RC1
OTA
VP/EN
R2
R1
*Optional
(eq. 15)
f Z1 + 0.75 @ f P0
f Z2 + f P0
@ R2
f P2 + f Z0
f P3 +
VRAMP is the peak-to-peak voltage of the oscillator ramp,
and gm is the transconductance error amplifier gain.
Capacitor CC2 is optional.
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f SW
2
(eq. 16)
NCP1581
The second one (method II) is for ceramic capacitors:
f Z2 + f 0 @
f P2 + f 0 @
Ǹ
Ǹ
The remaining calculations are the same for both
methods.
1 * sin q max
1 ) sin q max
1 ) sin q max
1 * sin q max
2
R C1 uu gm
(eq. 17)
f Z1 + 0.5 @ f Z2
f P3 + 0.5 @ f SW
C C1 +
1
2 @ p @ f Z1 @ R C1
C C2 +
1
2 @ p @ f P3 @ R C1
(eq. 18)
C FB1 +
2 @ p @ f 0 @ L @ V RAMP @ C OUT
V IN @ R C1
R FB1 +
1
2 @ p @ C FB1 @ f P2
1
* R FB1
2 @ p @ C FB1 @ f Z2
V PńEN
R2 +
@ R1
V OUT * V PńEN
R1 +
To check the design of this compensation network, the
following equation must be true:
R1 @ R2 @ R FB1
1 (eq. 19)
u gm
R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2
If it is not true, then a higher value of RC1 must be selected.
ORDERING INFORMATION
Device
NCP1581DR2G
Package
Shipping†
SOIC−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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LITERATURE FULFILLMENT:
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