NCP1599

NCP1599 Product Preview 1 MHz, 3 A Synchronous Buck Regulator The NCP1599 is a fixed 1 MHz, high−output−current, synchronous PWM converter that integrates a low−resistance, high−side P−channel MOSFET and a low−side N−channel MOSFET. The NCP1599 utilizes internally compensated current mode control to provide good transient response, ease of implementation, and excellent loop stability. It regulates input voltages from 2.8 V to 5.5 V down to an output voltage as low as 0.8 V and is able to supply up to 3.0 A of load current. The NCP1599 includes an internally fixed switching frequency (FSW), and an internal soft−start to limit inrush current. Other features include cycle −by −cycle current limiting, short−circuit protection, power saving mode and thermal shutdown. Features http://onsemi.com MARKING DIAGRAM 1 DFN6 CASE 506AH A Y WW G 1 1599 AYWW G • Wide Input Voltage Range: from 2.8 V to 5.5 V • Internal 140 mW High−Side P−Channel and 90 mW Low−Side • • • • • • • • • • • • • • • • • • N−Channel MOSFET Fixed 1 MHz Switching Frequency Cycle−by−Cycle Current Limiting Hiccup Mode Short−Circuit Protection Overtemperature Protection Internal Soft−Start Start−up with Pre−Biased Output Load Adjustable Output Voltage Down to 0.8 V Power Saving Mode During Light Load These are Pb−Free Devices DSP Power Hard Disk Drivers Computer Peripherals Home Audio Set−Top Boxes Networking Equipment LCD TV Wireless and DSL/Cable Modem USB Power Devices = Assembly Location = Year = Work Week = Pb−Free Package PIN CONNECTIONS FB 1 GND 2 LX 3 (Top View) 6 COMP 5 VCC 4 VCCP ORDERING INFORMATION Device NCP1599MNR2G Package Shipping† Applications DFN6 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. P0 1 Publication Order Number: NCP1599/D NCP1599 BLOCK DIAGRAM NCP1599 VCCP VCC Power Reset UVLO THD Hiccup COMP Soft−Start PMOS M1 + CA − + OSC Vref FB + + gm − − PWM + Control Logic LX GND Figure 1. Block Diagram PIN DESCRIPTIONS Pin No 1 2 3 4 5 6 EP Symbol FB GND LX VCCP VCC COMP PAD Description Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage to this pin to set the converter’s output voltage. Ground pin. Connect to thermal pad. The drains of the internal MOSFETs. The output inductor should be connected to this pin. Power input for the power stage Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect to this pin. Output of the Gm Amplifier and compensation node. Connect a series R−C network from this pin to GND for control loop regulation. Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the PCB. This pad must be soldered to the PCB for proper operation. http://onsemi.com 2 NCP1599 APPLICATION CIRCUIT Vin 2.8 V − 5.5 V VCCP VCC COMP LX GND FB Vout 0.8 V − 3.3 V Figure 2. NCP1599 Application Circuit ABSOLUTE MAXIMUM RATINGS Rating Power Supply Pin (Pin 4, 5) to GND LX to GND All other pins Operating Temperature Range Junction Temperature Storage Temperature Range Thermal Resistance Junction−to−Air (Note 1) TA TJ TS RqJA Symbol Vin Value −0.3 V (DC) to 6.5 V −1.0 V For T < 100 ns −0.6 V to Vin + 0.3 V, −1.0 V For T < 100 ns −0.3 V to 6.0 V, −1.0 V For T < 100 ns −40 to +85 −40 to +150 −55 to +150 68.5 °C °C °C °C/W Unit Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper. http://onsemi.com 3 NCP1599 min/max values unless noted otherwise) Parameter Vin Input Voltage Range VCC UVLO Threshold UVLO Hysteresis VCC Quiescent Current VCCP Quiescent Current FEEDBACK VOLTAGE Reference Voltage Feedback Input Bias Current Feedback Voltage Line Regulation GM AMPLIFIER Gm Amp Open Loop Voltage Gain (Note 2) Gm Amp Transconductance (Note 2) PWM Maximum Duty Cycle (Regulating) Minimum Controllable ON Time (Note 2) CURRENT SENSE AMPLIFIER Current Sense to COMP Transconductance (Note 2) PULSE−BY−PULSE CURRENT LIMIT Pulse−by−Pulse Current Limit (Note 3) OSCILLATOR Oscillator Frequency MOSFET High Side MOSFET ON Resistance High Side MOSFET Leakage (Note 2) Low Side MOSFET ON Resistance Low Side MOSFET Leakage (Note 2) SOFT−START Soft−Start Ramp Time (Note 2) Hiccup Timer (Note 2) THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis 2. Guaranteed by design. 3. Current limit operation not guaranteed below Vin = 4.0 V. 170 40 °C °C tSS FSW = 1 MHz 1.0 2.0 ms ms RDS(on) HS RDS(on) LS IDS = 100 mA, VGS = 5 V VSW = 0 V IDS = 100 mA, VGS = 5 V VSW = 5 V 90 140 200 10 125 10 mW mA mW mA FSW 0.87 1.0 1.13 MHz ILIM Vin = 4.0 V − 5.5 V 3.5 4.0 4.5 A gmPOWER 5.0 A/V 83 50 % ns AVgm gmCOMP VFB > 0.75 V, DICOMP=$10 mA 55 1000 dB mA/V Vref IFB VFB = VCOMP VFB = 0.8 V VFB = VCOMP, Vin = 2.7 V to 6.0 V 0.788 0.800 10 0.812 100 0.03 V nA %/V IinVCC IinVCCP Vin = 5.0 V, VFB = 1.5 V, (No Switching) Vin = 5.0 V,VFB = 1.5 V, (No Switching) ELECTRICAL CHARACTERISTICS (Vin = 2.8 V − 5.5 V, Vout = 1.2 V, TJ = +25°C for typical value; −40°C < TJ < +125°C for Symbol Vin Test Conditions Min 2.8 2.4 2.55 200 1.1 1.4 2.0 3.0 Typ Max 5.5 2.65 Unit V V mV mA mA http://onsemi.com 4 NCP1599 DETAILED DESCRIPTION Overview Output MOSFETs The NCP1599 is a synchronous PWM controller that incorporates all the control and protection circuitry necessary to satisfy a wide range of applications. The NCP1599 employs current mode control to provide good transient response, simple compensation, and excellent stability. The features of the NCP1599 include a precision reference, fixed 1 MHz switching frequency, a transconductance error amplifier, an integrated high−side P−channel MOSFET and low−side N−Channel MOSFET, internal soft−start, and very low shutdown current. The protection features of the NCP1599 include internal soft−start, pulse−by−pulse current limit, hiccup mode short−circuit protection, and thermal shutdown. Reference Voltage The NCP1599 includes low RDS(on), both high−side P−channel and low−side N−channel MOSFETs capable of delivering up to 3.0 A of current. When the controller is disabled or during a Fault condition, the controller’s output stage is tri−stated by turning OFF both the upper and lower MOSFETs. Adaptive Dead Time Gate Driver The NCP1599 incorporates an internal reference that allows output voltages as low as 0.8 V. The tolerance of the internal reference is guaranteed over the entire operating temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. Oscillator Frequency In a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. During the dead time, the body diode of the low side FET freewheels the current. The body diode has much higher voltage drop than that of the MOSFET, which reduces the efficiency significantly. The longer the body diode conducts, the lower the efficiency. In NCP1599, the drivers and MOSFETs are integrated in a single chip. The parasitic inductance is minimized. Adaptive dead time control method is used in NCP1599 to prevent the shoot through from happening and minimizing the diode conduction loss at the same time. Pulse Width Modulation A fixed precision oscillator is provided. The oscillator frequency range is 1 MHz with ±13% variation. Transconductance Error Amplifier The transconductance error amplifier’s primary function is to regulate the converter’s output voltage using a resistor divider connected from the converter’s output to the FB pin of the controller, as shown in the applications Schematic. A series RC compensation network must be connected from the error amplifier’s output (COMP pin) to GND to stabilize the converter. In some applications, a lower value capacitor may be connected from the COMP pin to GND to reduce the loop gain at higher frequencies. However, if this capacitor is too large the phase margin of the converter will be reduced. If a Fault occurs, the COMP pin is immediately pulled to GND and PWM switching is inhibited. Internal Soft−Start A high−speed PWM comparator, capable of pulse widths as low as 50 ns, is included in the NCP1599. The inverting input of the comparator is connected to the output of the error amplifier. The non−inverting input is connected to the the current sense signal. At the beginning of each PWM cycle, the CLK signal sets the PWM flip−flop and the upper MOSFET is turned ON. When the current sense signal rises above the error amplifier’s voltage then the comparator will reset the PWM flip−flop and the upper MOSFET will be turned OFF. Power Save Mode If the load current decreases, the converter will enter power save mode operation automatically. During power save mode, the converter skips switching and operates with reduced frequency, which minimizes the quiescent current and maintain high efficiency. Current Sense Amplifier To limit the startup inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. The internal soft start time is 1 ms typically. The NCP1599 monitors the current in the upper MOSFET. The current signal is required by the PWM comparator, the pulse−by−pulse current limiter, and the hiccup mode/over current counter. http://onsemi.com 5 NCP1599 PROTECTIONS Undervoltage Lockout (UVLO) The undervoltage lockout feature prevents the controller from switching when the input voltage is too low to power the internal power supplies and reference. Hysteresis must be incorporated in the UVLO comparator to prevent resistive drops in the wiring or PCB traces from causing ON/OFF cycling of the controller during heavy loading at power up or power down. The UVLO threshold allows steady−state operation at input voltages as low as 3.3 V. However, the current limit at these input voltage levels may not function appropriately due to increased RDSon . This could cause excessive heating and possible device failure. Overcurrent Protection (OCP) another normal soft−start. During soft−start, the overcurrent protection threshold is increased to prevent false overcurrent detection while charging the output capacitors. The hiccup mode scheme reduces input supply current and power dissipation during a short−circuit. It also allows for much improved system up−time by allowing auto−restart upon removal of a temporary short−circuit. Pre−Bias Startup NCP1599 detects high side switch current and then compares to a voltage level representing the overcurrent threshold limit. If the current through the high side FET exceeds the overcurrent threshold limit for seven consecutive switching cycles, overcurrent protection is triggered. Once the overcurrent protection occurs, hiccup mode engages. First, hiccup mode turns off both FETs and discharges the internal compensation network at the COMP pin. Next, the IC waits typically 2 ms and then resets the overcurrent counter. After this reset, the circuit attempts In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP1599 supports pre−bias start up by holding the low side FETs off till soft start ramp reaches the FB Pin voltage. Thermal Shutdown The NCP1599 protects itself from over heating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold the voltage at the COMP pin will be pulled to GND and both the upper and lower MOSFETs will be shut OFF. APPLICATION INFORMATION Programming the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin (see Figure 3). So the output voltage is calculated according to Eq.1. V out + V FB @ Vout L+ V out f @ I ripple @ 1* V out V in(max) (eq. 2) R1 ) R2 R2 (eq. 1) R1 FB R2 Figure 3. Output divider Inductor Selection Where Vout − the output voltage; f − switching frequency, 1.0 MHz; Iripple − Ripple current, usually it’s 20% − 30% of output current; Vin(max) − maximum input voltage. Choose a standard value close to the calculated value to maintain a maximum ripple current within 30% of the maximum load current. If the ripple current exceeds this 30% limit, the next larger value should be selected. The inductor’s RMS current rating must be greater than the maximum load current and its saturation current should be about 30% higher. For robust operation in fault conditions (start−up or short circuit), the saturation current should be high enough. To keep the efficiency high, the series resistance (DCR) should be less than 0.1 W, and the core material should be intended for high frequency applications. Output Capacitor Selection The inductor is the key component in the switching regulator. The selection of inductor involves trade−offs among size, cost and efficiency. The inductor value is selected according to the equation 2. The output capacitor acts to smooth the dc output voltage and also provides energy storage. So the major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is http://onsemi.com 6 NCP1599 related to capacitance and the ESR. The minimum capacitance required for a certain output ripple can be calculated by Equation 4. C OUT(min) + I ripple 8 @ f @ V ripple (eq. 3) network is to stabilize the control loop and achieve high performance in terms of the transient response, audio susceptibility and output impedance. Specifically, the compensator is added to increase low frequency magnitude, extend the 0 dB frequency (crossover frequency), and improve the phase characteristic. Where Vripple is the allowed output voltage ripple. The required ESR for this amount of ripple can be calculated by equation 5. ESR + V ripple I ripple (eq. 4) Current Mode Power Stage LX R1 + Gm − + 0.8 V − FB R2 CFF ESR RL Cout Based on Equation 2 to choose capacitor and check its ESR according to Equation 3. If ESR exceeds the value from Eq.4, multiple capacitors should be used in parallel. Ceramic capacitors can be used in most of the applications. In addition, both surface mount tantalum and through−hole aluminum electrolytic capacitors can be used as well. Maximum Output Capacitor RGM COMP RC CC1 CC2 NCP1599 family has internal 1 ms fixed soft−start and overcurrent limit. It limits the maximum allowed output capacitor to startup successfully. The maximum allowed output capacitance can be determined by the equation: C out(max) + I lim(min) * I load(max) * V out T SS(min) Di p−p 2 Figure 4. NCP1599 Compensation Components (eq. 5) Where TSS(min) is the minimum soft−start period (1ms); DiPP is the current ripple. This is assuming that a constant load is connected. For example, with 3.3 V/2.0 A output and 20% ripple, the maximum allowed output capacitance is 546 mF. Input Capacitor Selection There are several different types of compensation that can be used to improve the frequency response of the control loop. To determine which compensation scheme to use, some information about the power stage is needed. Use Vin = Vin(min) and R = Rmin (Iout(max)) when calculating compensation components. The DC gain of the voltage feedback loop is given by: A DC + R G CS A EA V FB V out (eq. 8) The input capacitor can be calculated by Equation 6. C in(min) + I out(max) @ D max @ 1 f @ V in(ripple) (eq. 6) Where AEA is the error amplifier voltage gain, 560 V/V (55 db), GCS is the current sense transconductance, 5.0 A/V, and R is the load resistor value. The power stage has one pole due to the output capacitor Cout and the load resistor R. It’s located at: f p1 + 1 2p @ C out @ R (eq. 9) Where Vin(ripple) is the required input ripple voltage. D max + V out V in(min) is the maximum duty cycle. (eq. 7) Compensation Design The NCP1599 is a current mode controller, therefore there are two feedback loops. The inner feedback loop derives its feedback from the sensed inductor current, while the outer loop monitors the output voltage. The compensation network is designed around the power components, or the power stage. An isolated schematic of the error amplifier and the various compensation components is shown in Figure 4. The error amplifier in conjunction with the compensation network makes up the compensator network. The purpose of the compensator The power stage may have a zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: f ESRZ + 1 2p @ C out @ R ESR (eq. 10) A compensator is designed to achieve improved performance and stability. The NCP1599 will typically require only a single resistor and capacitor for compensation, but depending on the power stage it could require three or four external components. First, a target crossover frequency (fc) for the loop gain must be selected. The crossover frequency is the bandwidth http://onsemi.com 7 NCP1599 of the converter. A higher bandwidth generally corresponds to faster response times and lower overshoots to load transients. However, the bandwidth should not be much higher than 1/10 the switching frequency. The NCP1599 operates with a 1.0 MHz switching frequency, so it is recommended to choose a crossover frequency between 40 kHz − 100 kHz. The schematic of the NCP1599 compensator is shown in Figure 2. The default design uses Rc and CC1 to form a lag (Type 2) compensator. The CC2 capacitor can be added to form an additional pole that is typically used to cancel out the ESR zero of the output capacitor. Finally, if extra phase margin is needed, the CFF capacitor can be added (this does not help at low output voltages, see below). The strategy taken here for choosing Rc and CC1 is to set the crossover frequency with Rc, and set the compensator zero with CC1. Using the selected target crossover frequency, fc, set Rc to: RC + 2p @ f C @ C out Gm EA @ G CS @ V out V FB W (eq. 11) C C2 + R GM ) R C 2p f ESR R GM R C (eq. 17) A feed−forward capacitor is recommended for most designs. The large resistor value and the parasitic capacitance of the FB Pin can cause a high frequency pole that can reduce the overall system phase margin. By placing a feed−forward capacitor CFF, these effects can be significantly reduced. CFF will provide a positive phase shift (lead) that can be used to increase phase margin. However, it is important to note that the effectiveness of CFF decreases with output voltage. This is due to the fact that the frequency of the zero fzff and pole fpff get closer together as the output voltage is reduced. The frequency of the feed−forward zero and pole are: f Zff + 1 2p R FB1C ff 1 2p R FB1 C ff R FB2 + f Zff V out V FB (eq. 18) f pff + R FB1 ) R FB2 (eq. 19) fC = Crossover frequency in Hertz (50kHz − 200kHz is recommended). The zero, due to the compensation capacitor (Cc1) and the compensation resistor (Rc), is located at: f Z1 + 2p 1 C C1 RC (eq. 12) Power Dissipation When fast transient responses are desired, fZ1 should be placed as high as possible, however it should not be higher than the selected crossover frequency fc. The guideline proposed here is to choose CC1 such that fZ1 falls somewhere between the power pole fP1 and 1⁄2 decade before the selected crossover frequency fc: 3.16 2p R C f C v C C1 v 1 2p f p1 R C (eq. 13) The compensation capacitor (Cc1) and the output resistor of error amplifier RGM creates another pole of the system, and it’s located at: f p2 + 1 2p C C1 R GM , (eq. 14) The NCP1599 is available in thermally enhanced 6−pin, DFN package. When the die temperature reaches +185°C, the NCP1599 shuts down (see the Thermal−Overload Protection section). The power dissipated in the device is the sum of the power dissipated from supply current (PQ), power dissipated due to switching the internal power MOSFET (PSW), and the power dissipated due to the RMS current through the internal power MOSFET (PON). The total power dissipated in the package must be limited so the junction temperature does not exceed its absolute maximum rating of +150°C at maximum ambient temperature. Calculate the power lost in the NCP1599 using the following equations: 1. High side MOSFET The conduction loss in the top switch is: P HSON + I 2 RMS_HSFET R DS(on)HS (eq. 20) Where: I RMS_FET + I out 2 ) DI PP 12 2 Where RGM = 66 • 103 W. In this compensation scheme, the pole created by CC2 is used to cancel out the zero created by the ESR of the output capacitor. This pole is located at: f p3 + 1 2p @ C C2 @ R RR D (eq. 21) , GM C GM )R (eq. 15) DIPP is the peak−to−peak inductor current ripple. The power lost due to switching the internal power high side MOSFET is: P HSSW + V in @ I out @ t r ) t f @ f SW 2 (eq. 22) C For the typical case, use CC2 if: f ESR t fS 2 (eq. 16) tr and tf are the rise and fall times of the internal power MOSFET measured at SW node. http://onsemi.com 8 NCP1599 2. Low side MOSFET The power dissipated in the top switch is: P LSON + I RMS_LSFET 2 @ R DS(on)LS (eq. 23) Layout Where: I RMS_LSFET + I out 2 ) DI PP 12 2 @ (1 * D ) (eq. 24) DIPP is the peak−to−peak inductor current ripple. The switching loss for the low side MOSFET can be ignored. The power lost due to the quiescent current (IQ) of the device is: P Q + V in @ I Q P TOTAL + P HSON ) P HSSW ) P LSON ) P Q (eq. 25) IQ is the switching quiescent current of the NCP1599. (eq. 26) Calculate the temperature rise of the die using the following equation: T J + T C ) P TOTAL @ q JC (eq. 27) qJC is the junction−to−case thermal resistance equal to 1.7°C/W. TC is the temperature of the case and TJ is the junction temperature, or die temperature. The case−to− ambient thermal resistance is dependent on how well heat can be transferred from the PC board to the air. Solder the underside−exposed pad to a large copper GND plane. If the die temperature reaches the thermal shutdown threshold the NCP1599 shuts down and does not restart again until the die temperature cools by 30°C. As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. To prevent noise both radiated and conducted, the high speed switching current path must be kept as short as possible. Shortening the current path will also reduce the parasitic trace inductance of approximately 25 nH/inch. At switch off, this parasitic inductance produces a flyback spike across the NCP1599 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the NCP1599 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise. The COMP and FB components should be kept as far away as possible from the switch node. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic like oscillation. Board layout also has a significant effect on thermal resistance. Reducing the thermal resistance from the ground pin and exposed pad onto the board will reduce die temperature and increase the power capability of the NCP1599. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple thermal vias under and around this pad to an internal ground plane will also help. Similar treatment to the inductor pads will reduce any additional heating effects. http://onsemi.com 9 NCP1599 PACKAGE DIMENSIONS DFN6 3*3 MM, 0.95 PITCH CASE 506AH−01 ISSUE O SCALE 2:1 D A B NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMESNION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.35 0.40 0.45 3.00 BSC 2.40 2.50 2.60 3.00 BSC 1.50 1.60 1.70 0.95 BSC 0.21 −−− −−− 0.30 0.40 0.50 2X 0.15 C 2X 0.15 C 0.10 C 6X 0.08 C SIDE VIEW 6X L 1 6X K 6 4 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ D2 PIN 1 REFERENCE E DIM A A1 A3 b D D2 E E2 e K L TOP VIEW A (A3) A1 e 3 4X C SEATING PLANE SOLDERING FOOTPRINT* 0.450 0.0177 0.950 0.0374 E2 3.31 0.130 6X 1.700 0.685 b (NOTE 3) 0.10 C A B BOTTOM VIEW 0.05 C 0.63 0.025 2.60 0.1023 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 NCP1599/D