NCP1605, NCP1605A,
NCP1605B
Power Factor Controller,
Enhanced, High Voltage and
Efficient Standby Mode
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The NCP1605 is a controller that exhibits near−unity power factor
while operating in fixed frequency, Discontinuous Conduction Mode
(DCM) or in Critical Conduction Mode (CRM).
Housed in a SOIC−16 package, the circuit incorporates all the
features necessary for building robust and compact PFC stages, with
a minimum of external components. In addition, it integrates the skip
cycle capability to lower the standby losses to a minimum.
General Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Near−Unity Power Factor
Fixed Frequency, Discontinuous Conduction Mode Operation
Critical Conduction Mode Achievable in Most Stressful Conditions
Lossless High Voltage Current Source for Startup
Soft Skipt Cycle for Low Power Standby Mode
Switching Frequency up to 250 kHz
Synchronization Capability
Fast Line / Load Transient Compensation
Valley Turn On
High Drive Capability: −500 mA / +800 mA
Signal to Indicate that the PFC is Ready for Operation
(“pfcOK” Pin)
VCC range: from 10 V to 20 V
Follower Boost Operation
Two VCC Turn−On Threshold Options:
15 V for NCP1605 & NCP1605B; 10.5 V for NCP1605A
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
•
•
Output Under and Overvoltage Protection
Brown−Out Detection
Soft−Start for Smooth Startup Operation
Overcurrent Limitation
Zero Current Detection Protecting the PFC stage from Inrush
Currents
Thermal Shutdown
Latched Off Capability
Typical Applications
• PC Power Supplies
• All Off Line Appliances Requiring Power Factor Correction
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 12
16
NCP1605G
AWLYWW
1
1
SOIC−16
D SUFFIX
CASE 751B
16
NCP1605xG
AWLYWW
1
x = A or B
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
G = Pb−Free Package
PIN CONNECTIONS
STBY 1
16 HV
BO 2
15 NC
14 OVP/UVP
Vcontrol 3
FB 4
13 STDWN
CSin 5
12 pfcOK/REF5V
CSout/ZCD 6
11 VCC
Ct 7
10 DRV
OSC/SYNC 8
Safety Features
•
•
•
•
•
MARKING
DIAGRAMS
1
9
GND
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1605DR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
NCP1605ADR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
NCP1605BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NCP1605/D
NCP1605, NCP1605A, NCP1605B
Rout1
Rbo1
Rout2
Vout
STBY control
Rbo2
Rovp1
1 16
2 15
Cbo
3 14
FB
CVctrl
CVCC
6 11
Vout
D1
VCC
7 10
Ct
8
CVref
pfcOK
LOAD
M1
Cbulk +
9
Cosc
Rocp
L1
Rovp2
OVP
5 12
Ac line
EMI
Filter
Icoil
+
4 13
Rzcd
Cin
Vin
VCC
Rdrv
Icoil
Rcs
Figure 1.
MAXIMUM RATINGS
Pin
Symbol
Value
Unit
11
Power Supply Input
Rating
VCC
−0.3, +20
V
11
Maximum Transient Voltage (Note 1)
VCC
−0.3, +25
V
VI
−0.3, +9
V
ICSOUT/ZCD
−3, 10
mA
VCONTROL
−0.3, VCONTROL MAX
(Note 2)
V
1, 2, 4, 5, 6, 7, 8, Input Voltage
13 and 14
6
Maximum Current
3
VCONTROL Pin
16
High Voltage Pin
VHV
−0.3, 600 V
V
Power Dissipation and Thermal Characteristics:
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
PD
RqJA
550
145
mW
°C/W
TJ
−55 to +125
°C
Maximum Junction Temperature
TJmax
150
°C
Storage Temperature Range
TSmax
−65 to +150
°C
Lead Temperature (Soldering, 10 s)
TLmax
300
°C
ESD Capability, HBM Model (all pins except HV) (Note 3)
HBM
2000
V
ESD Capability, MM Model (all pins except HV) (Note 3)
MM
200
V
Operating Junction Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability
must be observed as well.
2. “VCONTROLMAX” is the pin clamp voltage.
3. This device series contains ESD protection rated using the following tests:
Human Body Model (HBM) 2000V per JEDEC Standard JESD22, Method A114E.
Machine Model (MM) 200V per JEDEC Standard JESD22, Method A115A.
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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2
NCP1605, NCP1605A, NCP1605B
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified;
For NCP1605DR2G: for typical values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 7)
Symbol
Rating
Min
Typ
Max
Unit
Gate Drive Section
Trise
Output Voltage Rise Time @ CL = 1 nF, from 1 V to 10 V
−
40
−
ns
Tfall
Output Voltage Fall Time @ CL = 1 nF, from 10 V to 1 V
−
20
−
ns
ROH
Source Resistance @ IPin10 = 100 mA
−
15
25
W
Source Current capability (@ VPin10 = 0 V)
−
500
−
mA
ROL
Sink Resistance @ IPin10 = 100 mA
−
7
15
W
Isink
Sink Current Capability (@ VPin10 = 10 V)
−
800
−
mA
2.425
2.430
2.500
2.500
2.575
2.550
V
−
±20
−
mA
Isource
Regulation Block
VREF
Voltage Reference
NCP1605/A
NCP1605B
IEA
Error Amplifier Current Capability
GEA
Error Amplifier Gain
100
200
300
mS
Pin 4 Bias Current @ VPin4 = VREF
−500
−
500
nA
−
−
2.7
3.6
0.6
3.0
−
−
3.3
95.0
95.5
96.0
IBPin4
VCONTROL
− VCONTROLMAX
− VCONTROLMIN
− D VCONTROLl
Pin 2 Voltage:
V
− @ VPin4 = 2 V
− @ VPin4 = 3 V
VOUTL / VREF
Ratio (VOUT Low Detect Threshold / VREF) (Note 6)
HOUTL / VREF
Ratio (VOUT Low Detect Hysteresis / VREF) (Note 6)
IBOOST
Pin 2 Source Current when (VOUT Low Detect) is activated
%
−
−
0.5
%
190
240
290
mA
Shutdown Block
ILEAKAGE
Current Sourced by Pin 13 @ VPin14 = 2.3 V
−500
−
500
nA
VSTDWN
Pin 13 Threshold for Shutdown
2.375
2.500
2.625
V
Over and Under Voltage Protections
Overvoltage Protection Threshold
2.425
2.500
2.575
V
VOVP / VREF
VOVP
Ratio (VOVP / VREF) (Note 5)
99.5
100.0
100.5
%
VUVP / VREF
Ratio UVP threshold over VREF
8
12
16
%
−500
−500
−
−
500
500
TJ = 0°C to +125°C
NCP1605, TJ = −40°C to +125°C
NCP1605, TJ = −55°C to +125°C
54
52
51
60
−
−
69
69
69
@ VPin4 = 1.75 V
@ VPin4 = 2.50 V
156
313
182
370
214
428
−
5
−
V
0.9
1
1.1
V
IBPin14
Pin 13 Bias Current:
nA
@ VPin14 = VOVP
@ VPin14 = VUVP
Ramp Control
mA
Pin 7 Source Current: @ VPin4 = 1.00 V
IRAMP − 1.00 V
mA
Pin 7 Source Current:
IRAMP − 1.75 V
IRAMP − 2.50 V
Vcl_ff
VCLCRM
Pin 7 Clamp Voltage @ VPin4 = VPin2 = 2 V and VPin6 = 0 V
Pin 7 Clamp Voltage @ VPin4 = 0 V, VPin2 = 2 V and VPin6 = 1 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Not tested; guaranteed by characterization
6. Not tested; guaranteed by design
7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1605, NCP1605A, NCP1605B
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified;
For NCP1605DR2G: for typical values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 7)
Symbol
Rating
RCT
Ratio (Pin 7 Clamp Voltage / (Pin 7 Charge Current)
(VCLCRM / IRAMP) @ VPin6 = 0 V and
− VPin4 = 1.00 V
− VPin4 = 1.75 V
− VPin4 = 2.50 V
−
−
−
16.7
5.4
2.7
−
−
−
Delay (VPin7 > 5 V) to (DRV low)
−
90
200
ns
CINT
Average Pin 7 Internal Capacitance (VPin7 varying from 0 and 1 V)
Guaranteed by design
−
15
25
pF
VINIT
Maximum Pin 7 Voltage Allowing the Setting of the PWM Latch
−
50
90
mV
Pin 7 Sink Current (Drive low) @ VPin7 = 1 V
−
10
−
mA
−20
−5.0
6.0
6.0
20
15
mV
TONMIN
IRAMP_SINK
Min
Typ
Max
Unit
kW
Current Sense Block
Off100
Current Sense Pin Voltage,
100 mA being drawn from Pin 5
Off10
Current Sense Pin Voltage, 10 mA being drawn from Pin 5
3.0
8.0
13
mV
IMAX
Overcurrent Protection Threshold
230
250
265
mA
TOCP
(Ipin5 > 250 mA) to (DRV low) Propagation Delay (Note 5)
−
100
200
ns
KCS10
Ratio (IPin6/IPin5) @ IPin5 = 10 mA
99
108
117
%
KCS200
Ratio (IPin6/IPin5) @ IPin5 = 200 mA
98
101
103
%
VZCD
Pin 6 Comparator Threshold
50
100
200
mV
TZCD
Delay from (VPin6 < VZCD) to (DRV high)
−
120
240
ns
VSTBY
Standby Mode Threshold (VPin1 falling)
280
310
340
mV
HSTBY
Hysteresis for Standby Mode Detection
25
30
50
mV
99
100
101
%
TJ = 0°C to +125°C
NCP1605, TJ = −40°C to +125°C
NCP1605, TJ = −55°C to +125°C
90
89
88
100
−
−
110
110
110
TJ = 0°C to +125°C
NCP1605, TJ = −40°C to +125°C
NCP1605, TJ = −55°C to +125°C
90
89
88
100
−
−
110
110
110
−
3.0
−
V
NCP1605/A
NCP1605B
Standby Input
VSKIPOUT / VOUTL Ratio (Pin 4 Voltage to terminate a SKIP period) over the
(VOUT Low Detect Threshold) (Note 6)
Oscillator / Synchronization Block
Icharge
Idisch
Comparator Upper Threshold
Vsync_L
Comparator Lower Threshold
Tsync_min
mA
Oscillator Discharge Current
Vsync_H
Swing
mA
Oscillator Charge Current
−
2.0
−
V
0.9
1.0
1.1
V
Minimum Synchronization Pulse Width for Detection
−
−
500
ns
Pin 12 Voltage @ VPin13 = 5 V, 250 mA being sunk by Pin 12
−
60
120
mV
Comparator Swing (Vsync_H − Vsync_L)
pfcOK / REF5V
VpfcOKL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Not tested; guaranteed by characterization
6. Not tested; guaranteed by design
7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1605, NCP1605A, NCP1605B
TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0°C to +125°C, unless otherwise specified;
For NCP1605DR2G: for typical values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 7)
Symbol
Rating
VpfcOKH
(Pin 12 Voltage @ VPin13 = 0 V and
VPin3 = 5 V, with a 250 mA sourced by Pin 12)
(Pin 12 Voltage @ VPin13 = 0 V and
VPin3 = 5 V, with a 5 mA sourced by Pin 12)
Icap_ref
Current Capability
NCP1605/A
NCP1605B
NCP1605/A
NCP1605B
Min
Typ
Max
Unit
4.7
4.75
4.5
4.5
5.0
5.0
5.0
4.72
5.3
5.3
5.3
5.0
V
5 .0
10
−
mA
Brown−Out Detection Block
VBOH
Brown−Out Comparator Threshold (VPin2 rising)
NCP1605/A
NCP1605B
0.9
0.93
1.0
1.0
1.1
1.07
V
VBOL
Brown−Out Comparator Threshold (VPin2 falling)
NCP1605/A
NCP1605B
0.45
0.465
0.50
0.50
0.55
0.535
V
IBBO
Pin 2 Bias Current @ VPin2 = 0.5 V and 1 V
−500
−
500
nA
Thermal Shutdown
TLIMIT
Thermal Shutdown Threshold
−
155
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
15
−
°C
VCC UNDERVOLTAGE Lockout Section
VCCON
Turn on Threshold Level, VCC Raising Up
NCP1605
NCP1605A
NCP1605B
14
9.5
14.2
15
10.5
15
16
11.5
15.55
V
VCCOFF
Minimum Operating Voltage after Turn−on
NCP1605/A
NCP1605B
8.0
8.6
9.0
9.0
10
9.35
V
Difference (VCCON − VCCOFF)
NCP1605/B
NCP1605A
5.0
1.2
6.0
1.5
−
−
V
HUVLO
VCCSTUP
VCC Threshold below which the Startup Current Source Turns on
5.5
7.0
8.0
V
HLATCHOFF
Difference (VCCOFF − VCCSTUP)
0.6
2.0
−
V
VCC Level at which the Logic Resets
2.0
4.0
5.0
V
Threshold which IC2 stops working & switches to IC1, IC2 = 1 mA
NCP1605, TJ = 0°C to +125°C
NCP1605, TJ = −40°C to +125°C
NCP1605, TJ = −55°C to +125°C
NCP1605A
NCP1605B
−
0.3
0.3
−
0.3
2.1
−
−
2.1
1.8
−
2.5
2.55
−
2.2
VCCRST
VCCINHIBIT
V
Internal STARTUP Current Source
IC1_hv
IC1_Vcc
IC2
(High−Voltage Current Source
sunk by Pin 16, VCC = 13.5 V)
NCP1605/A
NCP1605B
5.0
7.0
12
12
20
17
mA
(Startup Charge Current flowing
out of the VCC Pin, VCC = 13.5 V)
NCP1605/A
NCP1605B
5.0
6.5
12
12
20
16.5
mA
High−Voltage Current Source, VCC = 0 V
NCP1605/A
NCP1605B
−
0.375
0.5
0.5
1.0
0.87
mA
−
2.0
310
310
2.5
3.5
570
550
5.0
7.0
780
750
mA
mA
mA
mA
Device Consumption
Icc_op1
Icc_op2
Icc_OFF
Icc_latchOFF
Power Supply Current:
Operating (@ VCC = 16 V, no load, no switching)
Operating (@ VCC = 16 V, no load, switching)
Off Mode (@ VCC = 16 V, Pin 2 grounded)
Latched−Off Mode (@ VCC = 13.5 V and VPin13 = 5 V)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Not tested; guaranteed by characterization
6. Not tested; guaranteed by design
7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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5
NCP1605, NCP1605A, NCP1605B
PIN FUNCTION DESCRIPTION
Pin
Number
Name
Function
1
STBY
An external signal (typically, a portion of the feedback signal of the downstream converter or a filtered
portion of the SMPS drive pulses) should be applied to Pin 1. When the Pin 3 voltage goes below
300 mV, the circuit enters a burst mode operation where the bulk voltage varies between the regulation
voltage and 95.5% of this level.
2
Brown−Out /
Inhibition
Apply a portion of the averaged input voltage to detect brown−out conditions. If VPin2 is lower than
0.5 V, the circuit stops pulsing until VPin2 exceeds 1 V (0.5 V hysteresis).
Ground Pin 6 to disable the part.
3
VCONTROL /
Soft−Start
The error amplifier output is available on this Pin. The capacitor connected between this pin and ground
adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor
ratios.
Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly
(soft−start).
4
Feedback
This pin receives a portion of the pre−converter output voltage. This information is used for the
regulation and the “output low” detection (VOUTL) that drastically speed up the loop response when the
output voltage drops below 95.5% of the wished level.
5
Current Sense
Input
This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the
maximum coil current and detect the core reset (coil demagnetization).
6
Current Sense
Output
This pin sources the Pin 5 current. Place a resistor between Pin 6 and ground to build the voltage
proportional to the coil current and detect the core reset. The impedance between Pin 6 and ground
should not exceed 3 times that of the Pin 5 to ground. You can further apply the voltage from an
auxiliary winding to improve the valley detection of the MOSFET drain source voltage.
7
Ct
(Ramp)
The circuit controls the power switch on−time by comparing the Pin 7 ramp to an internal voltage
(“Vton”) derived from the regulation block and the sensed “dcycle” (relative duration of the current cycle
over the corresponding switching period).
Pin 7 sources a current proportional to the squared output voltage to allow the Follower Boost operation
(optional) where the PFC output voltage stabilizes at a level that varies linearly versus the ac line
amplitude. This technique reduces the difference between the output and input voltages, to optimize the
boost efficiency and minimize the size and cost of the PFC stage
8
Oscillator /
synchronization
Connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. If the
coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the
core is reset. Hence, the PFC stage can operate in CRM in the most stressful conditions.
9
GND
Connect this pin to the pre−converter ground.
10
Drive
The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively
drive high gate charge power MOSFETs.
11
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 15 V (10.5 V
for NCP1605A) and turns off when VCC goes below 9 V (typical values). After startup, the operating
range is 10 V up to 20 V.
12
PfcOK / REF5V
The Pin 12 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low
otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and
that hence, it can start operation.
13
STDWN
14
OVP / UVP
15
NC
Creepage distance.
16
HV
Connect Pin 16 to the bulk capacitor. The internal startup current source placed between Pin 16 and the
VCC terminal, charges the VCC capacitor at startup.
Apply a voltage higher than 2.5 V on Pin 13 to permanently shutdown the circuit. This pin can be used
to monitor the voltage across a thermistor in order to protect the application from an excessive heating
and/or to detect an overvoltage condition.
To resume operation, it is necessary to decrease the circuit VCC below VCCRST (4 V typically) by for
instance, unplugging the PFC stage and replugging it after VCC is discharged.
The circuit turns off when VPin14 goes below 300 mV (UVP) and disables the drive as long as the pin
voltage exceeds 2.5 V (OVP).
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NCP1605, NCP1605A, NCP1605B
2.59
265
2.57
260
2.55
255
IREF, (mA)
VREF, (V)
2.53
2.51
2.49
2.47
250
245
2.45
240
2.43
2.41
−40
−15
10
35
60
85
235
−40
110
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Reference Voltage vs. Temperature
Figure 3. Reference Current vs. Temperature
103
2.60
102
VOVP/VREF, (%)
2.56
2.52
2.48
2.44
101
100
99
98
2.40
−40
−15
10
35
60
85
97
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Overvoltage Threshold vs. Temperature
Figure 5. Ratio Overvoltage Threshold
Overvoltage Reference vs. Temperature
2.61
2.56
VSTDWN, (V)
VOVP, (V)
−15
TJ, JUNCTION TEMPERATURE (°C)
2.51
2.46
2.41
2.36
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
110
Figure 6. Shutdown Threshold vs. Temperature
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NCP1605, NCP1605A, NCP1605B
0.6
0.5
15.16
VUVPVREF, (%)
VUVP, (V)
0.4
0.3
0.2
13.12
11.08
9.04
0.1
0
−40
−15
10
35
60
85
7
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Undervoltage Protection Threshold vs.
Temperature
Figure 8. Ratio (VUVP/VREF) vs. Temperature
15.4
9.7
9.4
15.1
VCCOFF, (V)
VCCON, (V)
9.1
14.8
14.5
14.2
13.9
−40
8.8
8.5
8.2
−15
10
35
60
85
7.9
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. VCC Turn on Threshold vs.
Temperature (VCC Raising Up) − NCP1605/B
Figure 10. VCC Minimum Operating Voltage
After Turn On − NCP1605/B
8.8
6.7
8.3
7.8
VCCSTUP, (V)
HUVLO, (V)
6.4
6.1
5.8
7.3
6.8
6.3
5.8
5.5
5.3
5.2
−40
−15
10
35
60
85
4.8
−40
110
TJ, JUNCTION TEMPERATURE (°C)
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Difference (VCCON − VCCOFF) vs.
Temperature − NCP1605/B
Figure 12. VCC Threshold Below which the Startup
Current Source Turns on vs. Temperature
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8
NCP1605, NCP1605A, NCP1605B
4
6
3.5
5
VCCRST, (V)
HLATCHOFF, (V)
3
2.5
2
4
3
2
1.5
1
1
−15
10
35
60
85
0
−40
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Difference (VCCOFF−VCCSTUP) vs.
Temperature
Figure 14. VCC Level Below Which the
Logic Resets vs. Temperature
20
20
18
18
16
16
IC1_VOFF, (mA)
IC1_HV, (mA)
0.5
−40
14
12
10
14
12
10
8
8
6
6
4
110
4
−40
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. High−Voltage Current Source (Sunk
by Pin 16) vs. Temperature (@ VCC = 13.5 V)
Figure 16. Startup Charge Current Flowing Out
of the VCC Pin vs. Temperature (@ VCC = 13.5 V)
90
1.2
80
70
HV_LEAKAGE, (mA)
IC2, (mA)
0.9
0.6
0.3
60
50
40
30
20
10
0
−40
0
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. High−Voltage Current Source vs.
Temperature (@ VCC = 0 V)
Figure 18. Pin 16 Leakage Current vs.
Temperature (@ VPIN16 = 500 V and VCC = 16 V)
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9
24
−12
22
−14
IEA_SINK, (mA)
IEA_SOURCE, (mA)
NCP1605, NCP1605A, NCP1605B
20
18
16
−16
−18
−20
−22
14
12
−40
−15
10
35
60
85
−24
−40
110
−15
TJ, JUNCTION TEMPERATURE (°C)
35
60
85
110
Figure 20. Sink Current Capability of the Error
Amplifier vs. Temperature
300
150
260
100
220
50
IBPIN4, (nA)
GEA, (mS)
Figure 19. Source Current Capability of the
Error Amplifier vs. Temperature
180
140
0
−50
100
−100
60
−40
−15
10
35
60
85
−150
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Error Amplifier Gain vs. Temperature
Figure 22. Feedback Pin Bias Current vs.
Temperature (@ VPIN4 = VREF)
3.9
3.3
3.8
3.2
3.7
3.1
D(VCONTROL), (V)
VCONTROLMAX, (V)
10
TJ, JUNCTION TEMPERATURE (°C)
3.6
3.5
3.4
2.9
2.8
2.7
3.3
3.2
−40
3
2.6
−15
10
35
60
85
110
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. VCONTROL Maximum Voltage vs.
Temperature
Figure 24. VCONTROL Maximum Swing
(DVCONTROL) vs. Temperature
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10
110
95.9
270
95.8
260
95.7
250
95.6
IBOOST, (mA)
VOUTL/VREF, (%)
NCP1605, NCP1605A, NCP1605B
95.5
95.4
240
230
220
95.3
210
95.2
200
95.1
190
−40
−15
10
35
60
85
110
−40
TJ, JUNCTION TEMPERATURE (°C)
105
105
100
100
IDISCH, (mA)
ICHARGE, (mA)
110
95
90
85
85
35
60
85
80
−40
110
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. Oscillator Charge Current vs.
Temperature
Figure 28. Oscillator Discharge Current vs.
Temperature
150
125
pfcOK_L (mV)
0.99
SWING, (V)
85
TJ, JUNCTION TEMPERATURE (°C)
1.01
0.97
0.95
0.93
0.91
−40
60
95
90
10
35
Figure 26. Pin 3 Source Current when (VOUT Low
Detect Threshold) is Activated vs. Temperature
110
−15
10
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. Ratio (VOUT Low Detect Threshold) /
VREF vs. Temperature
80
−40
−15
100
75
50
25
−15
10
35
60
85
0
−40
110
TJ, JUNCTION TEMPERATURE (°C)
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Oscillator Swing vs. Temperature
Figure 30. pfcOK Pin Low Level Voltage vs.
Temperature
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11
5.5
5
5.3
4
ICC_OP1, (mA)
pfcOK_H, (V)
NCP1605, NCP1605A, NCP1605B
5.1
4.9
4.7
2
1
4.5
−40
−15
10
35
60
85
0
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. pfcOK Pin High Level Voltage vs.
Temperature (250 mA Load)
Figure 32. Operating Consumption vs.
Temperature (VCC = 16 V, No Load, No Switching)
800
5
700
ICCOFF, (mA)
6
4
3
600
500
400
2
1
−40
−15
10
35
60
85
300
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 33. Operating Consumption vs.
Temperature (VCC = 16 V, No Load, Switching)
Figure 34. Off Mode Consumption vs.
Temperature (VCC = 16 V, Pin 2 Grounded)
800
700
ICCSTDOWN, (mA)
ICC_OP2, (mA)
3
600
500
400
300
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 35. Shutdown Mode Consumption vs.
Temperature (VCC = 16 V, Pin 2 GND)
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12
NCP1605, NCP1605A, NCP1605B
1.05
0.55
VCBOL, (V)
0.6
VCBOH, (V)
1.1
1
0.95
0.5
0.45
0.9
0.4
−40
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 36. Brown−Out Upper Threshold vs.
Temperature
Figure 37. Brown−Out Lower Threshold vs.
Temperature
14
14
12
12
8
OFF10, (mV)
OFF100, (mV)
10
6
4
10
8
6
2
4
0
−2
2
−40
−15
10
35
60
85
110
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. Current Sense Pin Voltage vs.
Temperature (100 mA Being Drawn from Pin 5)
Figure 39. Current Sense Pin Voltage vs.
Temperature (10 mA Being Drawn from Pin 5)
68
208
66
203
IRAMP_1.75 V, (mA)
IRAMP_1.00 V, (mA)
198
64
62
60
58
56
193
188
183
178
173
168
54
163
158
−40
52
−40
−15
10
35
60
85
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. Pin 7 Source Current
@ VPIN4 = 1.0 V vs. Temperature
Figure 41. Pin 7 Source Current
@ VPIN4 = 1.75 V vs. Temperature
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13
110
NCP1605, NCP1605A, NCP1605B
8
415
405
7
385
RCT (kW)
IRAMP_2.50 V, (mA)
395
375
365
6
5
355
345
4
335
325
−40
−15
10
35
60
85
3
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 42. Pin 7 Source Current @
VPIN4 = 2.5 V vs. Temperature
Figure 43. Ratio Pin 7 Clamp Voltage /
(Pin 7 Charge Current) that is (VCLCRM / IRAMP)
@ VPIN6 = 0 V and VPIN4 = 1.75 V
112
200
180
160
VZCD, (mV)
Kcs10, (%)
110
108
106
140
120
100
80
60
104
−40
−15
10
35
60
85
40
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 44. Ratio (IPIN6 / IPIN5) @ IPIN5 = 10 mA vs.
Temperature
Figure 45. Pin 6 Comparator Threshold vs.
Temperature
220
340
200
330
180
320
VSKIPH, (V)
TZCD, (ns)
160
140
120
100
310
300
290
80
280
60
270
40
−40
−15
10
35
60
85
260
−40
110
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 46. Delay from (ZCD Pin Low) to
(DRV High) vs. Temperature
Figure 47. Skip Cycle Threshold
(VPIN1 Falling) vs. Temperature
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14
110
26
160
24
140
22
120
20
ROH, (W)
180
100
80
18
16
60
14
40
12
20
10
0
−40
−15
10
35
60
85
8
−40
110
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 48. Minimum On−Time vs. Temperature
Figure 49. Gate Drive Source Resistance vs.
Temperature
16
14
12
ROL, (W)
tOMIN, (ns)
NCP1605, NCP1605A, NCP1605B
10
8
6
4
2
−40
−15
10
35
60
85
TJ, JUNCTION TEMPERATURE (°C)
110
Figure 50. Gate Drive Sink Resistance vs. Temperature
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15
NCP1605, NCP1605A, NCP1605B
Vout Low Detect
95.5% Vref
200 mA
VoutL
+
-
All the RS latches are
RESET dominant
HVCS_ON
HV
UVLO
pfcOK
Error Amplifier
VSTBY
+
Vref
±20 mA
FB
VDD
UVLOs
Latch
Reset
Internal
Thermal
Shutdown
TSD
UVLO (Vcc 250 mA
100 mV
CSout
ZCD
ZCD
+
-
REF5V
pfcOK
OVP
12% Vref
+
UVP
+
-
OVP
Vref
stdwn
+
S
Q
R
Vcc Vton during (t1+t2)
−> 0 V during t3 (dead−time)
−> Vton*(t1+t2)/T in average
S2
DT
(high during
dead−time)
Ramp Voltage
Figure 56. VTON Processing Circuit
PWM Outtage
The integrator OA1 amplifies the error between VREGUL and
IN1 so that in average, (VTON*(t1+t2)/T) equates VREGUL.
Figure 55. PWM Circuit and Timing Diagram
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19
Vin (V)
NCP1605, NCP1605A, NCP1605B
350,00
3,50
300,00
3,00
250,00
2,50
200,00
2,00
150,00
1,50
100,00
1,00
50,00
0,50
0,00
0,00
0
2
4
6
8
10
time (ms)
12
14
16
18
20
Figure 57. Input Voltage and On−time vs Time (example with FSW = 100 kHz, Pin =150 W, VAC = 230 V, L = 200 mH)
Regulation Block and Low Output Voltage Detection
A transconductance error amplifier with access to the
inverting input and output is provided. It features a typical
transconductance gain of 200 mS and a maximum
capability of ±20 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and
monitored by the inverting input (feedback pin − Pin 4).
The bias current is minimized (less than 500 nA) to allow
the use of a high impedance feedback network. The output
of the error amplifier is pinned out for external loop
compensation (Pin 3). Typically a capacitor in the range of
100 nF, is applied between Pin 3 and ground, to set the
regulation bandwidth below 20 Hz, as need in PFC
applications.
Vout Low
Detect
0.955*Vref
+
Vref
+
FB
Vcontrol
The swing of the error amplifier output is limited within
an accurate range:
• It is forced above a voltage drop (VF) by some circuitry.
• It is clamped not to exceed 3.0 V + the same VF voltage
drop.
Hence, VPin3 features a 3 V voltage swing. VPin3 is then
offset down by (VF) and divided by three before it connects
to the “VTON processing block” and the PWM section.
Finally, the output of the regulation is a signal (“VREGUL”
of the block diagram) that varies between 0 and 1 V.
VREGUL
200 mA
pfcOK
1V
Error
Amplifier
±20 mA
OVLflag1
+
VF
OFF
2R
+
VF
VREGUL
3V
0V
R
VF
Figure 58. Regulation Block
3 V + VF
VCONTROL
Figure 59. Correspondence between VCONTROL
and VREGUL
200 mA current source to speed−up the charge of the
compensation capacitor (Cpin3). Finally, it is like if the
comparator multiplied the error amplifier gain by 10.
One must note that this circuitry for undershoots limitation,
is not enabled during the startup sequence of the PFC stage
but only once the converter has stabilized (that is when the
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
undershoots. Overshoots are limited by the Overvoltage
Protection (see OVP section). To contain the undershoots, an
internal comparator monitors the feedback (VPin4) and when
VPin4 is lower than 95.5% of its nominal value, it connects a
www.onsemi.com
20
NCP1605, NCP1605A, NCP1605B
“pfcOK” signal of the block diagram, is high). This is
because, at the beginning of operation, the Pin 3 capacitor
must charge slowly and gradually for a soft−startup.
Remark: As shown in block diagram, the circuitry for
undershoots limitation is disabled as long as Pin 3 detects
standby conditions (VPin3 < 300 mV). This is to suppress the
risk of audible noise in standby thanks to the soft–start that
softens the bursts.
Hence, one obtains the Follower Boost characteristics. The
“Follower Boost” is an operation mode where the
pre−converter output voltage stabilizes at a level that varies
linearly versus the ac line amplitude. This technique aims at
reducing the gap between the output and input voltages to
optimize the boost efficiency and minimize the cost of the
PFC stage (refer to the MC33260 data sheet for more
information, at:
http://www.onsemi.com/pub/Collateral/MC33260−D.PDF ).
Remark: the timing capacitor applied to Pin 7 is
discharged and maintained grounded when the drive is low.
Furthermore, the circuit compares the Pin 7 voltage to an
internal reference 50 mV and prevents the PWM latch from
being set as long as VPin7 is higher than this low threshold.
This is to guarantee that the timing capacitor is properly
discharged before starting a new cycle.
On−Time Control for Maximum Power Adjustment
As aforementioned, the NCP1605 processes the error
amplifier output voltage to form a signal (VTON) that is used
by the PWM section to control the on−time. (VTON)
compensates the relative weight of the dead−time sequences
measured during the precedent current cycles. During the
conduction time of the MOSFET, Pin 7 sources a current that
is proportional to the square of the voltage applied to Pin 4
(feedback pin). Practically, as Pin 4 receives a portion of the
output voltage (VOUT), IPin7 is proportional to the square of
VOUT.
The MOSFET turns off when the Pin 7 voltage exceeds
VTON. Hence, the MOSFET on−time (t1) is given by:
t1 +
Current Sense and Zero Current Detection
The NCP1605 is designed to monitor a negative voltage
proportional to the coil current. Practically, a current sense
resistor (RCS) is inserted in the return path to generate a
negative voltage proportional to the coil current (VCS). The
circuit uses VCS for two functions: the limitation of the
maximum coil current and the detection of the core reset
(coil demagnetization). To do so, the circuit incorporates
an operational amplifier that sources the current necessary
to maintain the CS pin voltage null (refer to Figure 60). By
inserting a resistor ROCP between the CS pin and RCS, we
adjust the CS pin current as follows:
Cpin7 VTON
where k is a constant.
k VOUT 2
The coil current averaged over one switching period is:
t ICOIL u T + IIN(t) +
VIN t1 (t1 ) t2)
T
2L
Where IIN(t) and VIN(t) are the instantaneous input current
and voltage, respectively, t2 is the core reset time and T is the
switching period. Hence, the instantaneous input power is
given by the following equation:
* [RCS ICOIL] ) [ROCP Ipin5] + Vpin5 [ 0
Which leads to:
R
Ipin5 + CS ICOIL
ROCP
Cpin7 VIN2 VTON (t1 ) t2)
PIN(t) + VIN(t)IIN(t) +
@
T
2 L k VOUT 2
In other words, the Pin 5 current is proportional to the coil
current.
IPin5 is utilized as follows:
• If IPin5 exceeds 250 mA, an overcurrent is detected and
the PWM latch is reset. Hence, the maximum coil
current is:
As aforementioned, we have: VTON (t1 + t2)/T = VREGUL
where VREGUL is the signal outputted by the regulation
block. Hence, the average input power is:
t PIN u+
Cpin7 Vac 2
V
2 L k VOUT 2 REGUL
R
(ICOIL)max + OCP 250 mA
RCS
The maximum value of VREGUL being 1 V, the maximum
power that can be delivered is:
t PIN u MAX +
Cpin7 Vac 2
1V
2 L k VOUT2
•
To the light of the last equations, one can note that the PFC
power capability is inversely proportional to the square of the
output voltage. One sees that if the power demand is too high
to keep the regulation, (VREGUL=1V) and the power delivery
depends on the output voltage level that stabilizes to the
following value:
VOUT +
The propagation delay (Ipin5 higher than 250 mA) to
(drive output low) is in the range of 100 ns, typically.
The Pin 5 current is internally copied and sourced by
Pin 6. Place a resistor (RPin6) between Pin 6 and ground
to build a voltage proportional to the coil current. The
circuit detects the core reset when VPin6 drops below
100 mV, typically. The Pin 6 voltage equating:
Vpin6 +
Ǹ
Cpin7 1 V
V
2 L k h POUT ac
Rpin6 @ Rcs
@ ICOIL ,
Rcs
the coil current threshold for zero current detection is:
Where:
• POUT is the output power.
• And h is the efficiency.
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21
NCP1605, NCP1605A, NCP1605B
100 mV
400 W
ROCP
(ICOIL)zcd +
100 mV +
@ (ICOIL)MAX +
@ (ICOIL)MAX
Rpin6 @ RCS
Rpin6
Rpin6 @ 250 mA
Rdrv
Rzcd
Vin
D1
Icoil
6
EMI
Filter
Vdd
Cin
Current Mirror
Vdd
Ics
L1
CSout
100 mV
+
-
ZCD
Rsense
output
buffer
M1
Vcc
DRV
Cbulk
LOAD
10
Ics
outON
Vzcd
Ics > 250 mA ≥ OCP
Rocp CSin
Vout
S
LdT Q
R
DT
OCP
(RESET of the PWM latch)
5
Icoil
Figure 60. Current Sense Block
The CS block performs the overcurrent protection and the zero current detection.
• It is worth highlighting that the circuit permanently
The propagation delay (VPin6 lower than 100 mV) to (drive
output high) is in the range of 300 ns, typically.
The Zero Current Detection:
• Is used to detect the dead−time sequences (“DT” high)
and hence, to process (VTON) from the error amplifier
output (VCONTROL). In other words, this is an input of
the on−time modulation block.
• Prevents the MOSFET from turning on as long as the
“DT” and “ZCD” signals are low. This is the case as
long as some current flows through the coil. This
delaying action on the output stage tends to make the
MOSFET turn on at the valley. To further optimize the
valley switching, one can apply the voltage of an
auxiliary winding to Pin 6 (CSOUT). The voltage is
compared to an internal 100 mV reference, so that
ZCD turns high only if (VPin6 < 100 mV).
•
senses the coil current and that it prevents any turn on
of the power switch as long as the core is not reset.
This feature protects the MOSFET from the possible
excessive stress it could suffer from, if it was allowed
to turn on while a huge current flows through the coil.
In particular, this scheme effectively protects the PFC
stage during the startup phase when huge in−rush
currents charge the output capacitor.
In addition this detection method does not require any
auxiliary winding. A simple coil can then be used in
the PFC stage.
It is recommended to:
1. Keep ROCP equal to or lower than 5 kW
2. Choose RZCD as high as possible but not bigger
than (3 x ROCP). This is to avoid that the Pin 6
leakage prevents a proper zero current detection.
For instance, if ROCP is 2.2 kW, RZCD should not
exceed 6.6 kW.
Remarks:
• A resistor can be placed between Pin 6 and ground to
increase the ZCD precision.
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22
NCP1605, NCP1605A, NCP1605B
3. Place a resistor RDRV between the drive pin and
Pin 6 to ease the circuit detection by creating
some over−riding at the turn on instant. RDRV
should be selected in the range of 3 times RZCD.
For instance, if RZCD is 6.2 kW, a 22 kW resistor
can be used for RDRV.
NCP1605 dedicates one specific pin for the undervoltage
and overvoltage protections. The NCP1605 configuration
allows the implementation of two separate feedback
networks (see Figure 62):
− One for regulation applied to Pin 4.
− Another one for the OVP function.
Overvoltage Protection
While PFC circuits often use one single pin for both the
Overvoltage Protection (OVP) and the feedback, the
Vout (bulk voltage)
Rout1
1 16
2 15
3 14
Rout3
FB
Vout (bulk voltage)
HV
1 16
2 15
Rout1
OVP
3 14
FB
4 13
5 12
Rout2
6 11
7 10
8
8
9
Rovp2
9
Figure 62. Configuration with Two Separate
Feedback Networks
PfcOK / REF5V Signal
The double feedback configuration offers some
up−graded safety level as it protects the PFC stage even if
there is a failure of one of the two feedback arrangements.
However, if wished, one single feedback arrangement is
possible as portrayed by Figure 61. The regulation and
OVP blocks having the same reference voltage, the
resistance ratio Rout2 over Rout3 adjusts the OVP
threshold. More specifically,
The bulk regulation voltage is:
The NCP1605 can communicate with the downstream
converter. The signal “pfcOK/REF5V is high (5 V) when
the PFC stage is in normal operation (its output voltage is
stabilized at the nominal level) and low otherwise.
More specifically, “pfcOK/REF5V” is low:
• During the PFC stage startup, that is, as long as the
output voltage has not yet stabilized at the right level.
The startup phase is detected by the latch “LSTUP” of the
block diagram. “LSTUP” is set during each “off” phase so
that its output (“STUP”) is high when the circuit enters
an active phase. The latch is reset when the error
amplifier stops charging its output capacitor, that is,
when the output voltage of the PFC stage has reached its
desired regulation level. At that moment, “STUP” falls
down to indicate the end of the startup phase.
• In case of a condition preventing the circuit from
operating properly, i.e., during the VCC charge by the
high voltage startup current source, in a Brown−out
case or when one of the following major faults turns
off the circuit:
− Incorrect feeding of the circuit (“UVLO” high when
VCC
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