NCP1606

NCP1606 Cost Effective Power Factor Controller The NCP1606 is an active power factor controller specifically designed for use as a pre−converter in electronic ballasts, ac−dc adapters and other medium power off line converters (typically up to 300 W). It embeds a Critical Conduction Mode (CRM) scheme that substantially exhibits unity power factor across a wide range of input voltages and power levels. Housed in a DIP8 or SOIC−8 package, the NCP1606 minimizes the number of external components. Its integration of comprehensive safety protection features makes it an excellent driver for rugged PFC stages. General Features http://onsemi.com MARKING DIAGRAMS 1 SO−8 D SUFFIX CASE 751 8 1606x ALYW G 8 • • • • • • • • • • • • • “Unity” Power Factor No Need for Input Voltage Sensing Latching PWM for Cycle by Cycle On Time Control (Voltage Mode) High Precision Voltage Reference (±1.5% over the VCC and Temp. Ranges) Very Low Startup Current Consumption (≤ 40 mA) Low Typical Operating Current (2.1 mA) −500 mA / +800 mA Totem Pole Gate Driver Undervoltage Lockout with Hysteresis Pin to Pin Compatible with Industry Standards 1 8 1 DIP−8 P SUFFIX CASE 626 x A L, WL Y, YY W, WW G or G NCP1606x AWL YYWWG Safety Features = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Programmable Overvoltage Protection Protection against Open Loop (Undervoltage Protection) Accurate and Programmable On Time Limitation Overcurrent Limitation PIN CONNECTION Feedback Control Ct CS (Top View) VCC Drive Ground ZCD/STDWN Typical Applications • Electronic Light Ballast • AC Adapters, TVs, Monitors • All Off Line Appliances Requiring Power Factor Correction LBOOST ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. DBOOST RZCD + AC Line EMI Filter Cin ROUT1 Ccomp ROUT2 Ct 1 2 3 4 NCP1606 FB V CC VOUT LOAD (Ballast, SMPS, etc.) + CBULK VCC 8 7 6 5 RSENSE Ctrl DRV Ct GND CS ZCD Figure 1. Typical Application © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 3 1 Publication Order Number: NCP1606/D NCP1606 VCC VOUT Shutdown nPOK ROUT1 FB ROUT2 − + 300 mV UVP ESD (Enable EA) Dynamic OVP Isink>Iovp IEAsink VDD Enable Measure Fault + + − UVLO VDD Reg + 2.5 V CCOMP Control AC IN LBOOST Ct Ct ESD VDD 270 mA ESD Add VEAL Offset CS RSENSE ESD VDD VCL(NEG) Active Clamp ZCD RZCD VCL(POS) Clamp 2.3 V + − − + 1.6 V + + VCC VDD VDDGD CBULK E/A − ESD + DBOOST VCONTROL Static OVP VEAL Clamp Static OVP is triggered when clamp is activated. VEAH Clamp nPOK PWM − + SQ RQ VCC SQ RQ Off Timer Reset Shutdown VDDGD SQ RQ SQ RQ POK nPOK VDDGD GND Demag SQ RQ DRV DRV LEB + + + + − OCP VCS(limit) + − 200 mV *All SR Latches are Reset Dominant *All values shown are typical only. Refer to the “Electrical Characteristics” for complete specifications. Figure 2. Block Diagram http://onsemi.com 2 NCP1606 PIN FUNCTION DESCRIPTION Pin Number 1 Name Feedback (FB) Function The FB pin makes available the inverting input of the internal error amplifier. A simple resistor divider scales and delivers the output voltage to the FB pin to maintain regulation. The feedback information is also used for the programmable overvoltage and undervoltage protections. The regulation block output is available on this pin. A compensation network is placed between FB and Control to set the loop bandwidth low enough to yield a high power factor ratio and a low THD. The Ct pin sources a 270 mA current to charge an external timing capacitor. The circuit controls the power switch on time by comparing the Ct voltage to an internal voltage derived from the regulation block. This pin limits the pulse by pulse current through the switch MOSFET when connected as show in Figure 1. When the voltage exceeds 1.7 V (A version) or 0.5 V (B version), the drive turns off. The maximum switch current can be adjusted by changing the sense resistor. The voltage of an auxiliary winding should be applied to this pin to detect the moment when the coil is demagnetized for critical conduction mode operation. Ground ZCD to shutdown the part. Connect this pin to the pre−converter ground. The powerful integrated driver is suitable to effectively switch a high gate charge power MOSFET. This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V (typ) and turns off when VCC goes below 9.5 V (typ). After startup, the operating range is 10.3 V to 20 V. 2 3 4 Control Ct Current Sense (CS) Zero Current Detection (ZCD) Ground (GND) Drive (DRV) VCC 5 6 7 8 MAXIMUM RATINGS Pin 7 7 8 1, 2, 3, 4, 5 Output Drive Capability Maximum DRV Pin Voltage Power Supply Input Input Voltage Power Dissipation and Thermal Characteristics P suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction−to−Air D suffix, Plastic Package, Case 751 Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction−to−Air Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Rating Symbol IDRV(source) IDRV(sink) VDRV VCC VIN Value +500 −800 −0.3, +20 −0.3, +20 −0.3, +9 Unit mA mA V V V PD(DIP) RqJA(DIP) PD(SO) RqJA(SO) TJ TJmax TSmax TLmax 800 100 450 178 −25 to +125 150 −65 to 150 300 mW °C/W mW °C/W °C °C °C °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pins 1−8 (except pin 7): Human Body Model 2000 V per Mil−Std−883, Method 3015. Machine Model Method 200 V Pin 7: Human Body Model 2000 V per Mil−Std−883, Method 3015. Machine Model Method 170 V 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. http://onsemi.com 3 NCP1606 ELECTRICAL CHARACTERISTICS (Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −25°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV = 1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open) Symbol VCC UNDERVOLTAGE LOCKOUT SECTION VCC(on) VCC(off) HUVLO ICC(startup) ICC1 ICC2 ICC(fault) VCC Startup Threshold (Undervoltage Lockout Threshold, Vcc rising) VCC Disable Voltage after Turn On (Undervoltage Lockout Threshold, VCC falling) Undervoltage Lockout Hysteresis Icc consumption during startup: 0 V < VCC < VCC(on) − 200 mV Icc consumption after turn on at VCC = 12 V, No Load, 70 kHz switching Icc consumption after turn on at VCC = 12 V, 1 nF Load, 70 kHz switching Icc consumption after turn on at VCC = 12 V, 1 nF Load, no switching (such as during OVP fault, UVP fault, or grounding ZCD) Voltage Reference @ TJ = 25 °C over temperature range (−25°C to +125°C) Vref Line Regulation from VCC(on) + 200 mV < VCC < 20 V, @ TJ = 25°C Error Amplifier Current Capability: Sink (Control = 4 V, VFB = 2.6 V): Source (Control = 4 V, VFB = 2.4 V): Open Loop, Error Amplifier Gain (Note 3) Unity Gain Bandwidth (Note 3) FB Bias Current @ VFB = 3 V Control Pin Bias Current @ FB = 0 V and Control = 4.0 V. VCONTROL @ IEASOURCE = 0.5 mA, VFB = 2.4 V VCONTROL @ IEASINK = 0.5 mA, VFB = 2.6 V VEA(diff) = VEAH − VEAL. Difference between max and min Control voltages Overcurrent Protection Threshold: NCP1606A NCP1606B Leading Edge Blanking duration Overcurrent protection propagation delay. CS bias current @ VCS = 2 V Zero Current Detection Threshold (VZCD rising) Zero Current Detection Threshold (VZCD falling) VZCDH − VZCDL Maximum ZCD bias Current @ VZCD = 5 V Upper Clamp Voltage @ IZCD = 2.5 mA Current Capability of the Positive Clamp at VZCD = VCL(POS) + 200 mV: Negative Active Clamp Voltage @ IZCD = −2.5 mA Current Capability of the Negative Active Clamp: in normal mode (VZCD = 300 mV) in shutdown mode (VZCD = 100 mV) 11 8.7 2.2 − − − − 12 9.5 2.5 20 1.4 2.1 1.2 13 10.3 2.8 40 2.0 3 1.6 V V V mA mA mA mA Rating Min Typ Max Unit DEVICE CONSUMPTION REGULATION BLOCK (ERROR AMPLIFIER) VREF VREF(line) IEA 2.475 2.465 −2 8.0 −2 − − −500 −1 4.9 1.85 3.0 2.50 2.50 − 17 −6.0 80 1 − − 5.3 2.1 3.2 2.525 2.535 2 − − − − 500 1 5.7 2.4 3.4 dB MHz nA mA V V V V 1.6 0.45 150 40 −1 2.1 1.5 500 −2 5 5.0 0.45 2.5 35 1.7 0.5 250 100 − 2.3 1.6 700 − 5.7 8.5 0.6 3.7 70 1.8 0.55 350 170 1 2.5 1.8 900 +2 6.5 − 0.75 5.0 100 ns ns mA V V mV mA V mA V mA mA V mV mA GOL BW IFB IControl VEAH VEAL VEA(diff) VCS(limit) CURRENT SENSE BLOCK tLEB tCS ICS VZCDH VZCDL VZCDHYS IZCD VCL(POS) ICL(POS) VCL(NEG) ICL(NEG) ZERO CURRENT DETECTION 3. Parameter characterized and guaranteed by design, but not tested in production. http://onsemi.com 4 NCP1606 ELECTRICAL CHARACTERISTICS (Unless otherwise specified: For typical values, TJ = 25°C. For min/max values, TJ = −25°C to +125°C, VCC = 12 V, FB = 2.4 V, CDRV = 1 nF, Ct = 1 nF, CS = 0 V, Control = open, ZCD = open) Symbol VSDL VSDH VSDHYS tZCD tSYNC tSTART ICHARGE tCT(discharge) VCTMAX tPWM IOVP Shutdown Threshold (VZCD falling) Enable Threshold (VZCD rising) Shutdown Comparator Hysteresis Zero current detection propagation delay Minimum detectable ZCD pulse width Drive off restart timer Charge Current (VCT = 0 V) Time to discharge a 1 nF Ct capacitor from VCT = 3.4 V to 100 mV. Maximum Ct level before DRV switches off Propagation delay of the PWM comparator Dynamic overvoltage protection (OVP) triggering current: NCP1606A NCP1606B @ TJ = 25°C NCP1606B @ TJ = −25°C to +125°C Hysteresis of the dynamic OVP current before the OVP latch is released: NCP1606A NCP1606B Static OVP Threshold Voltage Undervoltage protection (UVP) threshold voltage Gate Drive Resistance: ROH @ ISOURCE = 100 mA ROH @ ISOURCE = 20 mA ROL @ ISINK = 100 mA ROL @ ISINK = 20 mA Drive voltage rise time from 10% VCC to 90% VCC with CDRV = 1 nF and VCC = 12 V. Drive voltage fall time from 10% VCC to 90% VCC with CDRV = 1 nF and VCC = 12 V. Driver output voltage at VCC = VCC(on) − 200 mV and Isink = 10 mA 0.25 Rating Min 150 − − − − 75 243 − 2.9 − Typ 200 290 90 100 70 180 270 − 3.2 150 Max 250 350 − 170 − 300 297 100 3.3 220 Unit mV mV mV ns ns ms mA ns V ns mA 34 9.0 8.7 − − 40 10.4 − 30 8 VEAL + 100 mV 0.3 0.4 45 11.8 12.1 mA − − V V W − − − − − − − 12 12 6 6 30 25 − 18 18 10 10 80 70 0.2 ns ns V RAMP CONTROL OVER AND UNDERVOLTAGE PROTECTION IOVP(HYS) VOVP VUVP GATE DRIVE SECTION ROH ROL trise tfall VOUT(start) 3. Parameter characterized and guaranteed by design, but not tested in production. http://onsemi.com 5 NCP1606 TYPICAL CHARACTERISTICS OSCILLATOR CHARGE CURRENT (mA) 274 272 270 268 266 264 262 260 −50 −25 0 25 50 75 100 125 150 ON TIME (ms) 14 12 Ct = 1 nF 10 8 6 4 2 0 0 1 2 3 VCONTROL (V) 4 5 6 TEMPERATURE (°C) Figure 3. Oscillator Charge Current (ICHARGE) vs. Temperature 3.30 3.25 3.20 3.15 3.10 3.05 3.00 −50 PWM PROPAGATION DELAY (ns) 170 Figure 4. Typical On Time (TON) vs. VCONTROL Level MAXIMUM Ct LEVEL (V) 160 150 140 −25 0 25 50 75 100 125 150 130 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Maximum Ct Level (VCTMAX) vs. Temperature 2.505 REFERENCE VOLTAGE (V) 2.500 2.495 GAIN (dB) 2.490 2.485 2.480 2.475 2.470 −50 −25 0 25 50 75 100 125 150 100 80 Figure 6. PWM Comparator Propagation Delay (tPWM) vs. Temperature 200 160 GAIN 60 PHASE 40 20 0 −20 10E+0 100E+0 120 80 40 0 −40 1E+6 10E+6 PHASE (°) 1E+3 10E+3 100E+3 TEMPERATURE (°C) FREQUENCY (Hz) Figure 7. Reference Voltage (VREF) vs. Temperature Figure 8. Error Amplifier Open Loop Gain (GOL) and Phase http://onsemi.com 6 NCP1606 TYPICAL CHARACTERISTICS 45 DYNAMIC OVP CURRENT (mA) 40 35 30 25 20 −50 IOVP DYNAMIC OVP CURRENT (mA) 12 11 IOVP 10 9 8 7 −50 IOVP(HYS) IOVP(HYS) −25 0 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 9. Overvoltage Activation Current vs. Temperature for the A Version SWITCHING SUPPLY CURRENT (ICC2) (mA) 2.20 STARTUP CURRENT (mA) 2.15 2.10 2.05 2.00 1.95 1.90 −50 24 22 20 18 16 14 12 Figure 10. Overvoltage Activation Current vs. Temperature for the B Version −25 0 25 50 75 100 125 150 10 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Supply Current (ICC2) vs. Temperature 13 VCC(ON) SUPPLY VOLTAGE (V) RESTART TIMER (ms) 12 11 10 9 8 −50 190 200 Figure 12. Startup Current (ICC_startup) vs. Temperature 180 VCC(OFF) 170 −25 0 25 50 75 100 125 150 160 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 13. Supply Voltage Thresholds vs. Temperature Figure 14. Restart Timer (tSTART) vs. Temperature http://onsemi.com 7 NCP1606 TYPICAL CHARACTERISTICS 18 OUTPUT DRIVE RESISTANCE (W) LEB FILTER DURATION (ns) 125 150 16 14 12 10 8 6 4 2 0 −50 −25 0 25 50 75 100 ROL ROH 280 270 260 250 240 −50 −25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Output Gate Drive Resistance (ROH and ROL) at 100 mA vs. Temperature A VERSION OVERCURRENT THRESHOLD (V) 1.710 1.705 1.700 1.695 1.690 1.685 1.680 1.675 1.670 −50 −25 0 25 50 75 B A Figure 16. LEB Duration (tLEB) vs. Temperature B VERSION OVERCURRENT THRESHOLD (V) VSDH VSDL 50 0.520 0.515 0.510 0.505 0.500 0.495 0.490 0.485 100 125 0.480 150 TEMPERATURE (°C) Figure 17. Overcurrent Threshold (VCS_Limit) vs. Temperature 0.320 SHUTDOWN THRESHOLD (V) −25 0 25 50 75 100 125 150 0.315 UVP THRESHOLD (V) 0.310 0.305 0.300 0.295 0.290 0.285 0.280 −50 0.35 0.30 0.25 0.20 0.15 −50 −25 0 25 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Undervoltage Protection Threshold (VUVP) vs. Temperature Figure 19. Shutdown Thresholds vs. Temperature http://onsemi.com 8 NCP1606 Introduction The NCP1606 is a voltage mode power factor correction (PFC) controller designed to drive cost effective pre−converters to meet input line harmonic regulations. This controller operates in critical conduction mode (CRM) for optimal performance in applications up to about 300 W. Its voltage mode scheme enables it to obtain unity power factor without the need for a line sensing network. The output voltage is accurately controlled by a high precision error amplifier. The controller also implements a comprehensive array of safety features for robust designs. The key features of the NCP1606 are as follows: • Constant on time (Voltage Mode) CRM operation. High power factor ratios are easily obtained without the need for input voltage sensing. This allows for optimal standby power consumption. • Accurate and Programmable On Time Limitation. The NCP1606 using an accurate current source and an external capacitor to generate the on time. • High Precision Voltage Reference. The error amplifier reference voltage is guaranteed at 2.5 V ±1.5% over process, temperature, and VCC levels. This results in very accurate output voltages. • Very Low Startup Consumption. The circuit consumption is reduced to a minimum (< 40 mA) during the startup phase which allows fast, low loss, charging of VCC. The architecture of the NCP1606 gives a controlled undervoltage lockout level and provides ample VCC hysteresis during startup. • Powerful Output Driver. A −500 mA / +800 mA totem pole gate driver is used to provide rapid turn on and turn off times. This translates into improved efficiencies and the ability to drive higher power MOSFETs. Additionally, a combination of active and passive circuitry is used to ensure that the driver output voltage does not float high while VCC is below its turn on level. • Programmable Overvoltage Protection (OVP). The adjustable OVP feature protects the PFC stage against excessive output overshoots that could damage the application. These events can typically occur during the startup phase or when the load is abruptly removed. The NCP1606B gives a lower OVP threshold, which can further reduce the application’s standby power loss. • Protection against Open Loop (Undervoltage Protection). Undervoltage protection (UVP) disables the PFC stage when the output voltage is excessively low. This also protects the circuit in case of a failure in the feedback network: if no voltage is applied to FB because of a bad connection, UVP is activated and shuts down the pre−converter. • Overcurrent Limitation. The peak current is accurately limited on a pulse by pulse basis. The level is adjustable by modifying the switch sense resistor. The • NCP1606B uses a lower overcurrent threshold, which can further reduce the application’s power dissipation. An integrated LEB filter reduces the chance of noise prematurely triggering the overcurrent limit. Shutdown Features. The PFC pre−converter can be easily placed in a shutdown mode by grounding either the FB pin or the ZCD pin. During this mode, the ICC current consumption is reduced and the error amplifier is disabled. Application information Most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line (Figure 20). This DC voltage is then processed by additional circuitry to drive the desired output. Rectifiers AC Line + Bulk Storage Capacitor Converter Load Figure 20. Typical Circuit without PFC This simple rectifying circuit draws power from the line when the instantaneous ac voltage exceeds the capacitor voltage. Since this occurs near the line voltage peak, the resulting current draw is non sinusoidal and contains a very high harmonic content. This results in a poor power factor (typically < 0.6) and consequently, the apparent input power is much higher than the real power delivered to the load. Additionally, if multiple devices are tied to the same input line, the effect is magnified and a “line sag” effect can be produced (see Figure 21). Vpk Rectified DC 0 AC Line Voltage 0 AC Line Current Line Sag Figure 21. Typical Line Waveforms without PFC Increasingly, government regulations and utility requirements necessitate control over the line current harmonic content. To meet this need, power factor correction is implemented with either a passive or active circuit. Passive circuits usually contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. Active circuits incorporate some form of http://onsemi.com 9 NCP1606 a high frequency switching converter which regulates the input current to stay in phase with the input voltage. These circuits operate at a higher frequency and so they are smaller, lighter in weight, and more efficient than a passive circuit. With proper control of an active PFC stage, almost any complex load can be made to appear in phase with the Rectifiers ac line, thus significantly reducing the harmonic current content. Because of these advantages, active PFC circuits have become the most popular way to meet harmonic content requirements. Generally, they consist of inserting a PFC pre−regulator between the rectifier bridge and the bulk capacitor (Figure 22). Converter PFC Preconverter AC Line + High Frequency Bypass Capacitor + NCP1606 Bulk Storage Capacitor Load Figure 22. Active PFC Pre−Converter with the NCP1606 The boost (or step up) converter is the most popular topology for active power factor correction. With the proper control, it produces a constant voltage while drawing a sinusoidal current from the line. For medium power ( Iovp Measure Icontrol VDD VEAL Static OVP Clamp Static OVP is triggered when clamp is activated. Fault ROUT2 Figure 34. OVP and UVP Circuit Blocks When the output voltage is in steady state, ROUT1 and ROUT2 regulate the FB voltage to 2.5 V. Also, during this equilibrium state, no current flows through the compensation capacitor (“CCOMP” of Figure 1). Therefore: • The ROUT1 current is: (V )nom * 2.5 V IR + OUT R OUT1 OUT1 (eq. 6) • Therefore, the error amplifier sinks: (eq. 11) (V ) nom ) DV OUT−2.5 V 2.5 V IR −I R + OUT − R OUT2 R OUT1 OUT1 OUT2 The combination of equations (4) and (7) leads to a very simple expression of the current sunk by the error amplifier: IPIN2 + I R OUT1 where (VOUT)nom is the nominal output voltage. • The ROUT2 current is: IR OUT2 * IR OUT2 + DV OUT R OUT1 (eq. 12) + 2.5 V R OUT2 (eq. 7) • And since no current flows through CCOMP, IR OUT1 + IR OUT2 å (V OUT)nom * 2.5 V + 2.5 V ROUT2 R OUT1 (eq. 8) Hence, the current absorbed by pin 2 (ICONTROL) is proportional to the output voltage excess. The circuit senses this current and disables the drive (pin 7) when ICONTROL exceeds IOVP (typically 40 mA in NCP1606A, 10.4 mA in NCP1606B). This gives the OVP threshold as: (VOUT) OVP + (VOUT) nom ) (R OUT1 @ I OVP) Under stable conditions, these equations are true. Conversely when VOUT is not at its nominal level, the output of the error amplifier sinks or sources the current necessary to maintain 2.5 V on pin 1. In particular, in the case of an overvoltage condition: • The error amplifier maintains 2.5 V on pin 1, and the ROUT2 current remains: IR + 2.5 V R OUT2 OUT2 (eq. 9) By simply adjusting ROUT1, the OVP limit can be easily set. Therefore, one can compute the ROUT1 and ROUT2 resistances using the following procedure: 1. Select ROUT1 to set the desired overvoltage level: ROUT1 + (V OUT)OVP * (VOUT) nom I OVP • The ROUT1 current is: (eq. 10) For instance if implementing the NCP1606B, and 420 V is the maximum output level and 400 V is the nominal output level, then ROUT1 + 420 * 400 + 1.9 MW 10.4 mA IR OUT1 + V OUT−2.5 V (V )nom ) DVOUT−2.5 V + OUT R OUT1 R OUT1 2. Select ROUT2 to adjust the regulation level: where DVOUT is the output voltage excess. http://onsemi.com 16 NCP1606 ROUT2 + 2.5 V @ ROUT1 V OUT(nom) * 2.5 V For the above example, this leads to: ROUT2 + 2.5 V @ 1.9 MW + 12.0 kW. 400 V * 2.5 V STATIC OVERVOLTAGE PROTECTION If the OVP condition lasts for a long time, it may happen that the error amplifier output reaches its minimum level (i.e. Control = VEAL). It would then not be able to sink any current and maintain the OVP fault. Therefore, to avoid any discontinuity in the OVP disabling effect, the circuit incorporates a comparator which detects when the lower level of the error amplifier is reached. This event, called “static OVP”, disables the output drives. Once the OVP event is over, and the output voltage has dropped to normal, then Control rises above the lower limit and the driver is re−enabled (Figure 18). Vout(nom) Vout Furthermore, the NCP1606 incorporates a novel startup sequence which ensures that undervoltage conditions are always detected at startup. It accomplishes this by waiting approximately 180 ms after VCC reaches VCC(on) before enabling the error amplifier (Figure 19). During this wait time, it looks to see if the feedback (FB) voltage is greater than the UVP threshold. If not, then the controller enters a UVP fault and leaves the error amplifier disabled. However, if the FB pin voltage increases and exceeds the UVP level, then the controller will start the application up normally. VCC(on) VCC(off) VCC VOUT(nom) VOUT FB 2.5 V VUVP VEAH Drive VeaH Vcontrol VeaL IovpH Icontrol IovpL Dynamic OVP VEAL UVP UVP Wait Control UVP Fault is “Removed” UVP Wait Figure 36. The NCP1606’s Startup Sequence with and without a UVP Fault The voltage on the output which exits a UVP fault is given by: VOUT (UVP) Static OVP + R OUT1 ) R OUT2 @ 300 mV R OUT2 (eq. 13) Figure 35. OVP Timing Diagram NCP1606 Undervoltage Protection (UVP) If ROUT1 = 1.9 MW and ROUT2 = 12.0 kW, then the VOUT UVP threshold is 48 V. This corresponds to an input voltage of approximately 34 Vac. Overcurrent Protection (OCP) When the PFC stage is plugged in, the output voltage is forced to roughly equate the peak line voltage. The NCP1606 detects an undervoltage fault when this output voltage is unusually low, such that the feedback voltage is below VUVP (300 mV typ). In an UVP fault, the drive output and error amplifier (EA) are disabled. The latter is done so that the EA does not source a current which would increase the FB voltage and prevent the UVP event from being accurately detected. The UVP feature helps to protect the application if something is wrong with the power path to the bulk capacitor (i.e. the capacitor cannot charge up) or if the controller cannot sense the bulk voltage (i.e. the feedback loop is open). A dedicated pin on the NCP1606 senses the peak current and limits the driver on time if this current exceeds VCS(limit). This level is 1.7 V (typ) on the NCP1606A and 0.5 V (typ) on the NCP1606B. Therefore, the maximum peak current can be adjusted by changing Rsense according to: Ipeak + V CS(limit) R sense (eq. 14) An internal LEB filter (Figure 20) reduces the likelihood of switching noise falsely triggering the OCP limit. This filter blanks out the first 250 ns (typical) of the current sense signal. If additional filtering is necessary, a small RC filter can be added between Rsense and the CS pin. http://onsemi.com 17 NCP1606 SHUTDOWN MODE DRIVE CS LEB + + − Imax OCP RSENSE optional Figure 37. OCP Circuitry with Optional External RC Filter The NCP1606 allows for two methods to place the controller into a standby mode of operation. The FB pin can be pulled below the UVP level (0.3 V typical) or the ZCD pin can be pulled below the VSDL level (typically 200 mV). If the FB pin is used for shutdown (Figure 21(a)), care must be taken to ensure that no significant leakage current exists on the shutdown circuitry. This could impact the output voltage regulation. If the ZCD pin is used for shutdown (Figure 38(b)), then any parasitic capacitance created by the shutdown circuitry will add to the delay in detecting the zero inductor current event. LBOOST VOUT ROUT1 NCP1606 Ccomp 1 FB 2 Ctrl 3 Ct Shutdown ROUT2 4 Cs VCC 8 DRV 7 GND 6 ZCD 5 NCP1606 1 FB 2 Ctrl 3 Ct 4 Cs VCC 8 DRV 7 GND 6 ZCD 5 RZCD Shutdown Figure 21(a) Figure 21(b) Figure 38. Shutting Down the PFC Stage by Pulling FB to GND (A) or Pulling ZCD to GND (B) To activate the shutdown feature on ZCD, the internal clamp must first be overcome. This clamp will draw a maximum of ICLNEG (5.0 mA maximum) before releasing and allowing the ZCD pin voltage to drop low enough to shutdown the part (Figure 39). After shutdown, the 5 mA IZCD ~70 mA comparator includes approximately 90 mV of hysteresis to ensure noise free operation. A small current source (70 mA typ) is also activated to pull the unit out of the shutdown condition when the external pull down is released. Shutdown VSDL VSDH VCLNEG ~1 V Figure 39. Shutdown Comparator and Current Draw to Overcome Negative Clamp http://onsemi.com 18 NCP1606 BOOST DESIGN EQUATIONS Components are identified in Figure 1 RMS Input Current Iac(rms) + Ipk(max) + POUT h @ Vac(rms) h (the efficiency of only the Boost PFC stage) is generally in the range of 90 − 95% Ipk(max) occurs at the lowest line voltage. f(min) is the minimum desired switching frequency. The maximum L must be calculated at low line and high line. The maximum on time occurs at the lowest line voltage and maximum output power. The off time is greatest at the peak of the AC line voltage and approaches zero at the AC line zero crossings. Theta (q) represents the angle of the AC line voltage. Maximum Inductor Peak Current Inductor Value 2 @ 2 @ P OUT h @ Vac LL V OUT 2 2 @ Vac 2 @ Lv * Vac VOUT @ Vac @ I pk(max) @ fSW(min) tON(max) + 2 @ L @ P OUT h @ Vac LL 2 t ON V OUT Vac (rms)@ sin(q) @ 2 *1 Maximum On Time Off Time tOFF + Frequency fSW + Pin 3 Capacitor Vac (rms) 2 @ h 2 @ L @ POUT Ct w @ 1* Vac (rms) @ |sin q| @ 2 V OUT Icharge and VCTMAX are given in the NCP1606 specification table. The turns ratio must be low enough so as to trigger the ZCD comparators at high line. RZCD must be large enough so that the shutdown comparator is not inadvertently activated. 2 @ POUT @ L @ Icharge h @ Vac RMS @ V CTMAX 2 Boost Turns to ZCD Turns Ratio Resistor from ZCD winding to the ZCD pin (pin 5) Boost Output Voltage NB : N ZCD v RZCD w V OUT * Vac HL @ 2 V ZCDH Vac HL @ 2 I CL_NEG @ (N B : N ZCD) ROUT1 ) ROUT2 ROUT2 VOUT + 2.5 V @ Maximum VOUT voltage prior to OVP activation and the necessary ROUT1 and ROUT2. VOUT(max) + V OUT(nom) ) R OUT1 @ I OVP ROUT1 + V OUT(max) * V OUT(nom) IOVP 2.5 V @ ROUT1 ROUT2 + V OUT(nom) * 2.5 V + R OUT1 ) R OUT2 @ V UVP R OUT2 POUT C bulk @ 2 @ p @ fline @ VOUT 2 @ P OUT 3 @ Vac LL @ h P OUT h @ Vac LL @ VOUT 8 @ 2 @ Vac LL 3 @ p @ V OUT IOVP is given in the NCP1606 specification table. IOVP is lower for the NCP1606B, then for the NCP1606A version. Minimum output voltage necessary to exit undervoltage protection (UVP) Bulk Cap Ripple VOUT VUVP is given in the NCP1606 specification table. Use fLINE = 47 Hz for worst case at universal lines. The ripple must not exceed the OVP level for VOUT. (UVP) Vripple (pk−pk) + Inductor RMS Current IcoilRMS + Id MAX(rms) + 4 @ 3 Boost Diode RMS Current 2@ 2 p@ 2 MOSFET RMS Current IM(rms) POUT +4@ 3 h @ Vac LL @ 1* http://onsemi.com 19 NCP1606 BOOST DESIGN EQUATIONS Components are identified in Figure 1 MOSFET Sense Resistor Rsense + V CS(limit) I pk VCS(limit) is given in the NCP1606 specification table. The NCP1606B has a lower VCS(limit) level. PRsense + I M(rms) 2 @ Rsense Bulk Capacitor RMS Current Type 1 CCOMP IC(rms) + 32 @ 2 @ P OUT 2 * (ILOAD(rms)) 2 9 @ p @ Vac LL @ VOUT @ h2 CCOMP + 10 G 20 4 @ p @ f line @ ROUT1 G is the desired attenuation in decibels (dB). Typically it is 60 dB. ORDERING INFORMATION Device NCP1606APG NCP1606ADR2G NCP1606BPG NCP1606BDR2G VcsLIMIT (typ) (Note 4) 1.7 V 1.7 V 0.5 V 0.5 V IOVP (typ) (Note 4) 40 mA 40 mA 10 mA 10 mA Package PDIP−8 SOIC−8 PDIP−8 SOIC−8 Shipping† 50 Units / Rail 2500 / Tape & Reel 50 Units / Rail 2500 / Tape & Reel 4. See the electrical specifications section for complete information on VCS and IOVP. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 20 NCP1606 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 21 NCP1606 PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626−05 ISSUE L 8 5 − B− 1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 F NOTE 2 − A− L C −T− SEATING PLANE J N D K M M TA M H G 0.13 (0.005) B M The product described herein (NCP1606), may be covered by the following U.S. patents: 5,073,850 and 6,362,067. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 22 NCP1606/D