NCP4355
Secondary Side SMPS OFF
Mode Controller for Low
Standby Power
Description
The NCP4355 is a secondary side SMPS controller designed for use
in applications which require extremely low no load power
consumption. The device is capable of detecting “no load” conditions
and entering the power supply into a low consumption OFF mode.
During OFF mode, the primary side controller is turned off and energy
is provided by the output capacitors thus eliminating the power
consumption required to maintain regulation. During OFF mode, the
output voltage relaxes and is allowed to decrease to an adjustable
level. Once more energy is required, the NCP4355 automatically
restarts the primary side controller by ONOFF current that flows
through ONOFF optocoupler. The NCP4355 controls the primary
controller with an “Active ON” signal, meaning that it only drives
optocoupler current during ON mode to minimize consumption during
OFF mode.
During normal power supply operation, the NCP4355 provides
integrated voltage feedback regulation, replacing the need for a shunt
regulator. The A and C versions include a current regulation loop in
addition to voltage regulation.
The NCP4355 includes a LED driver pin (except C version)
implemented with an open drain MOSFET driven by a 1 kHz square
wave with a 12.5% duty cycle for indication purpose.
The NCP4355 is available in SOIC−8 package.
DEVICE OPTIONS
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1
SOIC−8
D SUFFIX
CASE 751
8
1
XXXXX
A
L
Y
W
G
XXXXX
ALYWG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
NCP4355A
NCP4355B
NCP4355C
Adjustable Vmin
No
Yes
Yes
Current Regulation
Yes
No
Yes
LED driver
Yes
Yes
No
See detailed ordering, marking and shipping information in the
package dimensions section on page 16 of this data sheet.
Features
•
•
•
•
•
•
Operating Input Voltage Range: 3.5 V to 36.0 V
Supply Current < 100 mA
±0.5% Reference Voltage Accuracy (TJ = 25°C)
Constant Voltage and Constant Current (A and C versions) Control
Loop
Indication LED PWM Modulated Driver (except NCP4355C)
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Offline Adapters for Notebooks, Game Stations and Printers
• High Power AC−DC Converters for TVs, Set−Top Boxes, Monitors etc.
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 1
1
Publication Order Number:
NCP4355/D
NCP4355
Current
Regulation
VCC
VCC
management
VDD
Power
RESET
VREF
ON/OFF
IBIASV
Power
RESET
VREFC
SW3
VDD
OTA
Sink only
Voltage
Regulation
FBC
ISNS
OTA
Sink only
VSNS
VREF
0.9 x VREF
IDRIVEON
IBIASV
Enabling
SW1
Off Mode
Detection
Q S
Q
VCC
10%VCC
R
LED
OFFDET
SW2
1 kHz, 12% D.C.
Oscillator
GND
PowerRESET
Figure 1. Simplified Block Diagram − NCP4355A
VCC
VCC
management
VDD
Power
RESET
VREF
SW3
VDD
OTA
Sink only
Voltage
Regulation
FBC
Power
RESET
ON/OFF
IBIASV
VSNS
VREF
0.9 x VREF
IDRIVEON
IBIASV
Enabling
SW1
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
LED
OFFDET
SW2
1 kHz, 12% D.C.
Oscillator
GND
VMIN
PowerRESET
Min Output
Voltage
Figure 2. Simplified Block Diagram − NCP4355B
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VREFM
NCP4355
Current
Regulation
VCC
VCC
management
VDD
Power
RESET
VREF
ON/OFF
IBIASV
Power
RESET
VREFC
SW3
VDD
OTA
Sink only
Voltage
Regulation
FBC
ISNS
OTA
Sink only
VSNS
VREF
0.9 x VREF
IDRIVEON
IBIASV
Enabling
SW1
Q S
Off Mode
Detection
VCC
10%VCC
Q R
OFFDET
VMIN
GND
PowerRESET
Min Output
Voltage
Figure 3. Simplified Block Diagram − NCP4355C
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VREFM
NCP4355
PIN FUNCTION DESCRIPTION
NCP4355A
NCP4355B
NCP4355C
Pin Name
Description
8
8
8
VCC
Supply voltage pin
7
7
7
GND
Ground
1
1
1
VSNS
Output voltage sensing pin, connected to output voltage divider
2
2
2
OFFDET
−
3
3
VMIN
Minimum output voltage adjustment
3
−
4
ISNS
Current sensing input for output current regulation, connect it to shunt
resistor in ground branch.
4
4
−
LED
PWM LED driver output. Connected to LED cathode with current define by
external serial resistance
6
6
6
FBC
Output of current sinking OTA amplifier or amplifiers driving feedback optocoupler’s LED. Connect here compensation network (networks) as well.
5
5
5
ON/OFF
ON mode current sink. This output keeps primary control pin at low level
in on mode.
OFF mode detection input. Voltage divider provides adjustable off mode
detection threshold
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
−0.3 to 40.0
V
VONOFF, VFBC, VLED
−0.3 to VCC + 0.3
V
VSNS, VISNS, VOFFDET, VMIN
−0.3 to 10.0
V
ILED
10
mA
RqJA
260
277
°C/W
Junction Temperature
TJ
−40 to 150
°C
Storage Temperature
TSTG
−60 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
250
V
Input Voltage
ON/OFF, FBC, LED Voltage
VSNS, ISNS, OFFDET, VMIN Voltage
LED Current
Thermal Resistance − Junction−to−Air (Note 1)
NCP4355A/C
NCP4355B
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 50 mm2, 1.0 oz. Copper spreader.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114F
ESD Machine Model tested per JESD22−A115C
Latchup Current Maximum Rating tested per JEDEC standard: JESD78D.
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NCP4355
ELECTRICAL CHARACTERISTICS
0°C ≤ TJ ≤ 125°C; VCC = 15 V; unless otherwise noted. Typical values are at TJ = +25°C.
Test Conditions
Parameter
Maximum Operating Input Voltage
VCC UVLO
Symbol
VCCUVLO
VCC rising
VCC UVLO Hysteresis
Quiescent Current In OFF mode
Typ
VCC
VCC falling
Quiescent Current In Regulation
Min
VCCUVLOHYS
Unit
36.0
V
V
3.75
4.00
4.25
3.22
3.50
3.78
0.4
0.5
ICC
NCP4355A
Max
V
125
155
NCP4355B
107
135
NCP4355C
115
155
ICCOFF
90
110
1
VSNS < 1.12 V
mA
mA
VOLTAGE CONTROL LOOP OTA
Transconductance
Sink current only
gmV
Reference Voltage
3.8 V ≤ VCC ≤ 36.0 V, TJ = 25°C
VREF
Sink Current Capability
1.250
1.256
3.8 V ≤ VCC ≤ 36.0 V, TJ = 0 − 85°C
1.240
1.250
1.264
3.8 V ≤ VCC ≤ 36.0 V, TJ = 0 − 125°C
1.230
1.250
1.270
1.5
2.0
mA
100
nA
In regulation, VFBC > 1.5 V
ISINKV
IBIASV
In regulation
In OFF mode
2.5
1.2
In OFF mode, VSNS > 1.12 V
Inverting Input Bias Current Threshold
V
1.244
In OFF mode, VFBC > 1.5 V
Inverting Input Bias Current
S
VSNSBIASTH
mA
−100
−2.6
−2.3
−1.9
mA
1.07
1.12
1.17
V
CURRENT CONTROL LOOP OTA (except NCP4355B)
Transconductance
Sink current only
gmC
Reference Voltage
3
VREFC
60.0
Sink Current Capability
VFBC > 1.5 V
ISINKC
2.5
Inverting Input Bias Current
ISNS = VREFC
IBIASC
−100
VREFM
355
62.5
S
65.0
mV
mA
100
nA
400
mV
MINIMUM VOLTAGE COMPARATOR (except NCP4355A)
Threshold Voltage
Hysteresis
Output change from logic high to logic low
377
VMINH
40
mV
VOFFDETTH
10% VCC
V
OFF MODE DETECTION COMPARATOR
Threshold Value
2.5 V ≤ VCC ≤ 36.0 V
VCC = 15 V
Hysteresis
1.47
Output change from logic high to logic low
1.50
1.53
V
VOFFDETH
40
mV
fSWLED
1
kHz
LED DRIVER (except NCP4355C)
Switching Frequency
Duty Cycle
Switch Resistance
DLED
ILED = 5 mA
10.0
RSW2
12.5
15.0
50
%
W
ON MODE CONTROL
Sink Current
In ON mode, VONOFF > 0.6 V
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IDRIVEON
140
160
180
mA
NCP4355
1.29
1.28
1.28
1.27
1.27
1.26
1.25
1.25
1.24
1.23
1.23
−20
0
20
40
60
80
100
1.22
120
12
18
24
Figure 4. VREF at VCC = 15 V
Figure 5. VREF at TJ = 255C
63.0
62.9
62.9
62.8
62.8
62.7
62.7
62.6
62.5
62.4
62.2
62.1
62.0
−40
62.1
62.0
40
60
80
100
120
0
6
12
18
24
TJ (°C)
VCC (V)
Figure 6. VREFC at VCC = 15 V
Figure 7. VREFC at TJ = 255C
410
410
400
400
390
390
380
370
360
30
36
30
36
62.4
62.2
20
36
62.5
62.3
0
30
62.6
62.3
350
−40
6
VCC (V)
63.0
−20
0
TJ (°C)
VREFC (mV)
VREFC (mV)
1.26
1.24
1.22
−40
VREFM (mV)
VREF (V)
1.29
VREFM (mV)
VREF (V)
TYPICAL CHARACTERISTICS
380
370
360
−20
0
20
40
60
80
100
350
120
0
6
12
18
24
TJ (°C)
VCC (V)
Figure 8. VREFM at VCC = 15 V
Figure 9. VREFM at TJ = 255C
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NCP4355
TYPICAL CHARACTERISTICS
4.2
1.53
4.1
1.52
VCCUVLO_R
VOFFDETTH (V)
VCC (V)
4.0
3.9
3.8
3.7
3.6
VCCUVLO_F
−20
0
20
40
60
80
100
−20
0
20
40
60
80
100
TJ (°C)
TJ (°C)
Figure 10. VCCUVLO
Figure 11. VOFFDETTH at VCC = 15 V
175
−1.9
170
−2.0
120
−2.1
160
IBIASV (mA)
IONOFF (mA)
1.49
1.47
−40
120
165
155
150
−2.2
−2.3
−2.4
145
−2.5
140
135
−40
−20
0
20
40
60
80
100
−2.6
−40
120
0
20
40
60
80
TJ (°C)
Figure 12. IONOFF at VCC = 15 V
Figure 13. IBIASV at VCC = 15 V,
VSNS > VSNSBIASTH
120
120
115
115
110
110
105
105
100
100
95
90
80
80
75
70
−40
75
70
20
40
60
80
100
120
0
6
12
18
24
30
TJ (°C)
VCC (V)
Figure 14. ICC in Regulation at VCC = 15 V for
NCP4355B
Figure 15. ICC in Regulation at TJ = 255C
for NCP4355B
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120
90
85
0
100
95
85
−20
−20
TJ (°C)
ICC (mA)
ICC (mA)
1.50
1.48
3.5
3.4
−40
1.51
36
NCP4355
110
110
105
105
100
100
95
ICC_OFFmode (mA)
ICC_OFFmode (mA)
TYPICAL CHARACTERISTICS
90
85
80
75
85
80
75
70
70
65
65
60
−40
−20
0
20
40
60
80
100
60
120
6
12
18
24
30
VCC (V)
Figure 16. ICC in OFF Mode at VCC = 15 V,
VSNS < VSNSBIASTH, for NCP4355B
Figure 17. ICC in OFF Mode at TJ = 255C,
VSNS < VSNSBIASTH, for NCP4355B
3.5
2.0
3.4
1.9
36
1.8
ISINKV (mA)
3.2
3.1
3.0
2.9
2.8
1.7
1.6
1.5
1.4
2.7
2.6
2.5
−40
0
TJ (°C)
3.3
ISINKV (mA)
95
90
1.3
−20
0
20
40
60
80
100
1.2
−40
120
−20
0
20
40
60
80
100
TJ (°C)
TJ (°C)
Figure 18. Voltage OTA Current Sink
Capability in Regulation
Figure 19. Voltage OTA Current Sink
Capability in OFF Mode
120
1.4
3.5
3.4
1.3
3.3
fSWLED (kHz)
ISINKC (mA)
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
−40
1.2
1.1
1.0
0.9
−20
0
20
40
60
80
100
0.8
−40
120
−20
0
20
40
60
80
100
TJ (°C)
TJ (°C)
Figure 20. Current OTA Current Sink
Capability
Figure 21. LED Switching Frequency
at VCC = 15 V
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120
NCP4355
TYPICAL CHARACTERISTICS
100
90
RSW2 (W)
80
70
60
50
40
30
−40
−20
0
20
40
60
80
TJ (°C)
Figure 22. RSW2 at VCC = 15 V
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100
120
NCP4355
APPLICATION INFORMATION
Typical application circuits for NCP4355x are shown in
Figure 24, Figure 25 and Figure 26. Each IC version contains
different features. Please see Device options table or Block
diagrams for detail information. NCP4355A does not have
a VMIN pin for setting the minimum voltage level, therefore
it needs a special circuit shown in Figure 24 in the dashed
box. This is needed for correct detection of load connection
in OFF mode. The same circuit can be used for other versions
when high speed detection of load connection is needed.
Supply Voltage
The IC is supplied through VCC pin. Supply voltage
should be taken from output voltage in range from 4.5 V up
to 36 V. Power supply voltage should be separated from
output voltage by a diode D3 and some energy should be
stored in a VCC cap C6. Cap should be high enough to keep
enough energy for ONOFF optocoupler and NCP4355x
before primary controller is started. Time constant of the
VCC cap C6 and the IC supply current should be smaller
than time constant of power supply output filter and
maximum output current in OFF mode. VCC pin should also
be decoupled by 100 nF decoupling cap C5.
Figure 23. Shared Dividers Type
Current Regulation Path (A and C versions only)
The output current is sensed by the shunt resistor R11 in
series with the load. Voltage drop on R11 is compared with
internal precise voltage reference VREFC at ISNS transcon−
ductance amplifier input.
Voltage difference is amplified by gmC to output current
of amplifier, connected to FBC pin. Compensation network
is connected between this pin and ISNS input to provide
frequency compensation for current regulation path.
Resistor R12 separates compensation network from sense
resistor. Compensation network works into low impedance
without this resistor that significantly decreases
compensation network impact.
Current regulation point is set to current given by
Equation 4.
Voltage Regulation Path
The output voltage is detected on the VSNS pin by the R4,
R5 and R6 voltage divider. This voltage is compared with
the internal precise voltage reference. The voltage
difference is amplified by gmV of the transconductance
amplifier. The amplifier output current is connected to the
FBC pin. The compensation network is also connected to
this pin to provide frequency compensation for the voltage
regulation path. This FBC pin drives an optocoupler that
provides regulation of primary side. The optocoupler is
supplied via direct connection to VOUT line through
resistor R1.
Regulation information is transferred through the
optocoupler to the primary side controller where its FB pin
is usually pulled down to reduce energy transferred to
secondary output.
The VSNS voltage divider is shared with VMIN voltage
divider. The shared voltage divider can be connected in two
ways as shown in Figure 23. The divider type is selected
based on the ratio between VMIN and VOUT. When the
condition of Equation 1 is true, divider type 1 should be used.
V MIN u
V OUT V REFM
V REF
I OUTLIM +
OFF mode operation is advantageous for ultra low or zero
output current condition. The very long off time and the ultra
low power mode of the whole regulation system greatly
reduces the overall consumption.
The output voltage is varying between nominal and
minimal in OFF mode. When output voltage decreases
below set (except NCP4355A) minimum level, primary
controller is switch on until output capacitor C1 is charged
again to the nominal voltage.
The OFF mode detection is based on comparison of output
voltage and voltage loaded with fixed resistances (D2, C2,
R7 and R8). Figure 27 shows detection waveforms. When
output voltage is loaded with very low current, primary
controller goes into skip mode (primary controller stops
switching for some time). While output capacitor C1 is
discharged very slowly (no load condition), a fixed load R7
and R8 discharges the capacitor C2 faster than load current
discharges output voltage on C1.
Once OFFDET pin voltage is lower than VOFFDETTH (this
threshold is derived from VCC that is very close to VOUT),
(eq. 1)
(eq. 2)
and for type 2 by Equation 3.
V OUT + V REF R4 ) R5 ) R6
R6
(eq. 4)
OFF Mode Detection
Output voltage for divider type 1 can be computed by
Equation 2
V OUT + V REF R4 ) R5 ) R6
R5 ) R6
V REFC
R11
(eq. 3)
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NCP4355
OFF mode is detected. In OFF mode SW1 is switched off
and no IONOFF current is going through ON/OFF pin. The
primary controller’s REM pin voltage increases and primary
IC goes in to off mode.
IBIASV current flow from VSNS pin to feedback divider
is also activated when OFF mode is detected. This current
increases voltage at VSNS pin and due to it voltage OTA
sinks reduced current through regulation optocoupler. OTA
stops to sink current when VSNS voltage drops below VREF.
IBIASV current disappears when VSNS voltage is lower than
90% of VREF. This feature helps to avoid primary side
switching when OFF mode is detected at secondary side and
primary side is waiting for correct information at REM pin.
Primary FB pin voltage is above regulation range until
VOUT is at set level. Once VOUT is at set level, the secondary
controller starts to sink current from optocoupler LED’s and
primary FB voltage is stabilized in regulation region. With
nominal output power (without skip mode) OFFDET pin
voltage is higher than VOFFDETTH (typically 10% of VCC).
After some time, the load current decreases to low level
(5) and primary convertor uses skip mode (6) to keep
regulation of output voltage at set level and save some
energy. The skip mode consists of few switching cycles
followed by missing ones to provide limited energy by light
load. The number of missing cycles allows regulation for
any output power.
While both C1 and C2 are discharged during the missing
cycles, C2 discharge will be faster than C1 without output
current, VOFFDET drops below VOFFDETTH and OFF mode
is detected (7). This situation is shown in Figure 27 in detail.
When OFF mode is detected, current into ONOFF pin stops
to flow (7) and voltage at primary REM pin increases over
threshold level that forces primary controller into OFF
mode. Internal pull−up current IBIASV is switched on (7),
VSNS pin voltage increases (thanks to IBIASV) and voltage
amplifier sinks reduced current at time (8), when VSNS is
higher than VREF (9), to keep primary FB voltage below
switching level until REM pin voltage is high enough.
IBIASV current stops when VSNS voltage drops below 90%
of VREF.
Discharging of C1 continues (10) until output voltage
drops below level set by voltage divider at VMIN pin
(except NCP4355A where minimum VOUT is defined only
by VCC UVLO) (11). ONOFF current starts to flow,
primary REM voltage decreases and primary VCC voltage
is rising (12). Primary controller starts to operate, when
VCC voltage is enough and FB voltage is at regulation area
(13). Output capacitor C1 is recharged (14) to set voltage. If
there is still light load condition primary controller goes to
skip mode (15) again and after some time secondary
controller detects OFF mode by very light or no load
condition (16) and whole cycle is repeated.
Minimum Output Voltage Detection (except NCP4355A)
Minimum output voltage level defines primary controller
restart from OFF mode. It can be set by shared voltage
divider with voltage regulation loop. When VMIN voltage
drops below VREFM, OFF mode is ended and primary
controller restarts.
NCP4355A has no external adjustment and uses the
internal minimum voltage level specified by minimum
falling operation supply voltage and special load detection
circuit for faster detection of load connection (T2, R16 and
R17 at Figure 24). Principe of load connection detection is
that when load is connected, output capacitor C1 is
discharged faster than C6 capacitor by IC supply current.
Voltage across D3 increases and when there is enough
voltage to open T2 some current is injected into OFFDET
divider. Voltage at OFFDET pin goes above 10% of VCC and
OFF mode ends. This circuit can also be used with B and C
versions to dramatically speed up wakeup time from OFF
mode. If this circuit is not used, it is necessary to wait for C6
discharge below VCC UVLO falling level before the
primary controller is restarted.
LED Driver (except NCP4355C)
LED driver is active when VCC is higher than VCCMIN
and output voltage is in regulation (it is off during OFF
mode). LED driver consists of an internal power switch
controlled by PWM modulated logic signal and an external
current limiting resistor R3. LED current can be computed
by Equation 5
I LED +
V OUT * V F_LED
R3
Fast Restart From OFF Mode
The IC ends OFF mode when a load is connected to the
output and VOUT is discharged to VMIN level. There exists
another connection that allows transition to normal mode
faster without waiting some time for VOUT to discharge to
VMIN (it is necessary to use it with NCP4355A). This
schematic is shown at Figure 24 in dashed box. The basic
idea is that C6 is discharged by the IC faster than C1 by
output load in OFF mode. When an output load is applied,
capacitor C1 is discharged faster and this creates the voltage
drop at D3. When there is enough voltage at D3, T2 is
conducting and current is injected into the OFFDET divider
through R16. OFFDET voltage higher than 10% of VCC
ends OFF mode and ON/OFF current starts to flow. Primary
controller leaves OFF mode because voltage at REM pin
increase above OFF mode detection threshold.
(eq. 5)
PWM modulation is used to increase efficiency of LED.
Operation in OFF Mode Description
Operation waveforms in off mode and transition into OFF
mode with primary controller are shown in Figure 28.
Figure shows waveforms from the first start (1) of the
convertor. At first, primary controller charges VCC
capacitor over the VCCON level (2). When primary VCC is
over this level (3), primary controller starts to operate and
VOUT is slowly rising according to primary controller start
up ramp to nominal voltage (4). When VOUT is high enough,
VCC capacitor is charged from auxiliary winding.
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NCP4355
when load is connected during OFF mode. It can be seen that
the application is waiting not for low VOUT, but for low VCC
and then OFF mode is ended.
Normal operation waveforms for typical load detection
connection and improved load detection waveforms are
shown in Figure 29. Figure 30 shows waveforms for
NCP4355A (without VMIN detection) in OFF mode and
D4
VCC
D2
D1
D5
~VIN
C1
C7
R10 C4
C2
D3
D6
R9 C3
D7
D8
VCC
C5
OPTO1
R13
VCC
CS
LED1 R3
T2
R14
FB
GND REM
C8
R1
R15
T1
HV DRV
R16
C10
OPTO2
OPTO1
C6
R2
FBC VCC
LED
VSNS
ON/OFF
GND
ISNS
VOUT
R4
R12
R5
R11
R7
OFFDET
NCP4355A
R8
C9
OPTO2
OPTIONAL FOR
OTHER VERSIONS
Figure 24. Typical Application Schematic for NCP4355A
D4
VCC
D2
D1
~VIN
C7
D5
C1
C2
D3
D6
R9 C3
D7
C5
OPTO1
D8
VCC
R13
VCC
C8
R1
T1
HV DRV
LED1 R3
CS
R14
FB
GND REM
OPTO2
R2
C10
C6
OPTO1
FBC
LED
VSNS
OFFDET
ON/OFF
VMIN
GND
C9
OPTO2
Figure 25. Typical Application Schematic for NCP4355B
12
VOUT
VCC
NCP4355B
http://onsemi.com
R4
R5
R6
R7
R8
NCP4355
D4
VCC
D2
D1
~VIN
C7
D5
C1
C2
R10 C4
D3
D6
R9 C3
D7
D8
VCC
C5
OPTO1
R13
VCC
C8
FBC VCC
R1
T1
HV DRV
C6
ISNS
VSNS
R4
R12
CS
R14
FB
GND REM
OPTO2
R2
C10
OPTO1
ON/OFF
OFFDET
GND
NCP4355C
VMIN
VOUT
R5
R11
R7
R6
R8
C9
OPTO2
Figure 26. Typical Application Schematic for NCP4355C
Primary
Controller
Activity
Normal operation
Skip
Off mode
Very low or no load detected,
off mode activated
VOFFDET
10%
VOUT(VCC)
IOUT
Figure 27. OFF Mode Detection
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13
1
IONOFF
VREM_prim
10% VCC
VOFFDET
IBIASV switched on
1 kHz 12% wide
pulses
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14
FBC sink current disappears −>
lower current consumption
Application powered from COUT
Max IFBC at
off mode
SKIP
ON
16 Very light load −> off mode
OFF
15 Very light load −> skip mode
Start up, IOUT nominal or low
11
12 VOUT < VMIN −> IONOFF starts flow, primary VCC is rising
13
14 COUT charging
VOUT
IOUT
COMPRESSED TIME
SKIP
10c VOUT is close to minimum set voltage
10b Long time of COUT discharging
FBC sink current disappears −>
lower current consumption
Application powered from COUT
IFBC
10a
IBIASV
switched off
9
VREF
8 Very light load −> off mode
ON
7
Status
5
6 Light load −> skip mode
VCC_Prim VCCON
4 Start−up and regulation
ILED
3
VSNS
VMIN
2 Primary VCC cap is charged by DSS
NCP4355
Very low IOUT activates OFF mode with rarely COUT charging
VAUX
OFF
VFB_Prim
VMIN Threshold
1 kHz
12%
wide
pulses
Figure 28. Typical Application States and Waveforms in OFF Mode with Active On Primary Controller
NCP4355
NO LOAD
IOUT
LOAD IS CONNECTED
Primary side start delay
Secondary side detects low VOUT
VOUT
VCC
Vout is
discharged faster
VMIN level
VREMprim
Primary off mode ends
VOFFDET
Typical load detection behavior
NO LOAD
LOAD IS CONNECTED
IOUT
T2 is conducting
VOUT
VCC
VMIN level
Primary side start delay
VREMprim
Primary off mode ends
VOFFDET
Voltage delivered through T2 and R16
Improved load detection behavior
Figure 29. Typical and Improved Load Detection Comparison Waveforms
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15
NCP4355
LOAD IS CONNECTED
NO LOAD
IOUT
Primary side start delay
Detection
delay
Secondary side detects low VCCmin
VOUT
VCC
Vout is
discharged faster
VCCmin level
Primary side
start delay
VREMprim
Primary off mode ends
VOFFDET
Figure 30. Typical Load Detection of NCP4355A Without External Detection Circuit Waveforms
ORDERING INFORMATION
Marking
Adjustable
VMIN
Current
Regulation
LED
Driver
NCP4355ADR2G
NCP4355A
No
Yes
NCP4355BDR2G
NCP4355B
Yes
NCP4355CDR2G
NCP4355C
Yes
Device
Package
Shipping
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
No
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
Yes
No
SOIC−8
(Pb−Free)
2500 / Tape & Reel
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16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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