NCP5399
2-Phase Controller for CPU
Applications
The NCP5399 is a one or two−phase buck controller which
combines differential voltage and current sensing, and adaptive
voltage positioning to power Intel VR10.x processors. Dual−edge
pulse−width modulation (PWM) combined with inductor current
sensing reduces system cost by providing the fastest initial response
to transient load events. Staggered phase modulation reduces total
bulk and ceramic output capacitance required to satisfy transient
load−line regulation.
A high performance operational error amplifier is provided which
allows easy compensation of the system. The proprietary method of
Dynamic Reference Injection (patented) makes the error amplifier
compensation virtually independent of the system response to VID
changes, eliminating tradeoffs between overshoot and Dynamic VID
performance.
NCP5399
AWLYYWWG
32 PIN QFN
MN SUFFIX
CASE 485AM
ILIM 24
ROSC 23
3 VID4
VCC 22
GATE1
5VFILT
GATE3
NC
GND
21
20
19
18
17
16 CS3P
14 NC
13 NC
NCP5399
15 CS3N
DIFFOUT
VS+
SS
PWRGD
DRVON
12 COMP
4
5
6
7
8
CS1P 25
GND 27
CS1N 26
DAC_SEL 28
1 VID2
2 VID3
ENABLE 29
VID5 30
VID0 31
NCP5399 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
11 VFB
Applications
1
10 VDRP
Meets Intel’s VR 10.x Specifications
Dual−edge PWM for Fastest Initial Response to Transient Loading
High Performance Operational Error Amplifier
Dynamic Reference Injection (Patented)
DAC Range from 0.8375 V to 1.6 V
±0.5% System Voltage Accuracy from 1.0 V to 1.6 V
True Differential Remote Voltage Sensing Amplifier
Phase−to−Phase Current Balancing
“Lossless” Differential Inductor Current Sensing
Differential Current Sense Amplifiers for each Phase
Adaptive Voltage Positioning (AVP)
Frequency Range: 100 KHz – 1 MHz
Latched Over Voltage Protection (OVP)
Threshold Sensitive Enable Pin for VTT Sensing
Power Good Output with Internal Delays
Programmable Soft Start Time
This is a Pb−Free Device
NCP5399
AWLYYWWG
32 PIN LQFP
FT SUFFIX
CASE 873A
VID1 32
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MARKING DIAGRAMS
9 VS−
Features
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(Top View)
• Desktop Processors
• Gaming Applications
ORDERING INFORMATION
Device
Package
Shipping†
NCP5399FTR2G
LQFP−32 2000 / Tape & Reel
(Pb−Free)
NCP5399MNR2G
QFN−32 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2008
July, 2008 − Rev. 2
1
Publication Order Number:
NCP5399/D
NCP5399
NCP5399
VID0
VID1
VID2
VID3
VID4
VID5
DAC_SEL
VR10 / MARGIN
DAC
DAC Minus No Load Offset
Remote
Sense
Amplifier
SS
CSS
VS−
-
VS+
+
FAULT
RISO2
RFB
+
-
RFB1
Error Amplifier
CFB1
RT2
RISO1
OVP
Comparator
DIFFOUT
UV
Comparator
VFB
-
CH
CF
-
1.3 V
+
+
RF
COMP
RDRP
VDRP
RCS1
Droop
Amplifier
FAULT
CS1
CCS1 CS1N
RCS3
+
-
CS3N
+
-
GATE1
+
-
GATE3
Gain = 6
CS3
CCS3
+
-
Gain = 6
FAULT
OVP
Oscillator
ROSC
DRVON
RLIM1
+
ILIM
RLIM2
12 V
-
EN
VCC
+
-
RFILT
5VFILT
CFILT
+12V UVLO
5 V Shunt
Regulator
+
-
POR
GND
Figure 1. Functional Block Diagram
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2
Fault
Monitors
PWRGD
NCP5399
PIN DESCRIPTIONS
Pin No.
Symbol
Description
1
VID2
Voltage ID DAC input
2
VID3
Voltage ID DAC input
3
VID4
Voltage ID DAC input
4
DIFFOUT
5
VS+
Non−inverting input to the internal differential remote sense amplifier.
6
SS
A capacitor from this pin to ground programs the soft−start time.
7
PWRGD
Power Good output. Open drain type output. High indicates the output is regulating.
8
DRVON
Output to enable Gate Drivers
9
VS−
10
VDRP
11
VFB
12
COMP
13
NC
This pin can be grounded or left unconnected.
14
NC
This pin can be grounded or left unconnected.
15
CS3N
Inverting input of current sense amplifier #3
16
CS3P
Non−inverting input of current sense amplifier #3
17
GND
Power supply return
18
NC
19
GATE3
PWM output to gate driver.
20
5VFILT
Power input pin. Connect a 243 ohm resistor from this pin to VCC, and a 2.2 F ceramic capacitor from this
pin to ground.
21
GATE1
PWM output to gate driver.
22
VCC
12 V input supply monitor.
23
ROSC
A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies an output
voltage of 2 V which may be used to form a voltage divider to the ILIM pin for setting the over current shutdown threshold as shown in the Applications Schematics.
24
ILIM
Over current shutdown threshold. Connect this pin to the ROSC pin via a resistor divider as shown in the
Applications Schematics. To disable over current protection, connect this pin directly to the ROSC pin. For
correct operation, this pin should only be connected to the voltage generated by the ROSC pin – do not
connect this pin to externally generated voltages.
Output of the differential remote sense amplifier.
Inverting input to the internal differential remote sense amplifier.
Current signal output for Adaptive Voltage Positioning (AVP). The offset of this pin above the 1.3 V internal
bias voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount
of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for
no AVP.
Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and
the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP)
during load.
Output of the error amplifier and the non−inverting input of the PWM comparators.
Do not connect anything to this pin
25
CS1P
Non−inverting input of current sense amplifier #1
26
CS1N
Inverting input of current sense amplifier #1
27
GND
This pin must be grounded.
28
DAC_SEL
29
ENABLE
30
VID5
Voltage ID DAC input
31
VID0
Voltage ID DAC input
32
VID1
Voltage ID DAC input
Allows selection of VR10.x or MARGIN DAC
Pull this pin high to enable controller. Pull this pin to ground to disable controller. A Low to High transition on
this pin will initiate soft start. 20 MHz filtering at this pin is recommended.
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3
NCP5399
MAXIMUM RATINGS
Electrical Information
VMAX (V)
VMIN (V)
ISOURCE (mA)
ISINK (mA)
COMP
Pin Symbol
5.5
−0.3
10
10
VDRP
5.5
−0.3
5
5
VS+
2.0
GND – 300 mV
1
1
VS–
2.0
GND – 300 mV
1
1
DIFFOUT
5.5
−0.3
20
20
PWRGD
5.5
−0.3
N/A
20
DRVON
5.5
−0.3
1
2
VCC
15.0
−0.3
N/A
1
5VFILT
5.25
−0.3
N/A
40
ROSC
5.5
−0.3
1
N/A
All Other Pins
5.5
−0.3
*All signals reference to GND (pin 17) unless otherwise noted.
Thermal Information
Symbol
Value
Unit
Thermal Characteristic, LQFP Package (Note 1)
Rating
RJA
52
°C/W
Operating Junction Temperature Range (Note 2)
TJ
0 to 125
°C
Operating Ambient Temperature Range
TA
0 to 85
°C
Maximum Storage Temperature Range
TSTG
−55 to +150
°C
Moisture Sensitivity Level, LQFP Package
MSL
3
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP5399
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < 5VFILT < 5.25 V; All DAC Codes; C5VFILT = 1.0 F)
Parameter
Test Conditions
Min
Typ
Max
Units
Input Bias Current (Note 3)
−20
−
20
nA
Input Offset Voltage (Note 3)
−1.0
−
1.0
mV
Error Amplifier
Open Loop DC Gain (Note 3)
CL = 60 pF to GND, RL = 10 K to GND
−
100
−
dB
Open Loop Unity Gain Bandwidth
(Note 3)
CL = 60 pF to GND, RL = 10 K to GND
−
15
−
MHz
Open Loop Phase Margin (Note 3)
CL = 60 pF to GND, RL = 10 K to GND
−
70
−
deg
Slew Rate (Note 3)
Vin = 100 mV, G = −10 V/V,
COMP between 1.5 V and 2.5 V,
CL = 60 pF to GND,
DC Load = ±125 A
−
5
−
V/s
Maximum Output Voltage
10 mV of overdrive, ISOURCE = 2.0 mA
2.2
5VFILT−
20 mV
−
V
Minimum Output Voltage
10 mV of overdrive, ISINK = 2.0 mA
−
0.01
0.5
V
Output source current (Note 3)
10 mV input overdrive, COMP = 2.0 V
2.0
−
−
mA
Output sink current (Note 3)
10 mV input overdrive, COMP = 1.0 V
2.0
−
−
mA
Differential Summing Amplifier
VS+ Input Resistance
DRVON = low
DRVON = high
−
−
1.5
17
−
−
k
VS+ Input Bias Voltage
DRVON = low
DRVON = high
−
−
0.05
0.65
−
−
V
VS− Bias Current
VS− = 0 V
−
33
−
A
VS+ Input Voltage Range
0.95 ≤ DIFFOUT/VS+ ≤ 1.05
0.5 V ≤ DIFFOUT ≤ 2.0 V
−0.3
−
2.0
V
VS− Input Voltage Range
0.95 ≤ DIFFOUT/VS− ≤ 1.05
0.5 V ≤ DIFFOUT ≤ 2.0 V
−0.3
−
0.3
V
DC Gain VS+ to DIFFOUT
0 V < DAC − VS+ < 0.3 V
0.98
1.0
1.025
V/V
DAC Accuracy (measured at VS+)
Closed loop measurement including
error amplifier.
1.0 ≤ DAC ≤ 1.6
−0.5
−
0.5
%
0.8 ≤ DAC ≤ 1.0
−5
−
5
mV
−3 dB Bandwidth (Note 3)
CL = 80 pF to GND,
RL = 10 K to GND
−
10
−
MHz
Slew Rate (Note 3)
VS+ − VS− step = ±100 mV;
DIFFOUT between 1.3 V and 1.2 V
−
±5
−
V/s
Maximum Output Voltage
VS+ minus DAC = 0.8 V
ISOURCE = 2.0 mA
2.0
3.0
−
V
Minimum Output Voltage
VS+ minus DAC = −0.8 V
ISINK = 2.0 mA
−
0.01
0.5
V
Output source current (Note 3)
VS+ minus DAC = 0.8 V
DIFFOUT = 2.0 V
2.0
−
−
mA
Output sink current (Note 3)
VS+ minus DAC = −0.8 V
DIFFOUT = 1.0 V
2.0
−
−
mA
3. Guaranteed by design. Not tested in production.
4. This is the maximum current used by the internal circuits of the NCP5399 with no current flowing into the internal 5 V shunt regulator.
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5
NCP5399
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < 5VFILT < 5.25 V; All DAC Codes; C5VFILT = 1.0 F)
Parameter
Test Conditions
Min
Typ
Max
Units
−
1.30
−
V
5.64
5.8
5.95
V/V
−
4
−
MHz
2.5
−
−
V/s
−15.0
−
+15.0
mV
2.6
3.0
−
V
Internal Bias Voltage
The VDRP pin offset voltage & the
voltage at the Error Amp (+) input
VRDP Adaptive Voltage Positioning Amplifier
Current Sense Input to VDRP Gain
−60 mV < (CSxP – CSxN) < 60 mV
(each CS input independently)
Current Sense Input to VDRP −3 dB
Bandwidth (Note 3)
CL = 30 pF to GND,
RL = 10 KΩ to GND
VDRP Output Slew Rate (Note 3)
Vin = 25 mV, VDRP between 1.3 V and
1.9 V, CL = 330 pF to GND, RL between
1 k and 10 k to 1.3 V
VDRP Output Voltage Offset from
Internal Bias Voltage
CSxP = CSNx = 1.3 V
Maximum VDRP Output Voltage
CSxP – CSxN = 0.1 V
(all phases), Isource = 1.0 mA
Minimum VDRP Output Voltage
CSxP – CSxN = −0.033 V
(all phases) Isink = 1.0 mA
−
0.1
0.5
V
Output source current (Note 3)
VDRP = 2.0 V
−
1.3
−
mA
Output sink current (Note 3)
VDRP = 1.0 V
−
25
−
mA
−20
−
20
nA
Common Mode Input Voltage Range
−0.3
−
2.0
V
Differential Mode Input Voltage
Range
−120
−
120
mV
−1.0
−
1.0
mV
−
6.0
−
V/V
100
−
1000
kHz
−
−
950
235
450
1000
−
−
1050
kHz
kHz
kHz
Current Sense Amplifiers
Input Bias Current (Note 3)
CSxP = CSxN = 1.4 V
Input Referred Offset Voltage
(Note 3)
CSxP = CSxN = 1.000 V
Current Sense Input to PWM Gain
0 V < CSxP−CSxN < 0.1 V
Oscillator
Switching Frequency Range (Note 3)
Switching Frequency Accuracy
ROSC = 50 kΩ
ROSC = 25 kΩ
ROSC = 10 kΩ
Switching Frequency Tolerance
(Note 3)
100 KHz < Fsw < 1 MHz
−
15
−
%
ROSC Output Voltage
20 A = IROSC = 250 A
1.95
2.0
2.065
V
Modulators (PWM Comparators)
Minimum Pulse Width (Note 3)
Fs = 1000 KHz
−
30
40
ns
Propagation Delay (Note 3)
±20 mV of overdrive
−
20
−
ns
−
1
−
V
Magnitude of the PWM Ramp
0% Duty Cycle
COMP voltage when the PWM outputs
remain LOW
−
1.3
−
V
100% Duty Cycle
COMP voltage when the PWM outputs
remain HIGH
−
2.3
−
V
−
90
−
%
PWM Linear Duty Cycle (Note 3)
3. Guaranteed by design. Not tested in production.
4. This is the maximum current used by the internal circuits of the NCP5399 with no current flowing into the internal 5 V shunt regulator.
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NCP5399
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < 5VFILT < 5.25 V; All DAC Codes; C5VFILT = 1.0 F)
Parameter
Test Conditions
Min
Typ
Max
Units
−15
−
15
deg
Modulators (PWM Comparators)
PWM Phase Angle Error
Power Good Output (PWRGD)
PWRGD Output Saturation Voltage
IPWRGD = 10 mA
−
−
0.4
V
PWRGD Rise Time
External pull−up of 680 to 1.25 V,
CL = 45 pF, Vo = 10% to 90%
−
−
150
ns
PWRGD High – Output Leakage
Current
PWRGD = 5.0 V
−
−
1
A
PWRGD Upper Threshold Voltage
VCORE increasing, DAC = 1.3 V
−
300
−
mV
below
DAC
PWRGD Lower Threshold Voltage
VCORE decreasing, DAC = 1.3 V
−
350
−
mV
below
DAC
PWRGD Rising Delay
VCORE increasing
−
−
3
ms
PWRGD Falling Delay
VCORE decreasing
−
−
250
s
3.0
−
V5VFILT
V
PWM Outputs
Output High Voltage
Sourcing 500 A
Output Low Voltage
Sinking 500 A
−
−
0.15
V
Rise Time
CL = 20 pF, Vo = 0.3 to 2.0 V
−
7
25
ns
Fall Time
CL = 20 pF, Vo = 2.0 V to 0.3 V
−
9
25
ns
Output Impedance – Sourcing
Resistance to 5VFILT
−
100
−
Ω
Output Impedance – Sinking
Resistance to GND
−
100
−
Ω
3.0
−
−
V
DRVON
Output High Voltage
Sourcing 500 A
Output Low Voltage
Sinking 500 A
−
−
0.7
V
Rise Time
CL = 20 pF, Vo = 10% to 90%
−
24
30
ns
Fall Time
CL = 20 pF, Vo = 90% to 10%
−
11
20
ns
−
70
−
KΩ
3.75
5.0
6.25
A
Internal Pull Down Resistance
Soft−Start
Soft−Start Pin Source Current
Voltage on SS pin < DAC
Soft−Start Pin Ramp Time
Css = 0.01 F; Time to 1.05 V
−
2.2
−
ms
Soft−Start Pin Discharge Voltage
DRVON pin LO (Fault)
−
−
25
mV
Enable High Input Leakage Current
EN = 3.3 V
−
−
1.0
A
Rising Threshold
VUPPER
0.800
−
0.920
V
Falling Threshold
VLOWER
0.670
−
0.830
V
Total Hysteresis
VUPPER – VLOWER
−
130
−
mV
Enable Delay Time
Time from Enable transitioning HI to
initiation of Soft−start
1.0
−
5.0
ms
Disable Delay Time
Time from Enable transitioning LO to
DRVON LO
−
150
200
ns
Enable Input
3. Guaranteed by design. Not tested in production.
4. This is the maximum current used by the internal circuits of the NCP5399 with no current flowing into the internal 5 V shunt regulator.
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NCP5399
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < 5VFILT < 5.25 V; All DAC Codes; C5VFILT = 1.0 F)
Parameter
Test Conditions
Min
Typ
Max
Units
5.7
5.95
6.2
V/V
−
−
1.0
A
0.2
−
2.0
V
−33
17
67
mV
−
300
−
ns
DAC+
160
−
DAC+
200
mV
−
100
−
ns
VCC UVLO Start Threshold
−
9.25
9.5
V
VCC UVLO Stop Threshold
8.25
8.5
−
V
−
0.75
−
V
Current Limit
Current Sense Amp to ILIM Gain
20 mV < (CSx−CSxN) < 60 mV
(each CS Input independently)
ILIM Pin Input Bias Current
ILIM = 2.0 V
ILIM Pin Working Voltage Range
(Note 3)
ILIM offset voltage
Offset extrapolated to CSx − CSxN =
0 V and referred to the ILIM pin.
Delay (Note 3)
Overvoltage Protection
Overvoltage Threshold
Delay
Undervoltage Protection
VCC UVLO Hysteresis
VID Inputs
Upper Threshold
VUPPER
−
−
800
mV
Lower Threshold
VLOWER
300
−
−
mV
−
−
500
nA
500
−
800
ns
Input Bias Current
Delay before Latching VID Change
(VID De−Skewing) (Note 3)
Measured from the edge of the
change
1st
VID
Internal DAC Slew Rate Limiter
Positive Slew Rate Limit
VID step range of +500 mV
−
6.3
−
mV/s
Negative Slew Rate Limit
VID step range of −500 mV
−
−6.3
−
mV/s
Recommended Operating Current
Not Enabled; 243 to 12 V
−
30
−
mA
Minimum Operating Current
Operating at 1 MHz (Note 4)
16.5
−
−
mA
Regulated Voltage
EN Low, No PWM; 243 to 12 V, 1.0 F
to GND
−
5.0
−
V
1.0 V < DAC < 1.6 V
0. 8375 V < DAC < 1.0 V
−
−
±0.5
±5
%
mV
−
−
0.6
V
0.6
−
2.0
V
Shunt Regulator
DAC Voltage
System Voltage Accuracy
DAC = VR10.x DAC
DAC = MARGIN DAC
3. Guaranteed by design. Not tested in production.
4. This is the maximum current used by the internal circuits of the NCP5399 with no current flowing into the internal 5 V shunt regulator.
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NCP5399
VID4
400 mV
VID3
200 mV
VID2
100 mV
VID1
50 mV
VID0
25 mV
VID5
12.5 mV
VR10.x
Voltage (V)
MARGIN
Voltage (V)
0
1
0
1
0
1
1.6000
0.55000
0
1
0
1
1
0
1.5875
0.74375
0
1
0
1
1
1
1.5750
0.54375
0
1
1
0
0
0
1.5625
0.73750
0
1
1
0
0
1
1.5500
0.53750
0
1
1
0
1
0
1.5375
0.73125
0
1
1
0
1
1
1.5250
0.53125
0
1
1
1
0
0
1.5125
0.72500
0
1
1
1
0
1
1.5000
0.52500
0
1
1
1
1
0
1.4875
0.71875
0
1
1
1
1
1
1.4750
0.51875
1
0
0
0
0
0
1.4625
0.71250
1
0
0
0
0
1
1.4500
0.51250
1
0
0
0
1
0
1.4375
0.70625
1
0
0
0
1
1
1.4250
0.50625
1
0
0
1
0
0
1.4125
0.70000
1
0
0
1
0
1
1.4000
0.50000
1
0
0
1
1
0
1.3875
0.69375
1
0
0
1
1
1
1.3750
OFF
1
0
1
0
0
0
1.3625
0.68750
1
0
1
0
0
1
1.3500
OFF
1
0
1
0
1
0
1.3375
0.68125
1
0
1
0
1
1
1.3250
OFF
1
0
1
1
0
0
1.3125
0.67500
1
0
1
1
0
1
1.3000
OFF
1
0
1
1
1
0
1.2875
0.66875
1
0
1
1
1
1
1.2750
OFF
1
1
0
0
0
0
1.2625
0.66250
1
1
0
0
0
1
1.2500
OFF
1
1
0
0
1
0
1.2375
0.65625
1
1
0
0
1
1
1.2250
OFF
1
1
0
1
0
0
1.2125
0.65000
1
1
0
1
0
1
1.2000
OFF
1
1
0
1
1
0
1.1875
0.64375
1
1
0
1
1
1
1.1750
OFF
1
1
1
0
0
0
1.1625
0.63750
1
1
1
0
0
1
1.1500
OFF
1
1
1
0
1
0
1.1375
0.63125
1
1
1
0
1
1
1.1250
OFF
1
1
1
1
0
0
1.1125
0.62500
1
1
1
1
0
1
1.1000
OFF
1
1
1
1
1
0
OFF
0.61875
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9
NCP5399
VID4
400 mV
VID3
200 mV
VID2
100 mV
VID1
50 mV
VID0
25 mV
VID5
12.5 mV
VR10.x
Voltage (V)
MARGIN
Voltage (V)
1
1
1
1
1
1
OFF
OFF
0
0
0
0
0
0
1.0875
0.81250
0
0
0
0
0
1
1.0750
0.61250
0
0
0
0
1
0
1.0625
0.80625
0
0
0
0
1
1
1.0500
0.60625
0
0
0
1
0
0
1.0375
0.80000
0
0
0
1
0
1
1.0250
0.60000
0
0
0
1
1
0
1.0125
0.79375
0
0
0
1
1
1
1.0000
0.59375
0
0
1
0
0
0
0.9875
0.78750
0
0
1
0
0
1
0.9750
0.58750
0
0
1
0
1
0
0.9625
0.78125
0
0
1
0
1
1
0.9500
0.58125
0
0
1
1
0
0
0.9375
0.77500
0
0
1
1
0
1
0.9250
0.57500
0
0
1
1
1
0
0.9125
0.76875
0
0
1
1
1
1
0.9000
0.56875
0
1
0
0
0
0
0.8875
0.76250
0
1
0
0
0
1
0.8750
0.56250
0
1
0
0
1
0
0.8625
0.75625
0
1
0
0
1
1
0.8500
0.55625
0
1
0
1
0
0
0.8375
0.75000
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10
NCP5399
TYPICAL CHARACTERISTICS
4.90
ISS, SOFT START CURRENT (A)
2.017
ROSC VOLTAGE (V)
2.016
2.015
2.014
2.013
4.85
4.80
4.75
2.012
4.70
0
10
20
30
40
50
60
70
80
90
0
10
20
T, TEMPERATURE (°C)
40
50
60
70
80
90
Figure 3. Soft−Start Current vs. Temperature
1.003
4.30
1.002
DAC = 1.6 V
DAC = 1.1 V
1.001
DAC = 0.5 V
0
10
20
30
40
50
60
70
80
Start
4.25
UVLO THRESHOLD (V)
REMOTE SENSE AMPLIFIER GAIN (V/V)
Figure 2. ROSC Voltage vs. Temperature
1.000
30
T, TEMPERATURE (°C)
4.20
4.15
4.10
4.05
90
Stop
0
10
20
30
40
50
60
70
80
T, TEMPERATURE (°C)
T, TEMPERATURE (°C)
Figure 4. Remote Sense Amplifier Gain vs.
Temperature
Figure 5. UVLO Threshold vs. Temperature
0.90
90
2.0
Start
0.86
RSA BIAS ERROR (mV)
0.84
0.82
0.80
0.78
0.76
0.0
70°C
50°C
25°C
−1.0
Stop
0°C
0.74
0.72
85°C
1.0
0
10
20
30
40
50
60
70
80
−2.0
2
12
22
32
42
52
62
72
82
92
102
112
122
132
142
152
162
172
182
ENABLE THRESHOLD (V)
0.88
90
T, TEMPERATURE (°C)
DAC CODE
Figure 6. Enable Threshold vs. Temperature
Figure 7. Remote Sense Amplifier Bias Error
vs. DAC Code
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11
NCP5399
TYPICAL CHARACTERISTICS
6.35
6.30
1.45
DAC SLEW RATE (mV/s)
VDRP SOURCE CURRENT (mA)
1.50
1.40
1.35
1.30
1.25
0
10
20
30
40
50
60
70
80
Falling
6.25
6.20
6.10
6.05
6.00
90
Rising
6.15
0
10
20
30
40
50
60
70
80
T, TEMPERATURE (°C)
T, TEMPERATURE (°C)
Figure 8. VDRP Source Current vs.
Temperature
Figure 9. DAC Slew Rate vs. Temperature
3.0
3.0
2.0
2.0
90
DEVIATION (%)
VDRP OFFSET (mV)
Sinking
1.0
0.0
−1.0
Sourcing
1.0
0.0
0
10
20
30
40
50
60
70
80
−1.0
90
0
10
20
30
40
50
60
70
80
T, TEMPERATURE (°C)
T, TEMPERATURE (°C)
Figure 10. VDRP Offset vs. Temperature
Figure 11. PWM Output Resistance Deviation
vs. Temperature
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90
NCP5399
FUNCTIONAL DESCRIPTION
General
sense amplifier must be connected across the current
sensing element of the phase controlled by the
corresponding gate output (GATE1 or GATE3). If a phase
is unused, the Current Sense inputs of the unused channel
should be connected in parallel with the corresponding
Current Sense inputs of the other channel. In this way, the
CS to VDRP, and the CS to ILIM gains are double the
values given in the specifications above, which improves
accuracy. A voltage is generated across the current sense
element (such as an inductor or sense resistor) by the
current flowing in that phase. The outputs of the current
sense amplifiers are used to control three functions. First,
the outputs control the adaptive voltage positioning, where
the output voltage is actively controlled according to the
total output current. In this function, current sense outputs
are summed so that the total output current is used. This
summed output signal is also fed to the current limit circuit.
Finally, the individual phase currents are connected to the
respective PWM comparators. In this way current balance
is accomplished.
The NCP5399 dual edge modulated multiphase PWM
controller is specifically designed with the necessary
features for a high current VR10 CPU power system. The
IC consists of the following blocks: Precision
Programmable DAC, Differential Remote Voltage Sense
Amplifier, High Performance Voltage Error Amplifier,
Differential Current Feedback Amplifiers, Precision
Oscillator and Triangle Wave Generators, and PWM
Comparators. Protection features include Undervoltage
Lockout, Soft−Start, Overcurrent Protection, Overvoltage
Protection, and Power Good Monitor.
Remote Output Sensing Amplifier (RSA)
A true differential amplifier allows the NCP5399 to
measure the Vcore voltage referenced to ground at the
point of load. This configuration allows the regulator to
cancel out voltage drops in the Vcore ground return path.
The RSA also subtracts the DAC (minus VID offset)
voltage, thereby producing an unamplified output error
voltage at the DIFFOUT pin. This output has a 1.3 volt bias
to allow for positive and negative error voltages.
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The
oscillator ’s frequency is programmed by the resistance
connected from the ROSC pin to ground. The user will
usually form this resistance from two resistors in order to
create a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100 kHz/phase
to 1.0 MHz/phase. The oscillator generates 2 triangle
waveforms (symmetrical rising and falling slopes)
between 1.3 V and 2.3 V. The triangle waves have a 180
degree phase delay between them.
Precision Programmable DAC
A precision programmable DAC with 2 options is
provided. These DAC’s have 0.5% accuracy over the
entire operating temperature range of the part. The DAC
is selected by the voltage applied to pin28 − DAC_SEL.
The DAC table can be changed dynamically either before
or after ENABLE.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as
the controller of a voltage regulator, a capacitor from
COMP to VFB is required for stable unity gain test
configurations.
PWM Comparators with Hysteresis
Both PWM comparators receive the error amplifier
output signal at their noninverting input. Each comparator
receives one of the triangle waves offset by 1.3 V at it’s
inverting input. The output of the comparators generate the
PWM outputs GATE1 and GATE3. During steady state
operation, the duty cycle will center on the valley of the
triangle waveform, with steady state duty cycle calculated
by Vout/Vin. During a transient event, both high and low
comparator output transitions shift phase to the points
where the error amplifier output intersects the down and up
ramp of the triangle wave.
GATE Outputs
The part can be configured to run in single−phase or
2−phase mode. In 2−phase mode, both PWM outputs
GATE1 and GATE3 drive external gate drivers as shown in
the 2−phase Applications Schematic. In single−phase
mode, either GATE output can be used.
Differential Current Sense Amplifiers
Two differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
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13
NCP5399
Protection Features
Undervoltage Lockout
Overvoltage Protection and Power Good Monitor
An undervoltage lockout (UVLO) senses the voltage at
the VCC input. During powerup, the VCC input voltage to
the controller is monitored, and the PWM outputs and the
soft−start circuit are disabled until the input voltage
exceeds the threshold voltage of the UVLO comparator.
The UVLO comparator incorporates hysteresis to avoid
chattering, since VCC is likely to decrease as soon as the
converter initiates soft−start.
An output voltage monitor is incorporated. During
normal operation, if the voltage at the DIFFOUT pin
exceeds 1.5 V, the PWRGD pin goes low, the DRVON
signal remains high, the PWM outputs are set low. The
outputs will remain disabled until the VCC voltage is
removed and reapplied. During normal operation, if the
output voltage falls more than 350 mV below the DAC
setting, the PWRGD pin will be set low until the output
rises.
Overcurrent Shutdown
The NCP5399 incorporates a programmable overcurrent
function. A comparator and latch make up this function.
The inverting input of the comparator is connected to the
ILIM pin. The voltage at this pin sets the maximum output
current the converter can produce. The ROSC pin provides
a convenient and accurate reference voltage from which a
resistor divider can create the overcurrent setpoint voltage.
Although not actually disabled, tying the ILIM pin directly
to the ROSC pin sets the limit above useful levels –
effectively disabling overcurrent shutdown. The
comparator noninverting input is the summed current
information from the current sense amplifiers. The
overcurrent latch is set when the current information
exceeds the voltage at the ILIM pin. The outputs are
immediately disabled, the PWRGD and DRVON pins are
pulled low, and the soft−start is pulled low. The outputs will
remain disabled until the VCC voltage is removed and
re−applied, or the ENABLE input is brought low and then
high.
Soft−Start
The NCP5399 incorporates an externally programmable
soft−start. The soft−start circuit works by controlling the
ramp−up of the DAC voltage during powerup. The initial
soft−start pin voltage is 0 V. The soft−start circuitry clamps
the DAC input of the Remote Sense Amplifier to the SS pin
voltage until the SS pin voltage exceeds the DAC setting
(minus VID offset). Thereafter, the clamp on the DAC
voltage is removed and the soft−start pin is pulled to 0 V.
Shunt Regulator
An internal shunt regulator connected to the 5VFILT pin
is provided to convert the 12 V present at the VCC pin to
the 5 V required to power the NCP5399 circuitry. A 220 to
250 ohm resistor rated for at least 0.25 Watt dissipation
must be connected between the VCC and 5VFILT pins, in
order to limit the current drawn from the 12 V source. A
1.0 F ceramic capacitor must be connected from the
5VFILT pin to ground as close to the pins as possible.
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14
NCP5399
Programming the Switching Frequency
The switching frequency of the NCP5399 is controlled
by the current flowing out of the Rosc pin. Since the voltage
on the Rosc pin is fixed at 2 V, the current out of the pin,
and the operating frequency is a function of the sum of the
resistance of RLIM1 and RLIM2. The frequency can be
determined with the following formula:
Freq + 7750 Rosc−0.8887
Rosc +
(eq. 1)
23790
Freq1.1252
Where Freq is the switching frequency (per phase) in
kHz, and Rosc is the sum of the resistance RLIM1 and
RLIM2 in kohm.
Fs (kHz)
10000
1000
Series 1
100
0
20
40
60
80
100
120
140
Rosc, (RLIM1 + RLIM2) (k)
Figure 12.
The current limit function is based on the total sensed
current of all phases multiplied by a gain of 6. DCR sensed
inductor current is function of the winding temperature.
The best approach is to set the maximum current limit
based on the expected average maximum temperature of
the inductor windings.
DCRTmax + DCR25C ·
(eq. 2)
(1 ) 0.00393 (T max −25))
Calculate the current limit voltage:
ǒ
VILIMIT ^ 6 · IMIN_OCP · DCRTmax )
ǓǓ
ǒ
DCRTmax · Vout
· Vin−Vout * (N−1) · Vout
L
L
2 · Vin · Fsw
(eq. 3)
Solve for the individual resistors:
RLIM2 +
VILIMIT · RTOTAL
2·V
RLIM1 + RTOTAL−RLIM2
(eq. 4)
(eq. 5)
Final Equation for the Current Limit Threshold
ILIMIT(Tinductor) ^
ǒ
2 · V · RLIM2
RLIM1)RLIM2
Ǔ
6 · (DCR25C · (1 ) 0.00393(TInductor−25)))
Inductor Selection
When using inductor current sensing it is recommended
that the inductor does not saturate by more than 10% at
maximum load. The inductor also must not go into hard
saturation before current limit trips. The demo board includes
*
ǒ
Ǔ
Vout
· Vin−Vout * (N−1) · Vout
L
L
2 · Vin · Fsw
(eq. 6)
a two phase output filter using the T50−8 core from
Micrometals with 4turns and a DCR target of 0.75 m @
25°C. Smaller DCR values can be used, however, current
sharing accuracy and droop accuracy decrease as DCR
decreases.
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15
NCP5399
Inductor Current Sense Compensation
The NCP5399 uses the inductor current sensing method.
This method uses an RC filter to cancel out the inductance
of the inductor and recover the voltage that is the result of
Rsense(T) +
the current flowing through the inductor’s DCR. This is
done by matching the RC time constant of the current sense
filter to the L/DCR time constant. The first cut approach is
to use a 0.1 F capacitor for C and then solve for R.
L
0.1 · F · DCR25C · (1 ) 0.00393 · (T−25))
(eq. 7)
Because the inductor value is a function of load and
inductor temperature final selection of R is best done
experimentally on the bench by monitoring the Vdroop pin
and performing a step load test on the actual solution.
Simple Average PSPICE Model
A simple state average model shown in Figure 14 can be
used to determine a stable solution and provide insight into
the control system.
Figure 13.
E1
+
+
− −
E
0 GAIN = 6
12
−
+
−
+
VRamp_min
1.3 V
0
−
+
L
1
DCR
2
(250e−9/2)
Vin
12
1
4
RDRP
5.11 k
RF
CF
4.3 k
1.5 n
680 p
Unity
Gain
BW = 15 MHz R6
C3
10.6 n
0.75 m
CCer
(22e−6*18)
1Aac
ESRCer
0Adc
(1.5e−3/18)
2
ESLBulk
(3.5e−9/10)
ESLCer
(1.5e−9/18)
1
1
+
−
I1 = 10
I2 = 110
TD = 10u
TR = 50n
TF = 50n
PW = 40u
PER = 80u
I2
+
−
0
CFB1
1E3
RBRD
ESRBulk
(7e−3/10)
2
0
22 p
2
100 p
CBulk
(560e−6*10)
(0.85e−3/2)
Voff
CH
LBRD
RFB1
100
RFB
−+
Voff
Vout
+
−
1k
+
1k
1.3
Voffset
−
0
0
+
VDAC
−
1.25 V
0
Figure 14.
Compensation and Output Filter Design
The values shown on the demo board are a good place to
start for any similar output filter solution. The dynamic
performance can then be adjusted by swapping out various
individual components.
If the required output filter and switching frequency are
significantly different, it’s best to use the available PSPICE
models to design the compensation and output filter from
scratch.
The design target for this demo board was 1.0 m out to
2.0 MHz. The phase switching frequency is currently set to
330 kHz. It can easily be seen that the board impedance of
0.75 m between the load and the bulk capacitance has a
large effect on the output filter. In this case the ten 560 F
bulk capacitors have an ESR of 7.0 m. Thus the bulk ESR
plus the board impedance is 0.7 m + 0.75 m or
1.45 m. The actual output filter impedance does not drop
to 1.0 m until the ceramic breaks in at over 375 kHz. The
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16
NCP5399
controller must provide some loop gain slightly less than
one out to a frequency in excess 300 kHz. At frequencies
below where the bulk capacitance ESR breaks with the
bulk capacitance, the DC−DC converter must have
sufficiently high gain to control the output impedance
completely. Standard Type−3 compensation works well
with the NCP5399. RFB1 should be kept above 50 to
ensure compensator stability.
The goal is to compensate the system such that the
resulting gain generates constant output impedance from
DC up to the frequency where the ceramic takes over
holding the impedance below 1.0 m. See the example of
the locations of the poles and zeros that were set to optimize
the model above.
Zout Open Loop
Zout Closed Loop
Open Loop Gain with Current loop Closed
80
Voltage Loop Compensation Gain
1/(2*PI*CFB1*(RFB1+RFB))
60
1/(2*PI*CF*RF)
40
20
1/(2*PI*RF*CH)
RF/RFB1
RF/RFB
Error Amp
Open Loop
Gain
dB
0
1/(2*PI*(RBRD+ESRBulk)*CBulk)
−20
−40
1/(2*PI*SQRT(ESL_Cer*CCer))
1mOhm
−60
−80
−100
100
1/(2*PI*CCer*(RBRD+ESRBulk))
1000
10000
100000
1000000
10000000
Frequency
Figure 15.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk
and ceramic capacitor type output filter.
1
1
+
2 · CF · RF
2 · (RBRD ) ESRBulk) · CBulk
1
1
+
2 · CFBI · (RFBI ) RFB)
2 · CCer * (RBRD ) ESRBulk)
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17
(eq. 8)
NCP5399
RFB should be set to provide optimal thermal
compensation in conjunction with thermistor RT2, RISO1
and RISO2. With RFB set to 1.0 k, RFB1 is usually set to
100 for maximum phase boost, and the value of RF is
typically set to 4.0 k.
offset which is proportional to the output current thereby
forcing a controlled, resistive output impedance.
RRDP determines the target output impedance by the
basic equation:
Vout + Zout + RFB · DCR · 6
Iout
RDRP
RFB · DCR · 6
RDRP +
Zout
Droop Injection and Thermal Compensation
The VDRP signal is generated by summing the sensed
output currents for each phase and applying a gain of
approximately six. VDRP is externally summed into the
feedback network by the resistor RDRP. This introduces an
(eq. 9)
The value of the inductor’s DCR varies with temperature
according to the following equation 11:
DCR(T) + DCR25C · (1 ) 0.00393(T−25))
The system can be thermally compensated to cancel this
effect to a great degree by adding an NTC (negative
temperature coefficient resistor) in parallel with RFB to
reduce the droop gain as the temperature increases. The
NTC device is nonlinear. Putting a resistor in series with the
(eq. 10)
NTC helps make the device appear more linear with
temperature. The series resistor is split and inserted on both
sides of the NTC to reduce noise injection into the feedback
loop. The recommended total value for RISO1 plus RISO2
is approximately 1.0 k.
The output impedance varies with inductor temperature by the equation:
Ĉ Zout(T) +
RFB · DCR25C · (1 ) 0.00393(T−25)) · 6
Rdroop
(eq. 11)
By including the NTC RT2 and the series isolation resistors the new equation becomes:
Zout(T) +
RFB · (RISO1)RT2(T))RISO2)
RFB)RISO1)RT2(T))RISO2
· DCR25C · (1 ) 0.00393(T−25)) · 6
Rdroop
OVP
The overvoltage protection threshold is not adjustable.
OVP protection is enabled as soon as soft−start begins and
is disabled when the part is disabled. When OVP is tripped,
the controller commands all four gate drivers to enable
their low side MOSFETs, and VR_RDY transitions low. In
order to recover from an OVP condition, VCC must fall
below the UVLO threshold. See the state diagram for
further details. The OVP circuit monitors the output of
DIFFOUT. If the DIFFOUT signal reaches 180 mV above
the nominal 1.3 V offset the OVP will trip. The DIFFOUT
signal is the difference between the output voltage and the
DAC voltage plus the 1.3 V internal offset. This results in
the OVP tracking the DAC voltage even during a dynamic
change in the VID setting during operation.
The typical equation of a NTC is based on a curve fit
equation 14.
1 Ǔƫ
ƪǒ2731) TǓ * ǒ298
RT2(T) + RT225C · e
(eq. 12)
(eq. 13)
The demo board is populated with a 10 k NTC with a
Beta of 4300. Figure 16 shows the uncompensated and
compensated output impedance versus temperature.
Gate Driver and MOSFET Selection
ON Semiconductor provides the NCP3418B as a
companion gate driver IC. The NCP3418B driver is
optimized to work with a range of MOSFETs commonly
used in CPU applications. The NCP3418B provides special
functionality and is required for the high performance
dynamic VID operation of the part. Contact your local
ON Semiconductor applications engineer for MOSFET
recommendations.
Figure 16. Uncompensated and Compensated Output
Impedance vs. Temperature
ON Semiconductor provides an excel spreadsheet to
help with the selection of the NTC. The actual selection of
the NTC will be effected by the location of the output
inductor with respect to the NTC and airflow, and should
be verified with an actual system thermal solution.
Board Stack−Up
The demo board follows the recommended Intel
Stack−up and copper thickness as shown.
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18
NCP5399
Figure 17.
Board Layout
A complete Allegro ATX and BTX demo board layout
file and schematics are available by request at
www.onsemi.com and can be viewed using the Allegro
Free Physical Viewer 15.x from the Cadence website
http://www.cadence.com/.
Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further information or layout review contact
ON Semiconductor.
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19
NCP5399
PACKAGE DIMENSIONS
A1
A
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
32
25
0.20 (0.008) AB T-U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
AC T-U Z
AE
DETAIL Y
É
É
É
É
−Z−
9
4X
0.20 (0.008) AC T-U Z
S1
F
S
8X
J
R
−AB−
SECTION AE−AE
C E
−AC−
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
http://onsemi.com
20
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
0.10 (0.004) AC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE D
DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
D
DETAIL AD
G
SEATING
PLANE
M_
M
N
9
0.20 (0.008)
B1
NCP5399
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485AM−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32X
0.08 C
32X
A1
SIDE VIEW
L
9
D2
C
SEATING
PLANE
SOLDERING FOOTPRINT*
5.30
EXPOSED PAD
2.30
K 32X
16
32X
0.63
17
8
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.100 2.200 2.300
5.00 BSC
2.100 2.200 2.300
0.500 BSC
1.000 REF
0.300 0.400 0.500
E2
32X
b
2.30 5.30
24
1
32
25
e
0.10 C A B
0.05 C
32X
0.28
NOTE 3
BOTTOM VIEW
28X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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