NCP5603MNR2

NCP5603 High Efficiency Charge Pump Converter The NCP5603 is an integrated circuit dedicated to the medium power White LED applications. The power conversion is achieved by means of a charge pump structure, using two external ceramic capacitors, making the system extremely tiny. The device supplies a constant voltage to the load from a low battery voltage source. It is particularly suited for the High Efficiency LED used in low cost, low power applications, with high extended battery life. Features http://onsemi.com MARKING DIAGRAM • • • • • • • • • • Wide Battery Supply Voltage Range: 2.7 < VCC < 5.5 V Automatic Operating Mode 1X, 1.5X and 2X Improves Efficiency Dimmable Output Current Up to 350 mA Output Pulsed Current Selectable Output Voltage High Efficiency Up To 90% Supports 2.5 kV ESD, Human Body Model Supports 200 V Machine Model ESD Low 40 mA Short Circuit Current Pb−Free Package is Available DFN10 MN SUFFIX CASE 485C 5603 ALYW G 5603 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Applications • High Power LED • Back Light Display • High Power Flash PIN CONNECTIONS Vout C1P Vbat Fsel Vsel 1 2 3 4 5 (Top View) 10 C2P 9 8 7 6 C1N GND C2N EN ORDERING INFORMATION Device NCP5603MNR2 Package Shipping† QFN10, 3x3 3000/ Tape & Reel NCP5603MNR2G QFN10, 3x3 3000/ Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2005 1 November, 2005 − Rev. 1 Publication Order Number: NCP5603/D NCP5603 Vbat C3 GND 4.7 mF/16 V 2 C1 1 mF/16 V C1P C2P 9 C1N Vout 3 U1 Vbat C2N 7 C2 1 mF/16 V C4 GND 1 mF/16 V 10 1 PWM FSEL VSEL 6 EN/PWM 4 Fsel 5 Vsel 8 GND D1 GND NCP5603 LWT67C LWT67C LWT67C D2 D3 10 W 10 W 10 W D4 10 W R4 R1 R2 GND Figure 1. Typical Application http://onsemi.com 2 R3 LWT67C NCP5603 Vbat Vbat 3 Vbat 10 C2P LEVEL SHIFTER AND MOSFET DRIVE POWER SWITCHES 7 C2N Thermal Shutdown 9 C1N Vbat LOGIC AND ANALOG CONTROL 2 C1P Vout 1 Vout Fsel 4 GND Vbat − Vsel 5 + EN 6 BANDGAP GND GND 8 GND Figure 2. Block Diagram http://onsemi.com 3 NCP5603 PIN FUNCTION DESCRIPTION Pin 1 Symbol Vout Type OUTPUT, PWR Description This pin supplies the regulated voltage to the external LED. Since high current transients are present in this pin, care must be observed to avoid voltage spikes in the system. Good high frequency layout technique must be observed. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P, pin 9. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. This pin shall be connected to the power source, and must be decoupled to Ground by a low ESR capacitor (2.2 mF/6.3 V ceramic or better (see Note 1)). This pin is used to program the operating frequency: Fsel = 0 → Fop = 262 kHz Fsel = 1 → Fop = 650 kHz This pin setup the output voltage: Vsel = 0 → Vout = 4.5 V Vsel = 1 → Vout = 5.0 V This pin controls the activity of the NCP5603 chip: EN/PWM = Low → the chip is deactivated, the load is disconnected EN/PWM = High → the chip is activated and the load is connected to the regulated output current. The NCP5603 can operate either in a continuous mode (EN/PWM = High), or can be controlled by a PWM pulse applied to EN/PWM to dim the output light. When EN/PWM is Low, the external load is disconnected from the converter, providing a very low standby current. The pull down built−in resistance makes sure the chip is deactivated even if the EN/PWM pin is disconnected (see Note 2). 7 C2N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P, pin 10. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. This pin combines the Signal ground and the Power ground and must be connected to the system ground. Using good quality ground plane is mandatory to avoid spikes on the logic signal lines. One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N, pin 2. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. One side of the external charge pump capacitor is connected to this pin, associated with C2N, pin 7. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 2 C1N POWER 3 4 Vbat Fsel POWER INPUT, Digital 5 Vsel INPUT, Digital 6 EN/PWM INPUT, Digital 8 GND GROUND 9 C1P POWER 10 C2P POWER 1. Using ceramic 16 V working voltage capacitors is recommended to compensate the DC bias effect encountered with such type of capacitors. 2. Any external impedance connected to pin 6 shall be 10 kW or higher. http://onsemi.com 4 NCP5603 MAXIMUM RATINGS Rating Power Supply Voltage Power Supply Current Digital Input Pins Digital Input Pins Output Voltage ESD Capability (Note 3) Human Body Model Machine Model QFN10, 3x3 Package Power Dissipation @ Tamb = +85°C Thermal Resistance, Junction−to−Air (RqJA) Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating Moisture Sensitivity Level (MSL) Symbol Vbat Ibat Vin Iin Vout VESD 2.5 200 PDS RqJA TA TJ TJmax Tstg 580 68.5 −40 to +85 −40 to +125 +150 −65 to +150 100 mA per JEDEC standard, JESD78 1 per IPC/JEDEC standard, J−STD−020A kV V mW °C/W °C °C °C °C Value 7.0 800 −0.5 V < Vbat < Vbat +0.5 V < 6.0 V "5.0 5.5 Unit V mA V mA V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.5 kV per JEDEC Standard: JESD22−A114 Machine Model (MM) "200 V per JEDEC Standard: JESD22−A115. 4. The maximum package power dissipation limit must not be exceeded. http://onsemi.com 5 NCP5603 ELECTRICAL CHARACTERISTICS @ 2.85 V < Vbat < 5.5 V (−40°C to +85°C ambient temperature, unless otherwise noted). Characteristic Power Supply Quiescent Current @ Vbat = 3.7 V, Iout = 0 mA @ Pulsed Clock Fop = 262 kHz @ Pulsed Clock Fop = 650 kHz @ Continuous Clock Fop = 262 kHz @ Continuous Clock Fop = 650 kHz Shutdown Current @ Iout = 0 mA, EN/PWM = L @ 2.85 < Vbat < 4.2 V @ Vbat = 5.5 V Output Voltage Regulation @ Vsel = 1, 2.85 V < Vbat < 4.5 V @ Vsel = 0, 2.85 V < Vbat < 4.5 V Continuous DC Load Current (Note 7) Cin = 1.0 mF, CFLY = 1.0 mF, Cout = 1.0 mF @ Vsel = 1, 3.2 V < Vbat < 4.5 V @ Vsel = 0, 3.2 V < Vbat < 5.5 V @ Vsel = 1, 2.85 V < Vbat < 4.5 V @ Vsel = 0, 2.85 V < Vbat < 5.5 V Pulsed Output Current Cin = 10 mF, CFLY = 1.0 mF, Cout = 10 mF, Vbat = 3.6 V Pwidth = 500 ms, −40°C < TA < +65°C Output Continuous Short Circuit Current, Vout = 0 V Operating Frequency (Note 5) @ Fsel = 0, 2.85 V < Vbat < 4.5 V @ Fsel = 1, 2.85 V < Vbat < 4.5 V Output Voltage Ripple (Note 6) Fop = 262 kHz, Iout = 60 mA (Note 7) @ Cout = 1.0 mF @ Cout = 4.7 mF Digital Input High Level Digital Input Low level Output Power Efficiency @ Vbat = 3.3 V, Vout = 5.0 V, Iout = 60 mA, Fop = 262 kHz @ Vbat = 3.9 V, Vout = 5.0 V, Iout = 160 mA, Fop = 650 kHz Thermal Shut Down Protection Hysteresis 3 Pin 3 3 Symbol Vbat Iqsc − − − − 3 Istdb − − 3 Vout 4.75 4.275 3 Iout − − − − 3 IFLH − 3 Isch Fop 210 500 VPP − − 4, 5, 6 4, 5, 6 VIH VIL Ph − − THSD − − 75 84 160 20 − − − − °C 1.3 − 150 25 − − − 60 − 0.4 V V % 262 650 320 1000 mV − 350 40 − 100 mA kHz − − − − 160 200 80 120 mA 5.0 4.5 5.25 4.725 mA − − 2.5 4.0 V − − 1.0 2.1 0.8 1.2 − − mA Min 2.85 Typ − Max 5.5 Unit V mA 5. Temperature range guaranteed by design, not production tested. 6. Smaller footprint associated to lower working voltages (10 V or 6.3 V, size 0805 or 0602) can be used, but care must be observed to prevent DC bias effect on the capacitance final value. See capacitor manufacturer data sheets. 7. Ceramic X7R, ESR < 100 mW, SMD type capacitors are mandatory to achieve the Iout specifications. Depending upon the PCB layout, it might be necessary to use two 2.2 mF/6.3 V/ceramic capacitors in parallel, yielding an improved Vout noise over the temperature range. On the other hand, care must be observed to take into account the DC bias impact on the capacitance value. See ceramic capacitor manufacturer data sheets. 8. Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to Vbat. http://onsemi.com 6 NCP5603 TYPICAL CHARACTERISTICS 100 IOUT = 120 mA EFFICIENCY (%) 100 IOUT = 120 mA 90 EFFICIENCY (%) 90 80 80 70 70 60 60 50 2.5 3.0 3.5 4.0 Vin (V) 4.5 5.0 5.5 50 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Figure 3. Operating Modes Transitions and Output Power Efficiency @ Vout = 4.5 V/262 kHz 100 IOUT = 160 mA 90 EFFICIENCY (%) −40°C 25°C 80 85°C Figure 4. Operating Modes Transitions and Output Power Efficiency @ Vout = 4.5 V/650 kHz 70 60 50 2.5 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Figure 5. Operating Modes Transitions and Output Power Efficiency @ Vout = 5.0 V/650 kHz Figure 6. Typical Output Voltage Ripple 4.8 IOUT = 200 mA 4.7 4.6 Vout (V) 25°C 4.5 4.4 4.3 4.2 2.5 −40°C 85°C 3.0 3.5 4.0 Vbat (V) 4.5 5.0 5.5 Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S, ILED = 25mA Figure 7. Typical Output Voltage Line Regulation Figure 8. Output Voltage Startup from Scratch http://onsemi.com 7 NCP5603 TYPICAL CHARACTERISTICS Test conditions: Vbat = 3.6 V, Vout = 5 V, Load = 4*LW87S, ILED = 25mA Figure 9. Typical PWM Dimming VCC 3 C1 10 mF/10 V GND C2 1 mF/6.3 V EN PWR−FLASH FSEL GND VSEL NCP5603 Vbat C1P C1N EN/PWM Fsel Vsel GND R1 1W GND C2N 7 C2 1 mF/16 V 2 C1P Vout 10 1 9 6 4 5 8 C4 10 mF D1 OSRAM: LWW5SG GOLDEN DRAGON GND GND Figure 10. Typical High Power Flash Circuit http://onsemi.com 8 NCP5603 500 450 400 350 Iout (mA) 300 250 200 150 100 50 0 2.5 3.0 Vout = 4.5 V FSEL = 0 Load = OSRAM / LWW5SG PWR SWITCH = MGSF1N03 3.5 Vbat (V) 4.0 4.5 R=1W R = 2.2 W R=0W Figure 11. NCP5603 Output Current Table 1. Ceramic Preferred Capacitors Manufacturer TDK TDK TDK Type/Series C3216X5R1C475MT C2012X5R1C225MT C2012X5R1C105MT Format 1206 0805 0805 Value 4.7 mF / 16 V 2.2 mF / 16 V 1.0 mF / 16 V http://onsemi.com 9 NCP5603 GND C3 1.0 mF/16 V D4 1 D3 Vout LW67C D2 LW67C D1 LW67C C2 1 mF/16 V 10 LW67C TP2 1 ISENSE R9 82 W R8 82 W R7 82 W R6 82 W GND TP1 7 C2N C1P 1 Vout EN/PWM U1 NCP5603 3 2 9 6 4 5 8 GND C1N C1P Vsel Fsel Vbat C1 1 mF/16 V GND Vsel S3 Vsel GND R4 VCC Fsel C7 100 nF 6 7 U3A MC14538B Q Q C4 4.7 mF/16 V S2 Fsel GND 10 k R5 10 k 10 U3B MC14538B 9 C8 100 nF 15 C 12 A 11 B 13 CLR GND R11 1.5 k D5 PWM GND GND Q VCC GND P1 200 kA RC A B CLR C6 100 nF GND C5 33 nF GND VCC S1 4 NL27WZ14 U2B VCC CNT/PWM 3 6 NL27WZ14 U2A GND Z3 GND GROUND 1 10 S4 POWER 1 GND + 2 − + PK1 2 x 1.5 V VCC Adjust PWM 10 k R10 10 k 14 GND 2 1 4 4 mm 4 mm R2 4 100 k GND VCC J1 J2 3 R1 Figure 12. Evaluation Board Schematic Diagram http://onsemi.com 5 3 R3 RC C Q + NCP5603 Figure 13. Evaluation Board: Silk View (Top View) http://onsemi.com 11 NCP5603 PACKAGE DIMENSIONS DFN10 MN SUFFIX CASE 485C−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 EDGE OF PACKAGE PIN 1 REFERENCE 2X 2X 0.15 C 0.15 C 0.10 C 10X 0.08 C SIDE VIEW A1 C 10X L 1 5 A1 E2 10X K DETAIL B Side View (Optional) 10 10X 6 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 0.5651 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 ÉÉ ÉÉ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ DETAIL B E L1 DETAIL A Bottom View (Optional) TOP VIEW (A3) A SEATING PLANE EXPOSED Cu D2 e DETAIL A MOLD CMPD A3 SOLDERING FOOTPRINT* 2.6016 2.1746 1.8508 3.3048 10X 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS NCP5603 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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