DATA SHEET
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Linear Voltage Regulator Ultra-Low Iq, Wide Input
Voltage, Low Dropout
MARKING
DIAGRAMS
XDFN6
CASE 711AE
50 mA
1
XX MG
G
NCP715
The NCP715 is 50 mA LDO Linear Voltage Regulator. It is a very
stable and accurate device with ultra−low ground current consumption
(4.7 mA over the full output load range) and a wide input voltage range
(up to 24 V). The regulator incorporates several protection features
such as Thermal Shutdown and Current Limiting.
Features
• Operating Input Voltage Range: 2.5 V to 24 V
• Fixed Voltage Options Available: 1.2 V to 5.3 V
• Ultra Low Quiescent Current: Max. 4.7 mA Over Full Load and
•
•
•
•
•
•
Temperature
±2% Accuracy Over Full Load, Line and Temperature Variations
PSRR: 52 dB at 100 kHz
Noise: 190 mVRMS from 200 Hz to 100 kHz
Thermal Shutdown and Current Limit protection
Available in XDFN6 1.5 x 1.5 mm, SC−70 (SC−88A) and TSOP−5
Packages
These are Pb−Free Devices
XX MG
G
SC−70−5
(SC−88A)
CASE 419A
5
1
TSOP−5
CASE 483
5
XXX MG
G
1
XX
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
Typical Applications
• Portable Equipment
• Communication Systems
2.5 V < Vout < 24 V
1 mF
Ceramic
OUT
IN
1.2 V < Vout < 5.3 V
NCP715
NC
GND
NC
1 mF
Ceramic
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2016
September, 2022 − Rev. 7
1
Publication Order Number:
NCP715/D
NCP715
IN
THERMAL
SHUTDOWN
UVLO
BANDGAP
REFERENCE
MOSFET
DRIVER WITH
CURRENT LIMIT
OUT
EEPROM
GND
Figure 2. Simplified Block Diagram
Figure 3. Pin Description
PIN FUNCTION DESCRIPTION
Pin No.
SC−70
XDFN6
TSOP−5
Pin Name
5
6
3
OUT
Regulated output voltage pin. A small 0.47 mF ceramic capacitor is needed from this pin to
ground to assure stability.
1
2
4
N/C
No connection. This pin can be tied to ground to improve thermal dissipation or left
disconnected.
2
3
1
GND
Power supply ground.
3
4
5
N/C
No connection. This pin can be tied to ground to improve thermal dissipation or left
disconnected.
−
5
−
N/C
No connection. This pin can be tied to ground to improve thermal dissipation or left
disconnected.
4
1
2
IN
Description
Input pin. A small capacitor is needed from this pin to ground to assure stability.
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NCP715
ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage (Note 1)
Output Voltage
Output Short Circuit Duration
Maximum Junction Temperature
Operating Ambient Temperature Range
Storage Temperature Range
Symbol
Value
Unit
VIN
−0.3 to 24
V
VOUT
−0.3 to 6
V
tSC
Indefinite
s
TJ(MAX)
150
°C
TA
−40 to 125
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22−A114
ESD Machine Model tested per EIA/JESD22−A115
ESD Charged Device Model tested per EIA/JESD22−C101E
Latch up Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SC−70
Thermal Resistance, Junction−to−Air
RqJA
390
°C/W
Thermal Characteristics, XDFN6
Thermal Resistance, Junction−to−Air
RqJA
260
°C/W
Thermal Characteristics, TSOP−5
Thermal Resistance, Junction−to−Air
RqJA
250
°C/W
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 1.2 V
−40°C ≤ TJ ≤ 125°C; VIN = 2.5 V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 5)
Parameter
Operating Input Voltage
Test Conditions
Symbol
Min
IOUT ≤ 10 mA
VIN
10 mA< IOUT < 50 mA
Output Voltage Accuracy
Typ
Max
Unit
2.5
24
V
3.0
24
2.5 V < VIN < 24 V, 0 < IOUT ≤ 10 mA
VOUT
1.164
1.2
1.236
V
3.0 V < VIN < 24 V, 0 mA < IOUT < 50 mA
VOUT
1.164
1.2
1.236
V
3.0 V < VIN < 24 V, 1 mA < IOUT < 50 mA,
−20°C < TJ < 125°C;
VOUT
1.176
1.2
1.224
V
Line Regulation
2.5 V ≤ VIN ≤ 24 V, IOUT = 1 mA
RegLINE
2
mV
Load Regulation
IOUT = 0 mA to 50 mA
RegLOAD
5
mV
Dropout Voltage (Note 3)
Maximum Output Current
VDO
(Note 6)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 4)
Thermal Shutdown Hysteresis (Note 4)
VIN = 3.0 V, VOUT = 1.2 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT= 10 mF
f = 100 kHz
−
mV
200
mA
4.2
mA
5.8
PSRR
60
dB
VOUT = 1.2 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
65
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
3. Not Characterized at VIN = 3.0 V, VOUT = 1.2 V, IOUT = 50 mA.
4. Guaranteed by design and characterization.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA =
25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
6. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 1.5 V
−40°C ≤ TJ ≤ 125°C; VIN = 2.5 V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 9)
Parameter
Operating Input Voltage
Test Conditions
Symbol
Min
IOUT ≤ 10 mA
VIN
10 mA < IOUT < 50 mA
Output Voltage Accuracy
Typ
Max
Unit
2.5
24
V
3.0
24
2.5 V < VIN < 24 V, 0 < IOUT ≤ 10 mA
VOUT
1.455
1.5
1.545
V
3.0 V < VIN < 24 V, 0 < IOUT < 50 mA
VOUT
1.455
1.5
1.545
V
3.0 V < VIN < 24 V, 1 mA < IOUT < 50 mA,
−20°C < TJ < 125°C;
VOUT
1.470
1.5
1.530
V
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, IOUT = 1 mA
RegLINE
2
mV
Load Regulation
IOUT = 0 mA to 50 mA
RegLOAD
5
mV
Dropout Voltage (Note 7)
Maximum Output Current
Ground Current
VDO
(Note 10)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 8)
Thermal Shutdown Hysteresis (Note 8)
VIN = 3.0 V, VOUT = 1.5 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT = 10 mF
f = 100 kHz
−
mV
200
mA
4.2
mA
5.8
mA
PSRR
56
dB
VOUT = 1.5 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
75
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
7. Not Characterized at VIN = 3.0 V, VOUT = 1.5 V, IOUT = 50 mA.
8. Guaranteed by design and characterization.
9. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at
TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
10. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 1.8 V
−40°C ≤ TJ ≤ 125°C; VIN = 2.8V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 13)
Parameter
Operating Input Voltage
Test Conditions
Symbol
Min
IOUT ≤10 mA
VIN
10 mA < IOUT < 50 mA
Output Voltage Accuracy
Typ
Max
Unit
2.8
24
V
3.0
24
2.8 V < VIN < 24 V, 0 < IOUT < 10 mA
VOUT
1.746
1.8
1.854
V
3.0 V < VIN < 24 V, 1 mA < IOUT < 50 mA,
−20°C < TJ < 125°C;
VOUT
1.764
1.8
1.836
V
Line Regulation
3 V ≤ VIN ≤ 24 V, IOUT = 1 mA
RegLINE
3
mV
Load Regulation
IOUT = 0 mA to 50 mA
RegLOAD
10
mV
Dropout Voltage (Note 11)
Maximum Output Current
Ground Current
VDO
(Note 14)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
mV
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 12)
Thermal Shutdown Hysteresis
(Note 12)
VIN = 3.0 V, VOUT = 1.8 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT =10 mF
f = 100 kHz
200
mA
4.2
mA
5.8
mA
PSRR
60
dB
VOUT = 1.8 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
95
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
11. Not characterized at VIN = 3.0 V, VOUT = 1.8 V, IOUT = 50 mA
12. Guaranteed by design and characterization.
13. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA =
25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
14. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 2.5 V
−40°C ≤ TJ ≤ 125°C; VIN = 3.5 V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 17)
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage
0 < IOUT < 50 mA
VIN
3.5
Output Voltage Accuracy
3.5 V < VIN < 24 V, 0 < IOUT < 50 mA
VOUT
2.45
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, IOUT = 1 mA
RegLINE
3
mV
Load Regulation
IOUT = 0 mA to 50 mA
RegLOAD
10
mV
Dropout Voltage (Note 15)
VDO = VIN – (VOUT(NOM) – 75 mV)
IOUT = 50 mA
VDO
260
Maximum Output Current
(Note 18)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
Ground Current
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 16)
Thermal Shutdown Hysteresis
(Note 16)
Typ
2.5
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
VIN = 3.5 V, VOUT = 2.5 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT =10 mF
f = 100 kHz
Max
Unit
24
V
2.55
V
450
mV
200
mA
4.2
mA
5.8
mA
PSRR
60
dB
VOUT = 2.5 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
115
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
15. Characterized when VOUT falls 75 mV below the regulated voltage and only for devices with VOUT = 2.5 V.
16. Guaranteed by design and characterization.
17. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at
TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
18. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 3.0 V
−40°C ≤ TJ ≤ 125°C; VIN = 4.0 V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 21)
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage
0 < IOUT < 50 mA
VIN
4.0
Output Voltage Accuracy
4.0 V < VIN < 24 V, 0< IOUT < 50 mA
VOUT
2.94
Typ
3.0
Max
Unit
24
V
3.06
V
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, IOUT = 1 mA
RegLINE
3
mV
Load Regulation
IOUT = 0 mA to 50 mA
RegLOAD
10
mV
VDO = VIN – (VOUT(NOM) – 90 mV)
IOUT = 50 mA
VDO
Dropout voltage (Note 19)
Maximum Output Current
Ground current
(Note 22)
IOUT
0 < IOUT < 50 mA, -40 < TA < 85°C
IGND
250
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 20)
Thermal Shutdown Hysteresis
(Note 20)
VIN = 4.0 V, VOUT = 3.0 V
VPP = 100 mV modulation
IOUT = 1 mA, COUT = 10 mF
f = 100 kHz
400
mV
200
mA
4.2
mA
5.8
mA
PSRR
60
dB
VOUT = 3 V, IOUT = 50 mA,
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
135
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
-
25
-
°C
19. Characterized when VOUT falls 90 mV below the regulated voltage and only for devices with VOUT = 3.0 V
20. Guaranteed by design and characterization.
21. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested
at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as
possible.
22. Respect SOA
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 3.3 V
−40°C ≤ TJ ≤ 125°C; VIN = 4.3 V; IOUT = 1 mA, CIN = COUT = 1.0 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 25)
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage
0 < IOUT < 50 mA
VIN
4.3
Output Voltage Accuracy
4.3 V < VIN < 24 V, 0 < IOUT < 50 mA
VOUT
3.234
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, IOUT = 1 mA
Load Regulation
IOUT = 0 mA to 50 mA
VDO = VIN – (VOUT(NOM) – 99 mV)
IOUT = 50 mA
VDO
230
Dropout Voltage (Note 23)
Maximum Output Current
Ground Current
Max
Unit
24
V
3.3
3.366
V
RegLINE
3
10
mV
RegLOAD
10
(Note 26)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
Typ
100
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 24)
Thermal Shutdown Hysteresis
(Note 24)
VIN = 4.3 V, VOUT = 3.3 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT =10 mF
f = 100 kHz
mV
350
mV
200
mA
4.2
mA
5.8
mA
PSRR
60
dB
VOUT = 4.3 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
140
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
23. Characterized when VOUT falls 99 mV below the regulated voltage and only for devices with VOUT = 3.3 V.
24. Guaranteed by design and characterization.
25. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA =
25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
26. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 5.0 V
−40°C ≤ TJ ≤ 125°C; VIN = 6.0 V; IOUT = 1 mA, CIN = COUT = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 29)
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage
0 < IOUT < 50 mA
VIN
6.0
Output Voltage Accuracy
6.0V < VIN < 24V, 0< IOUT < 50 mA
VOUT
4.9
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, Iout = 1mA
Load Regulation
IOUT = 0 mA to 50 mA
VDO = VIN – (VOUT(NOM) – 150 mV)
IOUT = 50 mA
VDO
Dropout Voltage (Note 27)
Maximum Output Current
Ground Current
Max
Unit
24
V
5.0
5.1
V
RegLINE
3
10
mV
RegLOAD
10
30
mV
230
350
mV
200
mA
4.2
mA
5.8
mA
(Note 30)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
Typ
90
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 28)
Thermal Shutdown Hysteresis
(Note 28)
VIN = 6.0 V, VOUT = 5.0 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT =10 mF
f = 100 kHz
PSRR
56
dB
VOUT = 5.0 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
190
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
27. Characterized when VOUT falls 150 mV below the regulated voltage and only for devices with VOUT = 5.0 V.
28. Guaranteed by design and characterization.
29. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA =
25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
30. Respect SOA.
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NCP715
ELECTRICAL CHARACTERISTICS − Voltage Version 5.3 V
−40°C ≤ TJ ≤ 125°C; VIN = 6.3 V; IOUT = 1 mA, CIN = COUT = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 33)
Parameter
Test Conditions
Symbol
Min
Operating Input Voltage
0 < IOUT < 50 mA
VIN
6.3
Output Voltage Accuracy
6.3V < VIN < 24V, 0.1 mA< IOUT < 50 mA
VOUT
5.194
Typ
Max
Unit
24
V
5.3
5.406
V
60
mV
Line Regulation
VOUT + 1 V ≤ VIN ≤ 24 V, IOUT = 1mA
RegLINE
20
Load Regulation
IOUT = 0.1 mA to 50 mA
RegLOAD
20
VDO = VIN – (VOUT(NOM) – 159 mV)
IOUT = 50 mA
VDO
230
Dropout Voltage (Note 31)
Maximum Output Current
Ground Current
(Note 34)
IOUT
0 < IOUT < 50 mA, −40 < TA < 85°C
IGND
90
3.2
0 < IOUT < 50 mA, VIN = 24 V
Power Supply Rejection Ratio
Output Noise Voltage
Thermal Shutdown Temperature
(Note 32)
Thermal Shutdown Hysteresis
(Note 32)
VIN = 6.3 V, VOUT = 5.3 V
VPP = 200 mV modulation
IOUT = 1 mA, COUT =10 mF
f = 100 kHz
mV
350
mV
200
mA
4.2
mA
5.8
mA
PSRR
55
dB
VOUT = 5.3 V, IOUT = 50 mA
f = 200 Hz to 100 kHz, COUT = 10 mF
VN
195
mVrms
Temperature increasing from TJ = +25°C
TSD
170
°C
Temperature falling from TSD
TSDH
−
15
−
°C
31. Characterized when VOUT falls 159 mV below the regulated voltage and only for devices with VOUT = 5.3 V.
32. Guaranteed by design and characterization.
33. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA =
25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
34. Respect SOA.
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NCP715
1.2
2.506
VIN = 3.0 V
1.198
1.197
1.196
VIN = (5.0 − 24.0) V
1.195
1.194
1.193
1.192
−40
NCP715x12xxx
CIN = COUT = 1 mF
IOUT = 1 mA
−20
0
20
VIN = 3.0 V
2.504
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.199
2.502
2.5
VIN = (5.0 − 24.0) V
2.498
2.496
2.494
NCP715x25xxx
CIN = COUT = 1 mF
IOUT = 1 mA
2.492
40
60
80
100
2.49
−40
120
−20
0
3.315
5.015
3.312
5.01
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.02
3.309
3.306
3.303
3.294
−40
NCP715x33xxx
CIN = COUT = 1 mF
IOUT = 1 mA
VIN = 4.3 V to 24 V
−20
0
20
40
60
80
TEMPERATURE (°C)
100
5.005
1.192
1.188
VIN = 3.0 V
VIN = 5.0 V
VIN = 10 V
VIN = 15 V
VIN = 20 V
VIN = 24 V
1.184
1.180
1.176
1.172
0
10
20
30
OUTPUT CURRENT (mA)
120
4.995
NCP715x50xxx
CIN = COUT = 1 mF
IOUT = 1 mA
4.99
4.98
−40
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
2.504
120
NCP715x25xxx
CIN = COUT = 1 mF
TA = 25°C
2.500
2.496
2.492
2.488
VIN = 3.5 V
VIN = 5.0 V
VIN = 10 V
VIN = 15 V
VIN = 20 V
VIN = 24 V
2.484
2.480
2.476
40
−20
Figure 7. Output Voltage vs. Temperature
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.196
100
VIN = 6.0 V
5
4.985
120
NCP715x12xxx
CIN = COUT = 1 mF
TA = 25°C
1.200
80
VIN = (8.0 − 24.0) V
Figure 6. Output Voltage vs. Temperature
1.204
60
Figure 5. Output Voltage vs. Temperature
3.318
3.297
40
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. Output Voltage vs. Temperature
3.3
20
50
2.472
0
Figure 8. Output Voltage vs. Output Current
10
20
30
OUTPUT CURRENT (mA)
40
Figure 9. Output Voltage vs. Output Current
www.onsemi.com
12
50
NCP715
NCP715x33xxx
CIN = COUT = 1 mF
TA = 25°C
OUTPUT VOLTAGE (V)
3.308
3.304
3.300
3.296
3.292
VIN = 4.3 V
VIN = 10 V
VIN = 15 V
VIN = 20 V
VIN = 24 V
3.288
3.284
3.280
0
10
5.016
NCP715x50xxx
CIN = COUT = 1 mF
TA = 25°C
5.008
OUTPUT VOLTAGE (V)
3.312
5.000
4.992
4.984
4.976
VIN = 6.0 V
VIN = 10 V
VIN = 15 V
VIN = 20 V
VIN = 24 V
4.968
4.960
20
30
40
4.952
50
0
10
OUTPUT CURRENT (mA)
Figure 10. Output Voltage vs. Output Current
DROPOUT VOLTAGE (mV)
TA = 125°C
250
TA = 25°C
200
150
TA = −40°C
100
50
0
300
TA = 125°C
250
TA = 25°C
200
150
100
TA = −40°C
50
0
0
10
20
30
40
0
50
10
OUTPUT CURRENT (mA)
400
GND, QUIESCENT CURRENT (mA)
TA = 125°C
250
200
TA = 25°C
150
100
TA = −40°C
50
10
40
50
40
300
0
30
Figure 13. Dropout Voltage vs. Output Current
NCP715x50xxx
CIN = COUT = 1 mF
350
20
OUTPUT CURRENT (mA)
Figure 12. Dropout Voltage vs. Output Current
DROPOUT VOLTAGE (mV)
50
NCP715x33xxx
CIN = COUT = 1 mF
350
300
0
40
400
NCP715x25xxx
CIN = COUT = 1 mF
350
30
Figure 11. Output Voltage vs. Output Current
DROPOUT VOLTAGE (mV)
400
20
OUTPUT CURRENT (mA)
20
30
40
50
NCP715x12xxx
CIN = COUT = 1 mF
TA = 25°C
35
30
25
20
15
IOUT = 0
IOUT = 50 mA
10
5
0
0
5
10
15
20
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
Figure 14. Dropout Voltage vs. Output Current
Figure 15. Ground Current vs. Input Voltage
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13
25
NCP715
IOUT = 0
IOUT = 50 mA
35
40
NCP715x25xxx
CIN = COUT = 1 mF
TA = 25°C
30
GND, QUIESCENT CURRENT (mA)
GND, QUIESCENT CURRENT (mA)
40
25
20
15
10
5
0
0
5
10
15
20
30
25
20
15
10
5
0
25
0
5
10
INPUT VOLTAGE (V)
20
25
Figure 17. Ground Current vs. Input Voltage
4.5
40
NCP715x50xxx
CIN = COUT = 1 mF
TA = 25°C
IOUT = 0
IOUT = 50 mA
35
30
QUIESCENT CURRENT (mA)
GND, QUIESCENT CURRENT (mA)
15
INPUT VOLTAGE (V)
Figure 16. Ground Current vs. Input Voltage
25
20
15
10
5
0
5
10
15
20
4.3
4.0
3.8
3.5
3.3
3.0
2.8
2.5
−40
0
25
VIN = 3 V
VIN = 10 V
VIN = 24 V
−20
0
INPUT VOLTAGE (V)
NCP715x12xxx
CIN = COUT = 1 mF
IOUT = 0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 18. Ground Current vs. Input Voltage
Figure 19. Quiescent Current vs. Temperature
6.0
6.0
NCP715x25xxx
CIN = COUT = 1 mF
IOUT = 0
5.5
5.0
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
NCP715x33xxx
CIN = COUT = 1 mF
TA = 25°C
IOUT = 0
IOUT = 50 mA
35
4.5
4.0
3.5
3.0
2.5
2.0
−40
VIN = 3.5 V
VIN = 10 V
VIN = 24 V
−20
0
20
40
60
80
100
NCP715x33xxx
CIN = COUT = 1 mF
IOUT = 0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
−40
120
VIN = 4.3 V
VIN = 10 V
VIN = 24 V
−20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Quiescent Current vs. Temperature
Figure 20. Quiescent Current vs. Temperature
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14
NCP715
100
NCP715x50xxx
CIN = COUT = 1 mF
IOUT = 0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
−40
VIN = 6 V
VIN = 10 V
VIN = 24 V
−20
0
NCP715x12xxx
COUT = 10 mF
VIN = 3.0 V + 200 mVPP Modulation
TA = 25°C
80
PSRR (dB)
QUIESCENT CURRENT (mA)
6.0
60
IOUT = 1 mA
40
20
IOUT = 50 mA
0
20
40
60
80
100
0.1
120
TEMPERATURE (°C)
PSRR (dB)
40
IOUT = 50 mA
0
100
80
0.1
1
100
0.1
1
10
100
Figure 24. PSRR vs. Frequency
Figure 25. PSRR vs. Frequency
1.6
IOUT = 1 mA
40
20
IOUT = 50 mA
0.1
IOUT = 10 mA
IOUT = 50 mA
FREQUENCY (kHz)
60
0
40
0
1000
IOUT = 1 mA
FREQUENCY (kHz)
NCP715x50xxx
COUT = 10 mF
VIN = 6.0 V + 200 mVPP Modulation
TA = 25°C
1
10
1000
60
20
IOUT = 10 mA
10
100
NCP715x33xxx
COUT = 10 mF
VIN = 4.3 V + 200 mVPP Modulation
TA = 25°C
80
60
20
PSRR (dB)
IOUT = 1 mA
OUTPUT VOLTAGE NOISE (mV/√Hz)
PSRR (dB)
80
10
Figure 23. PSRR vs. Frequency
100
NCP715x25xxx
COUT = 10 mF
VIN = 3.5 V + 200 mVPP Modulation
TA = 25°C
1
FREQUENCY (kHz)
Figure 22. Quiescent Current vs. Temperature
100
IOUT = 10 mA
IOUT = 10 mA
100
1000
1000
COUT = 10 mF, 65.1 mVrms @ 200 Hz − 100 kHz
1.4
COUT = 4.7 mF, 80.5 mVrms @ 200 Hz − 100 kHz
COUT = 2.2 mF, 111.5 mVrms @ 200 Hz − 100 kHz
1.2
COUT = 1.0 mF, 172.1 mVrms @ 200 Hz − 100 kHz
COUT = 0.47 mF, 208 mVrms @ 200 Hz − 100 kHz
1.0
0.8
0.6
0.4
0.2
NCP715x12xxx
IOUT = 50 mA
TA = 25°C
VIN = 3 V
0.0
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 26. PSRR vs. Frequency
Figure 27. Output Spectral Noise Density vs.
Frequency
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15
NCP715
3.5
COUT = 4.7 mF, 128.4 mVrms @ 200 Hz − 100 kHz
COUT = 2.2 mF, 152.2 mVrms @ 200 Hz − 100 kHz
3.0
COUT = 1.0 mF, 172.1 mVrms @ 200 Hz − 100 kHz
COUT = 0.47 mF, 203.6 mVrms @ 200 Hz − 100 kHz
2.5
NCP715x25xxx
IOUT = 50 mA
TA = 25°C
VIN = 3.5 V
2.0
1.5
1.0
0.5
0.0
0.01
0.1
1
10
100
1000
COUT = 10 mF, 137.1 mVrms @ 200 Hz − 100 kHz
4.5
COUT = 4.7 mF, 145.7 mVrms @ 200 Hz − 100 kHz
4.0
COUT = 2.2 mF, 170.6 mVrms @ 200 Hz − 100 kHz
3.5
COUT = 1.0 mF, 220.8 mVrms @ 200 Hz − 100 kHz
COUT = 0.47 mF, 271.1 mVrms @ 200 Hz − 100 kHz
3.0
NCP715x33xxx
IOUT = 50 mA
TA = 25°C
VIN = 4.3 V
2.5
2.0
1.5
1.0
0.5
0.0
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 28. Output Spectral Noise Density vs.
Frequency
Figure 29. Output Spectral Noise Density vs.
Frequency
7.0
OUTPUT VOLTAGE NOISE (mV/√Hz)
5.0
COUT = 10 mF, 114.7 mVrms @ 200 Hz − 100 kHz
OUTPUT VOLTAGE NOISE (mV/√Hz)
OUTPUT VOLTAGE NOISE (mV/√Hz)
4.0
COUT = 10 mF, 186.1 mVrms @ 200 Hz − 100 kHz
6.0
COUT = 4.7 mF, 189.41 mVrms @ 200 Hz − 100 kHz
5.0
COUT = 1.0 mF, 244.5 mVrms @ 200 Hz − 100 kHz
COUT = 2.2 mF, 207.6 mVrms @ 200 Hz − 100 kHz
COUT = 0.47 mF, 305.0 mVrms @ 200 Hz − 100 kHz
4.0
NCP715x50xxx
IOUT = 50 mA
TA = 25°C
VIN = 6.0 V
3.0
2.0
1.0
0.0
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
Figure 30. Output Spectral Noise Density vs.
Frequency
Figure 31. Line Transient Response
Figure 32. Line Transient Response
Figure 33. Line Transient Response
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16
NCP715
Figure 34. Load Transient Response
Figure 35. Load Transient Response
Figure 36. Load Transient Response
Figure 37. Input Voltage Turn−On Response
Figure 38. Input Voltage Turn−On Response
Figure 39. Input Voltage Turn−On Response
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17
NCP715
APPLICATIONS INFORMATION
ambient temperature affect the rate of junction temperature
rise for the part. The maximum power dissipation the
NCP715 can handle is given by:
The NCP715 is the member of new family of Wide Input
Voltage Range Low Dropout Regulators which delivers
Ultra Low Ground Current consumption, Good Noise and
Power Supply Rejection Ratio Performance.
P D(MAX) +
Input Decoupling (CIN)
It is recommended to connect at least 0.1 mF Ceramic X5R
or X7R capacitor between IN and GND pin of the device.
This capacitor will provide a low impedance path for any
unwanted AC signals or Noise superimposed onto constant
Input Voltage. The good input capacitor will limit the
influence of input trace inductances and source resistance
during sudden load current changes.
Higher capacitance and lower ESR Capacitors will
improve the overall line transient response.
ƪTJ(MAX) * TAƫ
(eq. 1)
R qJA
The power dissipated by the NCP715 for given
application conditions can be calculated from the following
equations:
P D [ V INǒI GNDǒI OUTǓǓ ) I OUTǒV IN * V OUTǓ (eq. 2)
or
V IN(MAX) [
Output Decoupling (COUT)
P D(MAX) ) ǒV OUT
I OUT ) I GND
I OUTǓ
(eq. 3)
For reliable operation, junction temperature should be
limited to +125°C maximum.
The NCP715 does not require a minimum Equivalent
Series Resistance (ESR) for the output capacitor. The device
is designed to be stable with standard ceramics capacitors
with values of 0.47 mF or greater up to 10 mF. The X5R and
X7R types have the lowest capacitance variations over
temperature thus they are recommended.
Hints
VIN and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCP715, and
make traces as short as possible.
Power Dissipation and Heat sinking
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
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18
NCP715
ORDERING INFORMATION
Device
Nominal Output Voltage
Marking
Marking Rotation
Package
NCP715SQ12T2G
1.2 V
5A
NCP715SQ15T2G
1.5 V
5C
NCP715SQ18T2G
1.8 V
5D
NCP715SQ25T2G
2.5 V
5E
−
SC88A/SC70
(Pb−Free)
NCP715SQ30T2G
3.0 V
5F
NCP715SQ33T2G
3.3 V
5G
NCP715SQ50T2G
5.0 V
5H
NCP715MX12TBG
1.2 V
Q
NCP715MX15TBG (Note 35)
1.5 V
R
NCP715MX18TBG (Note 35)
1.8 V
T
NCP715MX25TBG (Note 35)
2.5 V
V
NCP715MX30TBG (Note 35)
3.0 V
Y
NCP715MX33TBG (Note 35)
3.3 V
2
NCP715MX50TBG (Note 35)
5.0 V
5
NCP715MX53TBG (Note 35)
5.3 V
5
+180°
NCP715SN12T1G
1.2 V
PZD
−
NCP715SN15T1G
1.5 V
PZE
−
NCP715SN18T1G
1.8 V
PZF
−
NCP715SN25T1G
2.5 V
PZG
−
NCP715SN30T1G
3.0 V
PZH
−
NCP715SN33T1G
3.3 V
PZJ
−
NCP715SN50T1G
5.0 V
PZK
−
Shipping†
3000 or 5000 /
Tape & Reel
(Note 35)
0°
XDFN6 1.5 x 1.5
(Pb−Free)
TSOP−5
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
35. Products processed after October 1, 2022 are shipped with quantity 5000 units / tape & reel.
www.onsemi.com
19
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
XDFN6 1.5x1.5, 0.5P
CASE 711AE
ISSUE B
DATE 27 AUG 2015
SCALE 4:1
D
L
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20mm FROM TERMINAL TIP.
L1
DETAIL A
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
ALTERNATE TERMINAL
CONSTRUCTIONS
E
PIN ONE
REFERENCE
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
2X
2X
0.10 C
DIM
A
A1
A3
b
D
E
e
L
L1
L2
TOP VIEW
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTIONS
A
DETAIL B
A3
0.05 C
GENERIC
MARKING DIAGRAM*
A1
0.05 C
C
SIDE VIEW
DETAIL A
e
SEATING
PLANE
1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
5X
L
3
1
MILLIMETERS
MIN
MAX
0.35
0.45
0.00
0.05
0.13 REF
0.20
0.30
1.50 BSC
1.50 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
L2
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
6
4
6X
RECOMMENDED
MOUNTING FOOTPRINT*
b
0.10 C A
BOTTOM VIEW
0.05 C
B
NOTE 3
6X
0.35
5X
0.73
1.80
0.83
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON56376E
XDFN6, 1.5 X 1.5, 0.5 P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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