NCP81038MNTWG

NCP81038 Synchronous Buck Controller with Auto Power Saving Mode and Built-In LDO • • • • • • • • • • • • • • • • • • Wide Input Voltage Range: from 5.5 V to 28 V Built−in 5 V / 60 mA LDO Built−in selectable 3.3 V or 12 V / 10 mA LDO Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz 180 Interleaved Operation Between the Two Channels in Continue−Conduction−Mode (CCM) Selected Power−Saving Mode/Forced PWM Mode Transient−Response−Enhancement (TRE) Control Input Supply Voltage Feed Forward Control Resistive or Lossless Inductor’s DCR Current Sensing Over−Temperature Protection Internal Fixed 8.5 ms Soft−Start Fixed Output Voltages 5 V and 3.3 V Power Good Outputs for Both Channels Built−in Adaptive Gate Drivers Output Discharge Operation Built−in Over−Voltage, Under−Voltage Protection Accurate Over−Current Protection Thermal Shutdown MARKING DIAGRAM 81038 ALYWG G 1 28 PIN QFN, 4x4 MN SUFFIX CASE 485AR 81038 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS 5V_LDOBYP 5V_LDOOUT 5V_LDOEN SKIP LDO2_EN LDO2_OUT VIN Features http://onsemi.com GH2 BST2 SWN2 GL2 PGND2 CSP2 CSN2 28 1 GND GH1 BST1 SWN1 GL1/FSET PGND1 CSP1 CSN1 FB2 COMP2 EN2/SS2 PG EN1/SS1 COMP1 FB1 NCP81038 is a dual synchronous buck controller that is optimized for converting the battery voltage or adaptor voltage into multiple power rails required in desktop and notebook system. NCP81038 consists of two buck switching controllers with fixed 5.0 V output on channel 2, 3.3 V on channel 1 and two on−board LDOs with three outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81038 supports high efficiency, fast transient response and provides power good signals. ON Semiconductor proprietary adaptive−ripple control enables seamless transition from CCM to DCM, where converter runs at reduced switching frequency with much higher efficiency at light load. The part operates with supply voltage ranging from 5.5 V to 28 V. NCP81038 is available in a 28−pin QFN package. (Top View) Applications • Desktop / Notebook Computers • System Power Supplies • I/O Power Supplies ORDERING INFORMATION Device Package Shipping† NCP81038MNTWG QFN−28 (Pb−Free) 4,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 10 1 Publication Order Number: NCP81038/D NCP81038 5V_LDOOUT VIN − + + − ENABLE 5V_LDOEN 5V_LDOBYP LDO VREF LDO2_OUT − + ENABLE LDO2_EN CSP1 CSN1 + − SKIP CSA BST1 COMP1 Control Logic Ramp Generator And PWM Logic Vbias VREF + E/A SS − FB1 OC & TRE Detection EN1 PG GND PG1 PG2 Vbias GH1 SW1 5V_LDOOUT UVLO, UVP, OVP, Power Good OCP, TSD and Protection GL1/ FSET PGND1 VIN Switcher 1 Shown Figure 1. Block Diagram http://onsemi.com 2 NCP81038 Table 1. PIN DESCRIPTIONS Pin No. Symbol 1, 21 GH1, GH2 Description Gate driver output of the top N−channel MOSFET. 2, 20 BST1, BST2 3, 19 SWN1, SWN2 Top gate driver input supply, a bootstrap capacitor connection between SWNx and this pin. Switch node between the top MOSFET and bottom MOSFET. 4 GL2 Gate driver output of bottom N−channel MOSFET in channel2. 18 GL1/FSET 5, 17 PGND1, PGND2 6, 16 CSP1, CSP2 Inductor current differential sense non−inverting input. 7, 15 CSN1, CSN2 Inductor current differential sense inverting input. 8, 14 FB1, FB2 Gate driver output of bottom N−channel MOSFET in channel1. And it is also used to set up switching frequency by connecting a resistor from this pin to ground. Power ground for channel 1 & 2. Output voltage feed back. 9, 13 COMP1, COMP2 10, 12 EN1, EN2 11 PG Power good indicator for both output voltages. Open−drain output. 22 VIN Battery or Adaptor input voltage 23 LDO2_OUT 24 LDO2_EN 25 SKIP 26 5V_LDOEN 27 5V_LDOOUT The output for internal 5 V LDO. A capacitor of minimum 4.7 mF is recommended to connect between this pin and ground. 28 5V_LDOBYP 5 V LDO bypass pin. E−Pad Output of the error amplifier. Channel 1 and channel 2 enable pin. Short this pin to ground to disable the switcher channel. Pull this pin high to enable the switcher channel. Second internal LDO output. A capacitor of minimum 1.0 mF is recommended to connect between this pin and ground. Enable for second internal LDO − Tie to VCC to setup LDO2 output at 12 V − Tie to 1/2VCC to setup LDO2 output at 3.3 V − Tie to ground to disable LDO DCM programming pin: − Ground this pin to setup automatic CCM−DCM transfer with 33 KHz minimum switching frequency limitation; − Connect this pin to VCC to force CCM operation; − Leave this pin open to give automatic CCM−DCM transfer with 33 KHz minimum switching frequency for channel 1 but forced CCM for channel 2. Enable for internal 5 V LDO. GND. http://onsemi.com 3 NCP81038 LDO2_OUT (3.3 V) VIN 10 K 5V_LDO 10 K 28 27 VIN LDO2_OUT SKIP 22 mFx2 26 25 24 23 22 21 20 19 AGND 18 17 GH1 BST1 0.1 mF SWN1 3.3 mH Vout1 3.3 V / 6.0 A GL1/FSET PGND1 16 CSP1 CSN1 15 EN2/SS2 FB1 EN1/SS1 COMP1 10 11 12 13 14 PG 9 COMP2 8 FB2 5V_LDOEN 5V_LDOOUT 5V_LDOBYP Vout2 5.0 V / 6.0 V GH2 BST2 1 0.1 mF 2 SWN2 3 GL2 4 PGND2 5 CSP2 6 CSN2 7 LDO2_EN EN5 SKIP VOUT1 Figure 2. Application Circuit Table 2. ABSOLUTE MAXIMUM RATINGS (Note 1) VIN to GND, 5V_LDOEN to GND −0.3 V (DC) to 28 V −1.0 V for T < 100 n SWN1, SWN2 to GND −0.6 V to 28 V, −10.0 V for T < 20 ns BST1, BST2 to GND −0.6 V to 34 V GH1, GH2 to GND −0.6 V to 34 V, −5.0 V for T < 100 ns PGND1, PGND2 −0.3 V to 0.3 V All other pin −0.3 V to 6.0 V, −1.0 V for T < 100 ns Operating Temperature Range, TA 0°C to +85°C Junction Temperature, TJ −40°C to +150°C Storage Temperature Range, TS −55°C to +150°C Pkg Power Dissipation (TA = +25°C), PD (Note 2) 2.45 W max RqJA = 51°C/W RqJ−Lead = 26°C/W RqJ−BoardTop = 3.2°C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Operation at −40°C to 0°C guaranteed by design, not production tested. 2. These data are based on JEDEC JESD51.7 highly conductive PCB multiple layer PCB (2 power and/or 2 ground planes 76 mm x 76 mm 1 oz each) connected by 20 thermal vias. 100 sq mm Cu heat spreader, 2 oz. http://onsemi.com 4 NCP81038 Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; 0°C < TA < 85°C for min/max values unless noted otherwise) Parameter Symbol Test Conditions Min Typ Max Units 28 V 5.15 V POWER SUPPLY Input Supply Voltage VIN 5.5 INTERNAL LDO OUTPUT 5V_LDOOUT Voltage VIN =12 V, I5V_LDOOUT = 60 mA 5V_LDOOUT Current VIN =12 V, EN1 = EN2 = 0 5V_LDO Switch to Bypass Threshold 4.85 5.0 100 4.7 5V_LDOOUT to 5V_IDOBYP Impedance LDOBYP = 5 V 4.95 V 1.0 W 100 200 mV LDO2_EN = VCC, VIN = 15 V, Load Current = 10 mA 11.4 12 12.6 V LDO2_EN = 1/2 VCC, VIN = 15 V, Load Current = 10 mA 3.2 3.3 3.46 V 10 15 Hysteresis LDO2_OUT Voltage mA LDO2_OUT Current mA SUPPLY CURRENT BSTx Quiescent Current BSTx Shutdown Supply Current IBST IBST_SD Vin Pin Supply Current Shutdown Current IVIN_SD VFB = 1.5 V, EN = 5.0 (No Switching), GH and GL are open 0.3 EN = 0, BST = 5 V, SWN = 0 6.0 mA mA Iload = 0 2.0 mA EN1, EN2, LDOEN, LDO2_EN = 0 5.0 mA EN1, EN2, LDOEN = 5 V, LDO2_EN = 5 V 1.15 mA EN1, EN2 = 0, LDOEN = 5 V, LDO2_EN = 2.5 V 1.57 mA EN1, EN2 = 0, LDOEN = 5 V, LDO2_EN = 0 1.11 mA OSCILLATOR Oscillator Frequency Fsw Rset = 1.8 k 270 300 330 KHz Rset = 9.1 k 340 400 460 KHz Rset = 16 k 540 600 660 KHz ±10 % Oscillator Frequency Accuracy ERROR AMPLIFIER 80 Open Loop DC Gain (Note 3) Open Loop Unity Gain Bandwidth (Note 3) F0dB,EA 10 Open Loop Phase Margin (Note 3) dB 15 MHz 60 Input Bias Current (Note 3) deg −200 200 nA −1.0 1.0 mV Input Offset Voltage (Note 3) V+ = V− = 0.8 V Slew Rate COMP pin to GND = 10 pF Maximum Output Voltage 10 mV of overdrive, ISOURCE = 2.0 mA Minimum Output Voltage 10 mV of overdrive, ISINK = 2.0 mA Output Source Current 10 mV of overdrive, Vout = 3.5 V 2.0 mA Output Sink Current 10 mV of overdrive, Vout = 1.0 V 2.0 mA 3. Guaranteed by Design 4. Parameters are for design only, not for product test. http://onsemi.com 5 2.5 V/ms 3.3 V 0.3 V NCP81038 Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; 0°C < TA < 85°C for min/max values unless noted otherwise) Parameter Symbol Test Conditions Min Typ Max Units 792 800 808 mV 0.25 %/V 5.5 V FEEDBACK VOLTAGE Reference Voltage VREF Feedback Voltage Line Regulation 5V_LDOOUT = 4.5 V ~ 5.5 V DIFFERENTIAL CURRENT SENSE AMPLIFIER CSP and CSN Common−mode Input Voltage Range Refer to AGND Current Sense Input to Output Gain (CSP)−(CSN) = 10 mV Differential Input Voltage Range −0.2 200 −60 mA/V 60 mV 45 mV 46 mV OVER CURRENT PROTECTION OCP Threshold Voltage OCP Trigger Clock Tick V(CSP)−V(CSN) @ 25°C 35 V(CSP)−V(CSN) @ 0 ~ 85°C 34 After EN, latch off after trigger # clocks 40 16 Short Circuit OCP Threshold Voltage 60 mV GATE DRIVER GH Pull−High Resistance RH_GH Source, V(BST−GH) = 0.1 2.5 W GH Pull−Low Resistance RL_GH Sink, V(GH−SWN) = 0.1 V 1.5 W GL Pull−High Resistance RH_GL Source, V(VCC−GL) = 0.1 V 2.0 W GL Pull−Low Resistance RL_GL Sink, V(GL−PGND) = 0.1 V 1.0 W Dead Time GL off to GH on 10 20 30 ns GH off to GL on 10 20 30 ns VOLTAGE MONITOR VCC Start Threshold 3.7 4.2 4.4 V VCC UVLO Hysteresis 100 200 300 mV 91.5 95 97.5 % Power Good Threshold Power Good High Delay PG in from lower PG hysteresis 5.0 % After soft start is done 500 ms 1.5 ms mA Power Good Low Delay Power Good Sink Current PG = 0.4 V 2.5 5.0 Output Overvoltage Rising Threshold After VCC POR, with respect to VFB 106 110 Overvoltage Fault Blanking Time Output Under-Voltage Trip Threshold 118 1.5 After soft start, with respect to VFB 45 50 %Vref ms 55 %Vref Under-voltage Protection Blanking Time tss ms Under−voltage Protection Delay 2.0 ms PWM Minimum Controllable ON Time 50 Minimum OFF Time 100 150 ns 0.4 0.44 V PWM Ramp Offset PWM Ramp Amplitude PWM Comparator Propagation Delay 0.36 ns VIN = 5 V 1.25 V VIN = 12 V 3.0 V 10 mV to 20 mV overdrive 25 3. Guaranteed by Design 4. Parameters are for design only, not for product test. http://onsemi.com 6 30 ns NCP81038 Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, Vout = 5.0 V, TA = +25°C for typical value; 0°C < TA < 85°C for min/max values unless noted otherwise) Parameter Symbol Test Conditions Min Typ Max Units INTERNAL BST DIODE Forward Voltage Drop IF = 10 mA, TA = 25°C 0.3 V Reverse−bias Leakage Current VBST = 34 V, VSW = 28 V, TA = 25°C 0.1 6.0 mA EN = 0, Vout = 0.5 V 20 30 W SOFT−STOP Output Discharge On−Resistance Discharge Threshold in Vcc 0.7 V SOFT−START Soft−Start Ramp Time tss From EN assertion to Vout ready 6.0 HI Threshold 1.4 12 18 ms EN EN1/EN2 Threshold V LO Threshold 5V_LDOEN Threshold 0.4 Hysteresis 200 mV Source Current, pull high to 5 V internally 0.75 mA HI Threshold 1.4 V LO Threshold 0.4 Hysteresis LDO2_EN V 200 Vout = 3.3 V 1.5 Vout = 12 V 4.95 2.5 Vout = 0 V mV 3.5 V 5.5 V 0.4 V THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 3) 150 °C Thermal Shutdown Hysteresis (Note 3) 40 °C 3. Guaranteed by Design 4. Parameters are for design only, not for product test. http://onsemi.com 7 NCP81038 DETAILED DESCRIPTION Overview temperature range of the controller. The reference voltage is trimmed using a test configuration that accounts for error amplifier offset and bias currents. The NCP81038 is a cost effective dual output controllers with three selectable LDO outputs suitable for desktop and server application. It provides one independent LDO which is 5 V/100 mA, two selectable LDOs which is 12 V or 3.3 V/10 mA, and two synchronous PWM controllers that incorporate all the control and protection circuitry necessary to satisfy a wide range of applications. The NCP81038 PWM switchers employ adaptive−ripple control to provide seamless transition between CCM and DCM while maintain high efficiency during light load. It also provides fast transient response and excellent stability. The features of the NCP81038 include a precision reference, selectable switching frequency, an error amplifier, adaptive gate driver, programmable soft−start, and very low shutdown current. The protection features of the NCP81038 include fixed/programmable soft−start, over−current protection, wide input voltage range, power good monitor, over voltage and under voltage protection, built in output discharge and thermal shutdown. Oscillator Frequency A fixed precision oscillator is provided. The actual switching frequency is set at 300 KHz, 400 KHz or 600 KHz by the resistor on GL1/FSET pin. The resistor and frequency can be referred to the table below. FSET resistor 1.8 K 9.1 K 16 K Switching Frequency 300 KHz 400 KHz 600 KHz Error Amplifier The error amplifier’s primary function is to regulate the converter’s output voltage using a resistor divider connected from the converter’s output to the FB pin of the controller, as shown in the Applications Schematic. A type III compensation network must be connected around the error amplifier to stabilize the converter. It has a bandwidth of greater than 15 MHz, with open loop gain of at least 80 dB. The COMP output voltage is clamped to a level above the oscillator ramp in order to improve large−scale transient response. 5V LDO and Switchover (5V_LDOOUT) The NCP81038 includes a high−current (100 mA) linear regulator that is configured for 5 V operation, which is bias supply necessary to power up the main analog supply rail for the IC and provides the current for the gate drivers. When the 3.3 V switching regulator is running and the 5 V switching regulator is still off (EN2 = 0), the 5 V linear regulator can provide about 80 mA to external load, while the remaining 20 mA is consumed by the 3.3 V regulator’s MOSFETS’ switching, giving typical switching frequency and MOSFETS’ gate capaciatance. Once the 5 V switching regulator is enabled, this 5V_LDO may be bypassed using 5V_LDOBYP input. Typically, a capacitor with 10−mF or higher is needed to keep 5V_LDO stable. Additionally, if VOUT2 voltage exceeds 4.75 V, the 5V_LDO is switched off and VOUT2 (5V buck output) is connected to 5V_LDOOUT through a bypass FET (typical 1 ohm) to provide 5 V rail. With this bypass function, the whole system efficiency is improving. The 5V_LDOEN pin is high voltage and can be connected to VIN voltage. However, 5V_LDOEN is not allowed to go beyond VIN pin voltage. Soft−Start To limit the start−up inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. The internal soft start time is 13 ms typically, from EN assertion to Vout ready. It includes a delay of 240 ms from EN assertion to the Vout ramp starting. 500 ms after both channel Vout ready, the PG (Power Good) is asserted. Soft−Stop Soft−Stop or discharge mode is always on during faults or disable. In this mode, a fault (UVP, OCP, TSD) or disable (EN) causes the output to be discharged through an internal 20−ohm transistor inside of VO terminal. The time constant of soft−stop is a function of output capacitance and the resistance of the discharge transistor. Adaptive Non−Overlap Gate Driver In a synchronous buck converter, a certain dead time is required between the low side drive signal and high side drive signal to avoid shoot through. During the dead time, the body diode of the low side FET free-wheels the current. The body diode has much higher voltage drop than that of the MOSFET, which reduces the efficiency significantly. The longer the body diode conducts, the lower the efficiency. NCP81038 implements adaptive dead time control to minimize the dead time, as well as preventing shoot through from happening. LDO2_OUT The NCP81038 includes 10 mA linear regulators that can be programmed for 12 V or 3.3 V operations. LDO2 can be enabled only when VCC is present. When LDO2_EN is connected to VCC, LDO2_OUT is programmed at 12 V. When LDO2_EN is connected to 1/2VCC, LDO2_OUT is set at 3.3 V. Typically, a minimum capacitor with 1.0−mF or higher is needed to keep LDO2_OUT stable. Reference Voltage The NCP81038 incorporates an internal reference that allows output voltages as low as 0.8 V. The tolerance of the internal reference is guaranteed over the entire operating http://onsemi.com 8 NCP81038 Forced Pulse Width Modulation (FPWM Mode) Over Voltage Protection (OVP) The device is operating as force PWM mode if SKIP is tied to VCC. Under this mode, the low−side gate driver signal is forced to be the complement of the high−side gate driver signal. This mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and better (fast) transient response. During the soft start operation, the NCP81038 automatically runs as FPWM mode regardless of the SKIP setting at either FPWM or SKIP mode to make sure to have smooth power up. When VFB voltage is above 110% (typical) of the nominal VFB voltage, the top gate drive is turned off and the bottom gate drive is turned on trying to discharge the output. It over voltage condition still exists after 1.5 ms, an OV fault is set. The power good will go low at the same time. The bottom gate drive will be turned off when VFB drops below the under voltage threshold. If then over voltage condition happens again, the high side MOSFET stays off and low side MOSFET will turn on again till output voltage drops down to under voltage threshold. Then low side gate will be off. EN resets or power recycle the device can exit the fault. Power Save Mode (Skip Mode) If the load current decreases, the converter will enter power save mode operation when SKIP pin is grounded. During power save mode, the converter skips switching and operates with reduced frequency but with minimum switching frequency of 33 KHz, which minimizes the quiescent current and maintains high efficiency. If SKIP pin is open, the channel 1 will enter power saving mode with reduced load but with minimum switching frequency of 33 KHz and channel 2 will stay in forced PWM mode. Under Voltage Protection (UVP) An UVP circuit monitors the VFB voltage to detect under voltage event. The under voltage limit is 50% (typical) of the nominal VFB voltage. If the VFB voltage is below this threshold over 1 ms, an UV fault is set and the device is latched off such that both top and bottom gate drives are off. EN resets or power recycle the device can exit the fault. UVP is delayed for soft start period (8.5 ms) after EN goes high. Transient Response Enhancement (TRE) EN1 and EN2 For a conventional trailing−edge PWM controller in CCM, the minimum response delay time is one switching period in the worst case. To further improve transient response, a transient response enhancement circuitry is introduced to the NCP81038. The controller continuously monitors the COMP signal, which is the output voltage of the error amplifier, to detect load transient events. A desired stable close−loop system with the NCP81038 has a ripple voltage in the COMP signal, which peak−to−peak value is normally in a range from 200 mV to 500 mV. There is a threshold voltage made in a way that a filtered COMP signal pluses an offset voltage. Once a large load transient occurs, the COMP signal is possible to exceed the threshold and then TRE is tripped in a short period, which is typically around one normal switching cycle. In this short period, the controller runs at higher frequency and therefore has faster response. After that the controller comes back to normal operation. EN1 and EN2 are logic level control signals to turn on or off buck converters individually. If ENx is below 0.4 V, the buck will be off. When ENx is above 1.8 V, the buck is turning on. In both ENx pins, there are about 0.75 mA source currents to pull them up to 5 V internally. Power Good Monitor (PG) NCP81038 provides window comparator to monitor the output voltage. When the output voltage is above 95% of regulation voltage, the power good pin outputs a high signal. Otherwise, PG stays low. The PG pin is open drain 5−mA pull down output. During startup, PG stays low until the feedback voltage is within the specified range for 128 clocks or about 0.5 ms. If feedback voltage falls outside the tolerance band, the PG pin goes low within microseconds. Over Current Protection (OCP) The NCP81038 protects converter if over−current occurs. The current through each channel is continuously monitored with differential current sense. Current limit threshold Vth_OC between CS+ and CS− is internally fixed to 40 mV. The current limit can be programmed by inductor’s DCR and current sensing resistor divider with Rs1 and Rs2. PROTECTIONS Under Voltage Lockout (UVLO) There are two undervoltage lock out protections (UVLO) in NCP81038. One is for VIN, which has a typical trip threshold voltage 3.9 V and trip hysteresis 200 mV. The other is for VCC (5V_LDOOUT serves as VCC internally), which has a typical trip threshold voltage 4.2 V and trip hysteresis 300 mV. If either is triggered, the device resets and waits for the voltage to rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger the fault counter to latch off the part. http://onsemi.com 9 NCP81038 L DCR Vin I LIM + I LIM(Peak) * Vout C Rs1 where Vin is the input supply voltage of the power stage, and fsw is normal switching frequency. Fig. X+1 shows NTC resistor network to compensate the temperature drift of DCR. If inductor current exceeds the current threshold, the high−side gate driver will be turned off cycle−by−cycle. In the mean time, an internal OC fault timer will be triggered. If the fault still exists after 16 clocks, the part latches off, both the high−side MOSFET and the low−side MOSFET are turned off. If the sensed current reaches 60 mV, the part will latch off right away. The fault remains set until the system has shutdown and re−applied VCC and/or the enable signal EN is toggled. Rs2 Vc + − Figure 3. X L DCR Vin Vout C R V O @ (V in * V O) 2 @ V in @ f SW @ L Pre−Bias Startup R2 R1 RNTC RTHE Vc + In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP81038 supports pre−bias start up by holding Low side FETs off till soft start ramp reaches the FB pin voltage. − Figure 4. X + 1 The Rs1, Rs2 and C can be calculated as: C @ ǒR S1ńńR S2Ǔ + L DCR Thermal Shutdown The NCP81038 protects itself from over heating with an internal thermal monitoring circuit. If the junction temperature exceeds the thermal shutdown threshold the voltage at the COMP pin will be pulled to GND and both the upper and lower MOSFETs will be shut OFF. The inductor peak current limit is: I LIM(Peak) + V th_DC k @ DCR , where k + R S2 R S1 ) R S2 The DC current limit is: http://onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN28 4x4, 0.4P CASE 485AR−01 ISSUE A DATE 20 NOV 2009 1 SCALE 2:1 PIN ONE REFERENCE B A D ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ L L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 ÏÏ ÏÏ EXPOSED Cu 0.10 C 0.10 C L MOLD CMPD DETAIL B TOP VIEW ALTERNATE CONSTRUCTION A DETAIL B A3 0.10 C GENERIC MARKING DIAGRAM* 0.08 C NOTE 4 A1 SIDE VIEW SEATING PLANE C XXXXXX XXXXXX ALYWG G 0.10 C A B D2 DETAIL A K 8 0.10 C A B 15 28X L E2 1 PIN 1 INDICATOR 22 e 28X BOTTOM VIEW b 0.07 C A B 0.05 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.15 0.25 4.00 BSC 2.50 2.70 4.00 BSC 2.50 2.70 0.40 BSC 0.30 REF 0.30 0.50 −−− 0.15 XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. RECOMMENDED MOUNTING FOOTPRINT NOTE 3 4.30 2.71 28X 0.62 1 2.71 4.30 PACKAGE OUTLINE 0.40 PITCH DOCUMENT NUMBER: 98AON30349E 28X 0.26 DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 Case Outline Number: http://onsemi.com QFN28 4X4, 0.4P DESCRIPTION: October, 2002 − Rev. 0 PAGE 1 OFXXX 2 1 DOCUMENT NUMBER: 98AON30349E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY M. LIN. 15 MAY 2008 A CHANGED DIMENSIONS D2, E2, K, L, MOUNTING FOOTPRINT AND MARKING DIAGRAM INFORMATION. REQ. BY J. LIU. 20 NOV 2009 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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