DATA SHEET
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Operational Amplifiers,
High Slew Rate, Low
Voltage, Rail-to-Rail Output
Features
Unity Gain Bandwidth: 7 MHz at VS = 5 V
Fast Slew Rate: 8 V/ms rising, 12.5 V/ms falling at VS = 5 V
Rail−to−Rail Output
No Output Phase Reversal for Over−Driven Input Signals
Low Offset Voltage: 0.5 mV typical
Low Input Bias Current: 1 pA typical
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ANxYWG
G
1
SOT553, 5 LEAD
CASE 463B
(NCS2003)
8
2K32
AYWG
G
Micro8
DM SUFFIX
CASE 846A
1
8
8
1
SOIC−8
CASE 751
1
20032
ALYWX
G
K32
YWW
AG
G
TSSOP−8
T SUFFIX
CASE 948S
14
NCS20034G
AWLYWW
14
1
SOIC−14 NB
CASE 751A
1
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
Applications
•
•
•
•
1
A3M
The NCS2003 family of op amps features high slew rate, low
voltage operation with rail−to−rail output drive capability. The 1.8 V
operation allows high performance operation in low voltage, low
power applications. The fast slew rate and wide unity−gain bandwidth
(5 MHz at 1.8 V) make these op amps suited for high speed
applications. The low input offset voltage (4 mV max) allows the op
amp to be used for current shunt monitoring. Additional features
include no output phase reversal with overdriven inputs and ultra low
input bias current of 1 pA.
The NCS2003 family is the ideal solution for a wide range of
applications and products. The single channel NCS2003, dual channel
NCS20032, and quad channel NCS20034 are available in a variety of
compact and space−saving packages. The NCV prefix denotes that the
device is AEC−Q100 Qualified and PPAP Capable.
•
5
5
SOT23−5
CASE 483
(NCS/NCV2003)
NCS2003/A, NCV2003,
NCS20032, NCV20032,
NCS20034, NCV20034
•
•
•
•
•
•
•
MARKING
DIAGRAMS
Current Shunt Monitor
Signal Conditioning
Active Filter
Sensor Buffer
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 2 of this data sheet.
End Products
•
•
•
•
Motor Control Drives
Hard Drives
Medical Devices
White Goods and Air Conditioners
© Semiconductor Components Industries, LLC, 2016
June, 2022 − Rev. 12
1
Publication Order Number:
NCS2003/D
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
Single Channel Configuration
NCS2003/A, NCV2003
OUT
1
VSS
2
5
IN+
1
VSS
2
VDD
5
VDD
4
OUT
3
IN+
−
−
+
+
4
IN−
IN−
3
SOT23−5
(TSOP−5)
SOT553−5
Quadruple Channel Configuration
NCS20034, NCV20034
Dual Channel Configuration
NCS20032, NCV20032
OUT 1
1
IN− 1
2
−
IN+ 1
3
+
VSS
4
OUT 1 1
14 OUT 4
8
VDD
IN− 1 2
−
− 13 IN− 4
7
OUT 2
IN+ 1 3
+
+ 12 IN+ 4
−
6
IN− 2
+
5
IN+ 2
VDD 4
11 VSS
IN+ 2 5
+
+ 10 IN+ 3
IN− 2 6
−
−
OUT 2 7
9 IN− 3
8 OUT 3
Figure 1. Pin Connections
ORDERING INFORMATION
Configuration
Automotive
Marking
Package
Shipping†
Single
No
AN3
SOT23−5
(Pb−Free)
3000 / Tape and Reel
NCS2003ASN2T1G
No
AN4
SOT23−5
(Pb−Free)
3000 / Tape and Reel
NCS2003XV53T2G
No
A3
SOT553−5
(Pb−Free)
4000 /Tape and Reel
NCV2003SN2T1G*
Yes
AN3
SOT23−5
(Pb−Free)
3000 / Tape and Reel
No
2K32
Micro8
(Pb−Free)
4000 / Tape and Reel
20032
SOIC−8
(Pb−Free)
2500 / Tape and Reel
K32
TSSOP−8
(Pb−Free)
3000 / Tape and Reel
2K32
Micro8
(Pb−Free)
4000 / Tape and Reel
20032
SOIC−8
(Pb−Free)
2500 / Tape and Reel
K32
TSSOP−8
(Pb−Free)
3000 / Tape and Reel
No
NCS20034G
SOIC−14
(Pb−Free)
2500 / Tape and Reel
Yes
NCS20034G
SOIC−14
(Pb−Free)
2500 / Tape and Reel
Device
NCS2003SN2T1G
NCS20032DMR2G
Dual
NCS20032DR2G
NCS20032DTBR2G
Yes
NCV20032DMR2G*
NCV20032DR2G*
NCV20032DTBR2G*
NCS20034DR2G
NCV20034DR2G*
Quad
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and
PPAP Capable.
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2
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated
Parameter
Symbol
Limit
Unit
VS
7.0
V
Input Voltage (Note 1)
VIN
VSS − 0.3 to 7.0
V
Input Current
IIN
10
mA
Output Short Current (Note 2)
IO
100
mA
Storage Temperature
TSTG
−65 to 150
°C
Junction Temperature
TJ
150
°C
Supply Voltage (VDD − VSS)
INPUT AND OUTPUT PINS
TEMPERATURE
ESD RATINGS (Note 3)
Human Body Model
NCx2003, A
NCx20032
NCx20034
HBM
3000
2000
3000
V
Machine Model
NCx2003, A
NCx20032
NCx20034
MM
200
100
150
V
Charged Device Model
NCx2003, A
NCx2003x
CDM
1000
2000
V
MSL
Level 1
ILU
100
OTHER PARAMETERS
Moisture Sensitivity Level (Note 5)
Latch−up Current (Note 4)
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Neither input should exceed the range of VSS − 300 mV to 7.0 V. This device contains internal protection diodes between the input pins and
VDD. When VIN exceeds VDD, the input current should be limited to the specified value.
2. Indefinite duration; however, maximum package power dissipation limits must be observed to ensure that the maximum junction temperature
is not exceeded.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 and JESD22−A114
ESD Machine Model tested per AEC−Q100−003 and JESD22−A115
ESD Charged Device Model tested per AEC−Q100−011 and ANSI/ESD S5.3.1−2009
4. Latch−up current tested per JEDEC Standard JESD78.
5. Moisture Sensitivity Level tested per IPC/JEDEC standard J−STD−020A.
THERMAL INFORMATION
Thermal Metric
Junction to Ambient
Thermal Resistance
Package
Single Layer Board (Note 6)
Multi Layer Board (Note 7)
SOT23−5/TSOP−5
408
355
Symbol
qJA
SOT553−5
428
406
Micro8/MSOP8
235
163
SOIC−8
240
179
TSSOP−8
300
238
SOIC−14
167
123
Unit
°C/W
6. Values based on a 1S standard PCB according to JEDEC51−3 with 1.0 oz copper and a 300 mm2 copper area
7. Values based on a 1S2P standard PCB according to JEDEC51−7 with 1.0 oz copper and a 100 mm2 copper area
RECOMMENDED OPERATING CONDITIONS
Parameter
Operating Supply Voltage (VDD − VSS)
Specified Operating Range
NCS2003, A
NCV2003, NCx20032, NCx20034
Input Common Mode Range
Symbol
Min
Max
Unit
VS
1.7
5.5
V
TA
−40
−40
+85
+125
°C
VCM
VSS
VDD−0.6
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
ELECTRICAL CHARACTERISTICS: VS = +1.8 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the
specified temperature range. Guaranteed by design and/or characterization.
Parameter
Symbol
Conditions
VOS
Min
Typ
Max
Unit
NCS2003A
0.5
3.0
mV
NCx2003, NCx20032, NCx20034
0.5
4.0
mV
5.0
mV
INPUT CHARACTERISTICS
Input Offset Voltage
Offset Voltage Drift
DVOS/DT
Input Bias Current
IIB
1
pA
Input Offset Current
IOS
1
pA
Channel Separation
XTLK
100
dB
2.0
NCS2003A (Note 8)
mV/°C
6.0
DC, NCx20032, NCx20034
mV/°C
Input Resistance
RIN
1
TW
Input Capacitance
CIN
1.2
pF
80
dB
92
dB
Common Mode Rejection
Ratio
CMRR
VIN = VSS to VDD – 0.6 V
70
VIN = VSS + 0.2 V to VDD – 0.6 V
65
RL = 10 kW
80
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
AVOL
75
RL = 2 kW
92
70
Output Current Capability
(Note 8)
ISC
Output Voltage High
VOH
Output Voltage Low
VOL
Sourcing
5
8
Sinking
10
14
RL = 10 kW
1.75
1.798
RL = 2 kW
1.7
1.78
RL = 10 kW
mA
V
NCx2003, A
7
50
NCx2003x
7
100
RL = 2 kW
20
100
mV
NOISE PERFORMANCE
Voltage Noise Density
eN
f = 1 kHz
20
nV/√Hz
Current Noise Density
iN
f = 1 kHz
0.1
pA√Hz
5
MHz
DYNAMIC PERORMANCE
Gain Bandwidth Product
GBWP
Slew Rate at Unity Gain
SR
Phase Margin
ym
Gain Margin
Am
Settling Time
tS
Rising Edge, RL = 2 kW, AV = +1
6
Falling Edge, RL = 2 kW, AV = +1
9
RL = 10 kW, CL = 5 pF
53
°
NCx2003, A
12
dB
NCx2003x
8
Settling time to
0.1%
1.8
RL = 10 kW, CL = 5 pF
VO = 1 Vpp,
Gain = 1, CL = 20 pF
V/ms
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design and/or characterization.
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4
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
ELECTRICAL CHARACTERISTICS: VS = +1.8 V (continued)
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the
specified temperature range. Guaranteed by design and/or characterization.
Parameter
Symbol
Conditions
Min
Typ
THD+N
VO = 1 Vpp, RL = 2 kW, AV = +1, f = 1 kHz
0.005
VO = 1 Vpp, RL = 2 kW, AV = +1, f = 10 kHz
0.025
Max
Unit
DYNAMIC PERORMANCE
Total Harmonics Distortion +
Noise
%
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
NCx2003
72
dB
80
65
NCx20032, NCx20034
Quiescent Current
IDD
No load, per channel
100
80
NCx2003, A
230
560
mA
1000
NCx20032,
NCx20034
275
375
575
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design and/or characterization.
ELECTRICAL CHARACTERISTICS: VS = +5.0 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the
specified temperature range. Guaranteed by design and/or characterization.
Parameter
Symbol
Conditions
VOS
Min
Typ
Max
Unit
NCS2003A
0.5
3.0
mV
NCx2003
0.5
4.0
mV
5.0
mV
INPUT CHARACTERISTICS
Input Offset Voltage
NCx20032, NCx20034
Offset Voltage Drift
DVOS/DT
2.0
NCS2003A (Note 9)
Input Bias Current
IIB
Input Offset Current
IOS
Channel Separation
XTLK
DC, NCx20032, NCx20034
mV/°C
6.0
mV/°C
1
pA
1
pA
100
dB
Input Resistance
RIN
1
TW
Input Capacitance
CIN
1.2
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Guaranteed by design and/or characterization.
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5
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
ELECTRICAL CHARACTERISTICS: VS = +5.0 V (continued)
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the
specified temperature range. Guaranteed by design and/or characterization.
Parameter
Symbol
Conditions
Min
Typ
VIN = VSS to VDD –
0.6 V
65
90
VIN = VSS + 0.2 V
to VDD – 0.6 V
63
NCx20032, NCx20034 VIN = VSS to VDD –
0.6 V
70
VIN = VSS + 0.2 V
to VDD – 0.6 V
65
Max
Unit
INPUT CHARACTERISTICS
Common Mode Rejection Ratio
CMRR
NCx2003, A
dB
90
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain
AVOL
RL = 10 kW
86
dB
92
78
RL = 2 kW
83
92
78
Output Current Capability
(Note 9)
ISC
Output Voltage High
VOH
Output Voltage Low
VOL
Sourcing
40
76
Sinking
50
96
RL = 10 kW
4.95
4.99
RL = 2 kW
4.9
4.97
RL = 10 kW
NCx2003, A
NCx2003x
mA
V
8
50
8
100
RL = 2 kW
24
100
mV
NOISE PERFORMANCE
Voltage Noise Density
eN
f = 1 kHz
20
nV/√Hz
Current Noise Density
iN
f = 1 kHz
0.1
pA√Hz
DYNAMIC PERORMANCE
Gain Bandwidth Product
GBWP
Slew Rate at Unity Gain
SR
Phase Margin
ym
Gain Margin
Am
Settling Time
tS
Total Harmonics Distortion +
Noise
THD+N
7
MHz
Rising Edge, RL = 2 kW, AV = +1
8
V/ms
Falling Edge, RL = 2 kW, AV = +1
12.5
RL = 10 kW, CL = 5 pF
NCx2003, A
64
NCx2003x
56
°
9
dB
0.6
ms
VO = 4 Vpp, RL = 2 kW, AV = +1, f = 1 kHz
0.002
%
VO = 4 Vpp, RL = 2 kW, AV = +1, f = 10 kHz
0.01
RL = 10 kW, CL = 5 pF
VO = 1 Vpp,
Gain = 1, CL = 20 pF
Settling time to
0.1%
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Guaranteed by design and/or characterization.
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6
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
ELECTRICAL CHARACTERISTICS: VS = +5.0 V (continued)
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. Boldface limits apply over the
specified temperature range. Guaranteed by design and/or characterization.
Parameter
Symbol
Conditions
Min
Typ
PSRR
NCx2003, A
72
80
Max
Unit
POWER SUPPLY
Power Supply Rejection Ratio
dB
65
NCx20032, NCx20034
Quiescent Current
IDD
No load, per channel
80
100
NCx2003, A
300
NCx20032,
NCx20034
325
660
mA
1000
450
675
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Guaranteed by design and/or characterization.
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NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
TYPICAL CHARACTERISTICS
600
700
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
600
+85°C
500
+125°C
400
+25°C
300
−40°C
200
100
500
400
300
VS = 1.8 V
200
100
No Load
No Load
0
1
3
2
4
0
−50
5
−25
0
SUPPLY VOLTAGE (V)
18
16
14
12
10
+85°C
+25°C
6
+125°C
4
2
0
0
1
2
3
4
1.4
1.2
+125°C
1
0.8
+85°C
0.6
−40°C
0.4
+25°C
0.2
VS = 1.8 V
0
5
0
VCM, COMMON MODE VOLTAGE (V)
0.5
HIGH LEVEL OUTPUT VOLTAGE (V)
+125°C
−40°C
+25°C
0
5
10
15
1.8
0.2
0
10
20
LOW LEVEL OUTPUT CURRENT (mA)
0.4
0.1
5
Figure 5. Low Level Output Voltage vs. Output
Current @ VS = 1.8 V
VS = 5 V
+85°C
125
1.6
Figure 4. Input Offset Current vs. VCM
0.3
100
1.8
VS = 5 V
−40°C
75
Figure 3. Quiescent Supply Current vs.
Temperature
LOW LEVEL OUTPUT VOLTAGE (V)
INPUT OFFSET CURRENT (pA)
20
8
50
25
TEMPERATURE (°C)
Figure 2. Quiescent Supply Current vs. Supply
Voltage
LOW LEVEL OUTPUT VOLTAGE (V)
VS = 5 V
VS = 2.7 V
15
20
−40°C
1.6
VS = 1.8 V
1.4
1.2
+25°C
1
+85°C
0.8
0.6
0.4
+125°C
0.2
0
0
−2
−4
−6
−8
−10
LOW LEVEL OUTPUT CURRENT (mA)
HIGH LEVEL OUTPUT CURRENT (mA)
Figure 6. Low Level Output Voltage vs. Output
Current @ VS = 5 V
Figure 7. High Level Output Voltage vs. Output
Current @ VS = 1.8 V
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NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
TYPICAL CHARACTERISTICS (Continued)
140
VS = 5 V
−40°C
4.9
100
+25°C
4.8
+85°C
4.7
60
+125°C
40
20
4.5
0
−4
−8
−12
−16
100
RL = 10 kW
TA = 25°C
80
100
1k
10k
100k
1M
−20
10
VS = 1.8 V
CL = 5 pF
TA = 25°C
100
60
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Open Loop Gain and Phase vs.
Frequency @ VS = 1.8 V
300
180
20
120
VS = 5 V
CL = 5 pF
TA = 25°C
100
60
1k
10k
100k
1M
10M
VS = 1.8 V
RL = 10 kW
TA = 25°C
70
240
Phase
0
100M
80
360
PHASE MARGIN (°)
Gain
240
120
Figure 10. CMRR vs. Frequency
Gain − 2 kW
Gain − 10 kW
Phase − 2 kW
Phase − 10 kW
300
PHASE (°)
AVOL (dB)
0
VS = 1.8 V
VS = 5 V
360
180
Phase
20
PHASE (°)
AVOL (dB)
Gain
40
1M
Gain − 10 kW
Gain − 2 kW
Phase − 10 kW
Phase − 2 kW
60
60
−20
10
100k
Figure 9. PSRR vs. Frequency
100
0
10k
Figure 8. High Level Output Voltage vs. Output
Current @ VS = 5 V
40
40
1k
FREQUENCY (Hz)
60
80
100
HIGH LEVEL OUTPUT CURRENT (mA)
80
0
10
VS = 1.8 V
VS = 5 V
0
10
−20
100
CMRR (dB)
80
4.6
20
RL = 10 kW
TA = 25°C
120
PSRR (dB)
HIGH LEVEL OUTPUT VOLTAGE (V)
5
60
50
40
30
20
10
0
0
100M
0
FREQUENCY (Hz)
50
100
150
200
CAPACITIVE LOAD (pF)
Figure 12. Open Loop Gain and Phase vs.
Frequency @ VS = 5 V
Figure 13. Phase Margin vs. Capacitive Load
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9
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
TYPICAL CHARACTERISTICS (Continued)
120
VOLTAGE (mV)
100
VS = 1.8 V
RL = 2 kW
TA = 25°C
120
100
80
60
40
60
40
20
0
0
1800
1600
1400
0
20
40
−20
−20
60
60
Figure 15. Non−Inverting Small Signal
Transient Response
VS = 1.8 V
RL = 2 kW
TA = 25°C
1800
Output
Input
1600
1400
VOLTAGE (mV)
600
400
1000
800
600
400
200
0
0
0
20
40
−200
−20
60
Output
Input
VS = 1.8 V
RL = 2 kW
TA = 25°C
1200
200
−200
−20
0
20
40
60
TIME (ms)
TIME (ms)
Figure 16. Inverting Large Signal Transient
Response
Figure 17. Non−Inverting Large Signal
Transient Response
100
VS = 5 V
RL = 2 kW
TA = 25°C
Output
Input
10
4
1
THD+N (%)
VOLTAGE (V)
40
Figure 14. Inverting Small Signal Transient
Response
800
3
2
1
RL = 2 kW
AV = +1
TA = 25°C
f = 1 kHz
0.1
VS = 1.8 V
0.01
0.001
0
−1
−20
20
TIME (ms)
1000
5
0
TIME (ms)
1200
6
Output
Input
VS = 1.8 V
RL = 2 kW
TA = 25°C
80
20
−20
−20
VOLTAGE (mV)
140
Output
Input
VOLTAGE (mV)
140
VS = 5 V
0
20
40
0.0001
0.01
60
0.1
1
TIME (ms)
OUTPUT VOLTAGE (Vpp)
Figure 18. Non−Inverting Large Signal
Transient Response
Figure 19. THD+N vs. Output Voltage
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10
10
NCS2003/A, NCV2003, NCS20032, NCV20032, NCS20034, NCV20034
TYPICAL CHARACTERISTICS (Continued)
1
VS = 1.8 V
0.01
VS = 5 V
0.001
0.0001
10
100
10
1k
10k
80
60
40
20
100
1k
10k
100k
Figure 21. Input Voltage Noise vs. Frequency
40
35
0.001
0.0001
30
25
20
15
10
5
TA = 25°C
100
1k
10k
0
100k
11
12
13
14
FREQUENCY (Hz)
FALLING EDGE SLEW RATE (V/ms)
Figure 22. Noise Density vs. Frequency
Figure 23. Falling Edge Slew Rate @ Vs = 5 V
45
CHANNEL SEPARATION (dB)
VS = 5 V
TA = 25°C
40
NUMBER OF PARTS
TA = 25°C
Figure 20. THD+N vs. Frequency
0.01
35
30
25
20
15
10
0
−10
−20
Vs = 1.8 V
Vs = 5 V
−30
−40
TA = 25°C
−50
−60
−70
−80
−90
−100
5
0
100
FREQUENCY (Hz)
0.1
0.00001
10
VS = 1.8 V
VIN = VS/2
FREQUENCY (Hz)
VS = 1.8 V
VIN = VS/2
1
120
0
10
100k
NUMBER OF PARTS
CURRENT NOISE DENSITY (pA/√Hz)
VOLTAGE NOISE (nV/√Hz)
0.1
THD+N (%)
140
RL = 2 kW
AV = +1
TA = 25°C
f = 1 kHz
7
8
−110
−120
9
10
100
1K
10K
100K
RISING EDGE SLEW RATE (V/ms)
FREQUENCY (Hz)
Figure 24. Rising Edge Slew Rate @ Vs = 5 V
Figure 25. Channel Separation
www.onsemi.com
11
1M
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−553, 5 LEAD
CASE 463B
ISSUE C
SCALE 4:1
D
−X−
5
A
4
1
2
3
b
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
L
E
−Y−
DATE 20 MAR 2013
HE
DIM
A
b
c
D
E
e
L
HE
c
5 PL
0.08 (0.003)
M
X Y
RECOMMENDED
SOLDERING FOOTPRINT*
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.004
0.008
0.061
0.063
MIN
0.020
0.007
0.003
0.061
0.045
MAX
0.024
0.011
0.007
0.065
0.049
0.012
0.065
GENERIC
MARKING DIAGRAM*
0.3
0.0118
XXMG
G
0.45
0.0177
XX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
1.0
0.0394
1.35
0.0531
MILLIMETERS
NOM
MAX
0.55
0.60
0.22
0.27
0.13
0.18
1.60
1.65
1.20
1.25
0.50 BSC
0.10
0.20
0.30
1.55
1.60
1.65
MIN
0.50
0.17
0.08
1.55
1.15
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR 1
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
STATUS:
98AON11127D
ON SEMICONDUCTOR STANDARD
1
© Semiconductor Components Industries, LLC, 2002
January, 2002 − Rev. 01O
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
SOT−553, 5 LEAD
http://onsemi.com
1
STYLE 5:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled exceptCase
when
stamped
Outline
Number:
463B
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON11127D
PAGE 2 OF 2
ISSUE
REVISION
DATE
A
ADDED STYLES 3−9. REQ. BY D. BARLOW
11 NOV 2003
B
ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO
27 MAY 2005
C
UPDATED DIMENSIONS D, E, AND HE. REQ. BY J. LETTERMAN.
20 MAR 2013
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. C
Case Outline Number:
463B
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro8
CASE 846A−02
ISSUE K
DATE 16 JUL 2020
SCALE 2:1
GENERIC
MARKING DIAGRAM*
8
XXXX
AYWG
G
1
XXXX
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB14087C
MICRO8
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
STYLE 3:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
N-SOURCE
N-GATE
P-SOURCE
P-GATE
P-DRAIN
P-DRAIN
N-DRAIN
N-DRAIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE C
DATE 20 JUN 2008
SCALE 2:1
K REF
8x
0.20 (0.008) T U
0.10 (0.004)
S
2X
L/2
8
0.20 (0.008) T U
T U
B
−U−
1
J J1
4
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
K1
K
A
−V−
S
S
5
L
PIN 1
IDENT
M
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
DETAIL E
G
PLANE
0.25 (0.010)
N
M
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
N
F
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
G
DETAIL E
XXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
STATUS:
98AON00697D
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
TSSOP−8
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON00697D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION.
18 APR 2000
A
ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS.
13 JAN 2006
B
CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C.
REBELLO.
13 MAR 2006
C
REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED
MARKING INFORMATION. REQ. BY C. REBELLO.
20 JUN 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
June, 2008 − Rev. 01C
Case Outline Number:
948S
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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