NCS2300MUTAG

NCS2300 Headset Detection Interface The NCS2300 is a compact and cost effective headset detection interface IC. It integrates a comparator, OR gate, and N−channel MOSFET to detect the presence of a stereo headset with a microphone. Pull−up resistors for the detection pins are internalized. A built in resistor divider provides the reference voltage for detecting the left audio channel. The logic low output of the OR gate indicates the headset has been connected properly. The NCS2300 comes in a space saving UDFN6 package (1.2 x 1.0 mm). http://onsemi.com MARKING DIAGRAM Features • Supply Voltage: 1.6 V to 2.75 V • Low Quiescent Supply Current: 7.5 mA typical @ VDD = 1.8 V • Integrated Resistors, Comparator, OR Gate, and N−Channel MOSFET 1 A M G Typical Applications • Cell Phones, Smartphones • Tablets • Notebooks M G = Specific Device Code = Date Code = Pb−Free Package • Space Saving UDFN6 Package • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant A UDFN6 MU SUFFIX CASE 517AA PIN DIAGRAM GND 1 6 OUT MIC 2 5 VDD GND_detect 3 4 L_detect Top View ORDERING INFORMATION Device NCS2300MUTAG Package Shipping† UDFN6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 5 1 Publication Order Number: NCS2300/D NCS2300 to baseband GPIO MIC bias voltage 1 GND 2 MIC 3 GND_detect NCS2300 OUT 6 VDD 5 L_detect 4 VDD 2.2k M G R L MIC GND_detect L_detect L R GND L/R to audio codec Figure 1. Typical Application Schematic NCS2300 VDD VDD 2 MIC 6 OUT 1 GND VDD 270k Reference voltage accurate within 5% − 1M + VDD VDD 1M 1M VDD 4 3 5 L_detect GND_detect VDD Figure 2. Block Diagram http://onsemi.com 2 NCS2300 Table 1. OUTPUT LOGIC Inputs Outputs L_detect GND_detect OUT MIC Headset 0 0 0 1 (external pull−up) Detected 0 1 1 0 1 0 1 0 1 1 1 0 Not Detected Table 2. PIN DESCRIPTION Pin Name Type Description 1 GND Power GND is connected to the system ground. 2 MIC Output The open drain MIC output controls the bias on the MIC line. When the headset is not present, MIC is pulled low. When the headset is present, MIC is pulled up to the MIC bias voltage through an external pull−up resistor. 3 GND_detect Input GND_detect is the OR gate input. An internal 1 MW pull−up resistor pulls this pin high when the headset is not present. 4 L_detect Input L_detect is the comparator input. An internal 1 MW pull−up resistor pulls this pin high when the headset is not present. 5 VDD Power VDD is connected to the system power supply. A 0.1 mF decoupling capacitor is recommended as close as possible to this pin. 6 OUT Output OUT is a logic output that indicates whether the headset has been properly connected. OUT will be logic low only when GND_detect and L_detect are low. Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit VDD 0 to 2.75 V VL_detect −0.1 to VDD + 0.1 V VGND_detect −0.1 to VDD + 0.1 MIC Output Pin Voltage Range VMIC 0 to 6.0 V Maximum MIC Current IMIC 2 mA TJ(max) +125 °C Tstg −65 to +150 °C ESDHBM ESDMM 5000 250 ILU 800 MSL Level 1 Supply Voltage Range L_detect Input Pin Voltage Range GND_detect Input Pin Voltage Range Maximum Junction Temperature Storage Temperature Range ESD Capability (Note 2) Human Body Model Machine Model V Latch−up Current (Note 3) Moisture Sensitivity Level (Note 4) mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115) 3. Latch−up Current tested per JEDEC standard: JESD78 4. Moisture Sensitivity Level tested per IPC/JEDEC standard: J*STD*020A http://onsemi.com 3 NCS2300 Table 4. OPERATING RANGES Rating Conditions Symbol Min Typ Max Unit VDD 1.6 1.8 2.75 V VIN 0 VDD V Dt / DV 0 10 ns/V VMIC 0 3.0 V Ambient Temperature TA −40 85 °C Junction Temperature TJ −40 125 °C Power Supply Voltage Input Voltage L_detect and GND_detect pins Input Transition Rise or Fall Rate GND_detect pin Bias Voltage on MIC Output Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS Typical values are referenced to TA = 25°C, VDD = 1.8 V, unless otherwise noted. Min/max values apply from TA = −40°C to 85°C, unless otherwise noted. (Note 5) Test Conditions Parameter Symbol Min Typ Max Unit 7.5 12 mA 1.33 V SUPPLY CHARACTERISTICS Quiescent Supply Current VGND_detect = 1.8 V or 0 V IDD INPUT CHARACTERISTICS OF L_DETECT Voltage Input Low VDD = 1.8 V VIL Voltage Input High VDD = 1.8 V VIH Propagation Delay to OUT Cout = 15 pF, GND_detect = 0 V, L_detect = 1.31 V to 1.52 V Low Voltage Input Leakage VL_detect = 0 V High Voltage Input Leakage Input Capacitance 1.5 V tpLH, tpHL 480 ns IIL 1.8 mA VL_detect = 1.8 V IIH 500 pA f = 1 MHz CIN 3 pF INPUT CHARACTERISTICS OF GND_DETECT Voltage Input Low VDD = 1.8 V VIL Voltage Input High VDD = 1.8 V VIH Propagation Delay to OUT Cout = 15 pF, RL = 1 MW, L_detect = 0 V, GND_detect = 0 to 1.8 V Low Voltage Input Leakage 0.63 1.17 V V tpLH, tpHL 550 ps VGND_detect = 0 V IIL 1.8 mA High Voltage Input Leakage VGND_detect = 1.8 V IIH 500 pA Input Capacitance f = 1 MHz CIN 3 pF Voltage Output Low VDD = 1.8 V, IOH = 0.1 mA VOL Voltage Output High VDD = 1.8 V, IOH = −0.1 mA VOH Rise Time COUT = 15 pF, RL = 1 MW trise 7 ns Fall Time COUT = 15 pF, RL = 1 MW tfall 4 ns RDS(on) 0.9 OUTPUT CHARACTERISTICS OF OUT 0.10 1.70 V V CHARACTERISTICS OF MIC Drain−Source On Resistance of NMOS VDD = 1.8 V, IMIC = 1 mA 1.4 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by characterization and/or design. http://onsemi.com 4 NCS2300 TYPICAL CHARACTERISTICS 1.8 9.5 VDD = 1.6 V VDD = 1.8 V VDD = 2.0 V 9 8.75 8.5 8.25 8 7.75 7.5 7.25 0 25 50 75 1.74 1.72 1.7 1.68 1.66 1.64 1.62 −5 100 −3 −1 −2 SINK CURRENT (mA) Figure 3. Supply Current vs. Temperature Figure 4. VOH vs. IOH of OUT Pin 180 2 160 1.8 T = −40°C T = 25°C T = 85°C 140 −4 TEMPERATURE (°C) 120 100 80 60 40 20 VDD = 1.6 V T = −40°C T = 25°C T = 85°C 1.6 0 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 1 2 3 4 1 5 1.2 1.4 1.6 1.8 SOURCE CURRENT (mA) MIC DRAIN CURRENT (mA) Figure 5. VOL vs. IOL of OUT Pin Figure 6. On Resistance vs. Drain Current at VDD = 1.6 V 2 2 2 VDD = 1.8 V T = −40°C T = 25°C T = 85°C 1.6 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 VDD = 2.0 V T = −40°C T = 25°C T = 85°C 1.8 ON RESISTANCE (W) 1.8 ON RESISTANCE (W) 1.76 1.6 −25 ON RESISTANCE (W) VOLTAGE OUTPUT LOW (mV) 7 −50 T = −40°C T = 25°C T = 85°C 1.78 VOLTAGE OUTPUT HIGH (V) SUPPLY CURRENT (mA) 9.25 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 MIC DRAIN CURRENT (mA) MIC DRAIN CURRENT (mA) Figure 7. On Resistance vs. Drain Current at VDD = 1.8 V Figure 8. On Resistance vs. Drain Current at VDD = 2.0 V http://onsemi.com 5 2 NCS2300 TYPICAL CHARACTERISTICS 2.25 2 2 VDD = 1.8 V 1.75 1.75 1.5 VOLTAGE (V) VOLTAGE (V) 1.5 1.25 1 Input 100 mV 50 mV 20 mV 10 mV 0.75 0.5 0.25 1 0.75 VDD = 1.8 V Input 100 mV 50 mV 20 mV 10 mV 0.5 0.25 0 0 −0.25 −100 1.25 0 100 200 300 400 500 −0.25 −100 600 700 0 100 200 300 400 500 600 700 TIME (ns) TIME (ns) Figure 9. Low to High Propagation to OUT with Changing Input Overdrive of L_detect Figure 10. High to Low Propagation to OUT with Changing Input Overdrive of L_detect APPLICATIONS INFORMATION SUPPLY VOLTAGE a cross point switch and additional circuitry is necessary to detect and swap the ground and microphone pins. The NCS2300 works with a wide range of supply voltages from 1.6 V to 2.75 V. A 0.1 mF decoupling capacitor should be placed as close as possible to the VDD pin. Since the NCS2300 has built in latch-up immunity up to 800 mA, series resistors are not recommended on VDD. MIC PIN BIASING The typical application schematic in Figure 1 shows the recommended 2.2 kW pull−up resistor to the MIC bias voltage. The MIC bias voltage can exceed VDD and can go as high as 3 V. While the headset is not detected, the internal NMOS transistor is enabled to mute the MIC signal. In the typical application scenario with a 2.2 kW pull−up to a 2.3 V MIC bias voltage, the MIC pin is pulled near 1 mV when the headset is not present. The internal NMOS transistor is optimized to sink up to 2 mA of current, allowing some flexibility in the selection of the pull−up resistor and MIC bias voltage. AUDIO JACK DETECTION The NCS2300 is designed to simplify the detection of a stereo audio connector with a microphone contact. When the headset is not connected, the internal pull−up resistors on L_detect and GND_detect pull those pins high. When the headset is connected to the switched audio jack, the headset ground and left audio channel trigger L_detect and GND_detect to logic low. The NCS2300 can work with either the CTIA or OMTP standard. In order to support both standards simultaneously, http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6, 1.2x1.0, 0.4P CASE 517AA−01 ISSUE D 1 SCALE 8:1 EDGE OF PACKAGE 2X 0.10 C ÉÉ ÉÉ ÉÉ L1 E DETAIL A Bottom View (Optional) TOP VIEW 2X EXPOSED Cu 0.10 C (A3) 0.10 C A1 A 10X 0.08 C ÉÉÉ ÉÉÉ A3 DETAIL B Side View (Optional) 5X XM L 3 X M L2 b 0.10 C A B 0.05 C 6 = Specific Device Code = Date Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 4 e NOTE 3 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.30 0.40 0.00 0.15 0.40 0.50 GENERIC MARKING DIAGRAM* C A1 6X DIM A A1 A3 b D E e L L1 L2 MOLD CMPD SEATING PLANE SIDE VIEW 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D PIN ONE REFERENCE DATE 03 SEP 2010 MOUNTING FOOTPRINT* BOTTOM VIEW 6X 6X 0.42 0.40 PITCH 0.22 1.07 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON22068D 6 PIN UDFN, 1.2X1.0, 0.4P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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