NCV70517
Micro-stepping Motor Driver
Description
The NCV70517 is a micro−stepping stepper motor driver for bipolar
stepper motors. The chip is connected through I/O pins and an SPI
interface with an external microcontroller. The NCV70517 contains
a current−translation table and takes the next micro−step depending on
the clock signal on the “NXT” input pin and the status of the “DIR”
(= direction) register or input pin. The chip provides an error message
if an electrical error, an under−voltage or an elevated junction
temperature is detected. It is using a proprietary PWM algorithm
for reliable current control.
NCV70517 is fully compatible with the automotive voltage
requirements and is ideally suited for general−purpose stepper motor
applications in the automotive, industrial, medical, and marine
environment.
Due to the technology, the device is especially suited for use
in applications with fluctuating battery supplies.
Features
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December, 2018 − Rev. 0
1
32
QFNW32
CASE 484AB
MARKING DIAGRAM
1
Dual H−bridge for 2−phase Stepper Motors
Programmable Peak−current up to 800 mA
Low Temperature Boost Current up to 1100 mA
On−chip Current Translator
SPI Interface
5 Step Modes from Full−step up to 16 Micro−steps
Fully Integrated Current−sensing and Current−regulation
Back−EMF Measurement
On Chip Stall Detection
PWM Current Control with Automatic Selection of Fast and Slow
Decay
Fixed PWM Frequency
Active Fly−back Diodes
Full Output Protection and Diagnosis
Thermal Warning and Shutdown
Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs, 5 V
Tolerant Open Drain Outputs
Reset Function
Overcurrent Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2016
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1
N70517−2
FAWLYYWWG
G
N70517−2
F
A
WL
YY
WW
G
= Specific Device Code
= Fab Location
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 23 of this data sheet.
Publication Order Number:
NCV70517/D
NCV70517
TYPICAL APPLICATION SCHEMATIC
The application schematic below shows typical
connections for applications with low axis counts and/or
with software SPI implementation. For applications with
many stepper motor drivers, some “minimal wiring”
examples are shown at the last sections of this datasheet.
100 nF
VDD
C4
100 nF
C3
D1
100 nF
VBAT
C1
C2
100 uF
R1 R2
VDD
VBB
VBB
DIR
R3
NXT
R4
DO
R8
uC
R5
MOTXP
NCV70517
DI
MOTXN C5
CLK
R6
CSB
R7
MOTYP
ERRB
R9
MOTYN
M
C6
C7
C8
GND
Figure 1. Typical Application Schematic
Table 1. EXTERNAL COMPONENTS
Component
C1
C2, C3
C4
C5, C6, C7, C8
Function
VBB buffer capacitor (Note 1)
Max Tolerance
Unit
22 ... 100
±20%
mF
VBB decoupling capacitor (Note 2)
100
±20%
nF
Optional VDD decoupling capacitor (Note 3)
100
±20%
nF
1 ... 3.3 max
±20%
nF
1..5
±10%
kW
1
±10%
kW
100
±10%
W
Optional EMC filtering capacitor (Note 4)
R1, R2
Pull up resistor
R3 – R7
Optional resistors
R8, R9
Optional resistors (Note 5)
D1
Typ. Value
Optional reverse protection diode
e.g. MURD530
1. Low ESR < 4 W, mounted as close as possible to the NCV70517. Total decoupling capacitance value has to be chosen properly to reduce
the supply voltage ripple and to avoid EM emission.
2. C2 and C3 must be close to pins VBB and coupled GND directly.
3. Radiated emissions around 100 MHz can be improved by avoiding this capacitor.
4. Optional capacitors for improvement of EMC and system ESD performance. The slope times on motor pins can be longer than specified
in the AC table.
5. Value depends on characteristics of mC inputs for DO and ERRB signals.
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NCV70517
VDD
Timebase
DI
DIR
ERRB
EMC
T
R
A
N
S
L
A
T
O
R
TSD
SPI
Open/
Short
DO
NXT
Internal voltage
regulator 3.3 V
STALL
CLK
CSB
VBB
Logic &
Registers
OTP
P
W
M
MOTXN
I−sense
EMC
P
W
M
Band−
gap
NCV70517
GND
Figure 2. Block Diagram
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MOTYP
MOTYN
I−sense
POR
UV
detect
MOTXP
NCV70517
GNDP
GNDP
MOTXN
MOTXN
MOTYN
MOTYN
GNDP
GNDP
PACKAGE AND PIN DESCRIPTION
32
31
30
29
28
27
26
25
MOTXP 1
24 MOTYP
MOTXP 2
23 MOTYP
VBB 3
22 VBB
VBB 4
21 VBB
QFN32 5x5
NCV70517
DIR 5
20 NC
NC 6
19 NC
NC 7
18 NC
CSB 8
12
13
DO
ERRB
VDD
GND
14
15
16
CLK
11
NC
10
NC
9
DI
17 NXT
Figure 3. Pin Connections – QFNW32 5x5
Table 2. PIN DESCRIPTION
Pin No.
QFNW32 5x5
Pin Name
Description
1, 2
MOTXP
3, 4, 21, 22
VBB
Positive end of phase X coil
Battery voltage supply
5
DIR
Direction input
6, 7, 14, 15, 18, 19, 20
NC
Not Connected
8
CSB
I/O Type
Driver Output
Supply
Digital Input
SPI chip select input
Digital Input
9
DI
SPI data input
10
DO
SPI data output (Open Drain)
Digital Output
Digital Input
Error Output (Open Drain)
Digital Output
11
ERRB
12
VDD
Internal supply
Supply
13
GND
Ground
Supply
16
CLK
SPI clock input
Digital Input
17
NXT
Next micro−step input
Digital Input
23, 24
MOTYP
25, 26, 31, 32
GNDP
Positive end of phase Y coil
27, 28
MOTYN
Negative end of phase Y coil
Driver Output
29, 30
MOTXN
Negative end of phase X coil
Driver Output
Ground
Driver Output
Supply
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NCV70517
Table 3. ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Min
Supply voltage (Note 6)
VBB
Digital input/outputs voltage
VIO
Junction temperature range (Note 7)
Storage Temperature (Note 8)
Max
Unit
−0.3
+40
V
−0.3
+6.0
V
Tj
−50
+175
°C
Tstrg
−55
+160
°C
HBM Electrostatic discharge voltage (Note 9)
Vesd_hbm
−2
+2
kV
System Electrostatic discharge voltage (Note 10)
Vsyst_esd
−8
+8
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. VBB Max is +43 V for limited time < 0.5 s.
7. The circuit functionality is not guaranteed.
8. For limited time up to 100 hours. Otherwise the max storage temperature is 85°C.
9. HBM according to AEC−Q100: EIA−JESD22−A114−B (100 pF via 1.5 kW).
10. System ESD, 150 pF, 330 W, contact discharge on the connector pin, unpowered.
Operating ranges define the limits for functional
operation and parametric characteristics of the device. A
mission profile (Note 11) is a substantial part of the
operation conditions; hence the Customer must contact
ON Semiconductor in order to mutually agree in writing on
the allowed missions profile(s) in the application.
Table 4. RECOMMENDED OPERATING RANGES
Symbol
Min
Max
Unit
Battery Supply voltage
Characteristic
VBB
+6
Typ
+29
V
Digital input/outputs voltage
VIO
0
+5.5
V
Parametric operating junction temperature range (Note 12)
Tjp
−40
+145
°C
Functional operating junction temperature range (Note 13)
Tjf
−40
+160
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time,
the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the
device is operated by the customer, etc. No more than 100 cumulated hours in life time above Ttw.
12. The parametric characteristics of the circuit are not guaranteed outside the Parametric operating junction temperature range.
13. The maximum functional operating temperature range can be limited by thermal shutdown Ttsd.
Package Thermal Characteristic
The major thermal resistances of the device are the Rth
from the junction to the ambient (Rthja) and the Rth from the
junction to the exposed pad (Rthjp).
Using an exposed die pad on the bottom surface of the
package is mainly contributing to this performance. In order
to take full advantage of the exposed pad, it is most
important that the PCB has features to conduct heat away
from the package. In the table below, one can find the values
for the Rthja and Rthjp:
The NCV70517 is available in a thermally optimized
QFNW32 5x5 package. For the optimizations, the package
has an exposed thermal pad which has to be soldered to the
PCB ground plane. The ground plane needs thermal vias to
conduct the heat to the bottom layer.
For precise thermal cooling calculations the major
thermal resistances of the devices are given. The thermal
media to which the power of the devices has to be given are:
• Static environmental air (via the case)
• PCB board copper area (via the device pins and
exposed pad)
Table 5. THERMAL RESISTANCE
Package
Rth, Junction−to−Exposed Pad, Rthjp
QFNW32 5x5
6 K/W
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NCV70517
EQUIVALENT SCHEMATICS
The following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified
representations of the circuits used.
DIGITAL
IN
DI, CLK,
NXT, DIR
DIGITAL
OUT
ERRB
Ipd
VDD
Ipu
MOT
OUT
DIGITAL
IN
CSB
MOTXP,
MOTXN,
MOTYN,
MOTYP
VDD
VBB
DIGITAL
OUT
DO
Figure 4. Input and Output Equivalent Diagrams
ELECTRICAL CHARACTERISTICS
DC PARAMETERS
range from 6 to 29 V, unless otherwise specified.
Convention: currents flowing into the circuit are defined as
positive.
The DC parameters are guaranteed over junction
temperature from −40 to 145°C and VBB in the operating
Table 6. DC PATAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
MOTORDRIVER
MOTXP
MOTXN
MOTYP
MOTYN
VBB = 14 V
800
mA
Max current during booster function
VBB = 14 V, Tj = −45°C
1100
mA
IMSabs
Absolute error on coil current
VBB = 14 V, Tj = 145°C
IMSmax,Peak = 800 mA
and 100 mA
−10
10
%
IMSrel
Matching of X & Y coil currents
VBB = 14 V
IMSmax,Peak = 800 mA
and 100 mA
−7
7
%
2.4
W
IMSmax,Peak
IMSboost,Peak
RDS(on)
Rmpd
Max current through motor coil in
normal operation
On resistance of High side + Low
side Driver at the highest current
range
Tj = 145°C
Motor pin pull−down resistance
HiZ mode
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70
kW
NCV70517
Table 6. DC PATAMETERS (continued)
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
0.8
V
LOGIC INPUTS
VinL
CSB
VinH
Logic low input level, max
Logic high input level, min
2.4
V
IinL_pu
Input pull up current for logic low
level (Note 14)
IinL_pu_slp
Input pull up current for logic low
level in sleep mode (Note 14)
3
mA
IinH_pu
Input leakage current for logic high
level
1
mA
0.8
V
VinL
DI, CLK
25
Logic low input level, max
VinH
Logic high input level, min
2.4
Rinpd
DI, CLK pin pull−down resistance
(Note 14)
75
VinL
NXT, DIR
V
150
Logic low input level, max
VinH
Logic high input level, min
2.4
Rinpd
NXT, DIR pin pull−down resistance
(Note 14)
75
mA
300
kW
0.8
V
V
150
300
kW
0.4
V
OPEN DRAIN LOGIC OUTPUT
VOLmax
ERRB
Output voltage
6 mA sink current
VOHmax
Maximum drain voltage
5.5
V
IOLmax
Maximum allowed drain current
(Note 22)
12
mA
0.4
V
PUSH−PULL LOGIC OUTPUT WHEN CSB = 0 (Figure 4)
VOLmax
DO
Output voltage low
6 mA sink current
VOHmin
Output voltage high without pull−up
4 mA source current
VDD − 1.3
V
VOHmax
Maximum pin voltage
5.5
V
IOLmax
Maximum allowed pin current
(Note 22)
12
mA
THERMAL WARNING & SHUTDOWN
Ttw
Thermal warning (Notes 15 and 16)
135
145
155
°C
Ttsd
Thermal shutdown (Note 17)
155
165
175
°C
Tlow
Low temperature level (Note 15)
12
28
44
°C
H−Bridge off voltage low threshold
5.7
6.0
6.3
V
Under voltage hysteresis
100
250
600
mV
SUPPLY AND VOLTAGE REGULATOR
UV
VBB
UV_HYST
Ibat
Total current consumption (Note 18)
Unloaded outputs
VBB = 29 V
4
15
mA
Ibat_s
Sleep mode current consumption at
temperature ≤ 85°C (Note 19)
VBB = 5.5 V & 18 V
Tj ≤ 85°C
12
20
mA
Regulated internal supply (Note 20)
5.5 V < VBB < 29 V
Load = 0 mA, 15 mA
3.3
3.6
V
3.0
V
80
mA
VDD
VddReset
IddLim
VDD
Digital supply reset level @ power
down (Note 21)
Current limitation
Pin shorted to ground
VBB = 14 V
3.0
14. All Pull−up and pull down currents stay activated during sleep to avoid floating input pins. Placing the pin in wrong state during sleep results
in higher sleep currents in the application.
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NCV70517
15. Thermal warning and low temperature level are derived from thermal shutdown (Ttw = Ttsd – 20°C, Tlow = Ttsd – 137°C).
16. No more than 100 cumulated hours in life time above Ttw.
17. Parameter guaranteed by trimming relevant OTPs in production test at 160°C and VBB = 14 V.
18. Dynamic current is with oscillator running, all analogue cells active. Coil currents 0 mA, SPI active, ERRB inactive, no floating inputs.
19. All outputs unloaded, no floating inputs. Not tested in production, guaranteed by device characterization.
20. Pin VDD must not be used for any external supply.
21. The SPI registers content will not be altered above this voltage.
22. Maximum allowed drain current that the output can withstand without getting damaged. Not tested in production.
RDS(ON)/RDS(ON)_MAX [−]
1
0,8
0,6
0,4
Typ
BestCase
0,2
WorstCase
0
−50
0
50
100
150
temp [5C]
Figure 5. ON Resistance of High Side + Low Side Driver at the Highest Current Range
24
22
Ibat_s [mA]
20
18
VBB = 14 V
16
VBB = 18 V
14
12
10
8
−40
−20
0
20
40
60
80
100
120
temp [5C]
Figure 6. Typical Sleep Mode Current Consumption
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140
NCV70517
AC PARAMETERS
The AC parameters are guaranteed over junction temperature from −40 to 145°C and VBB in the operating range from 6
to 29 V, unless otherwise specified.
Table 7. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
Frequency of internal oscillator
VBB = 14 V
9
10
11
MHz
INTERNAL OSCILLATOR
fosc
MOTORDRIVER
fpwm
MOTxx
fjit_depth
(Note 23)
PWM jitter modulation depth
tOCdet
Open coil detection with
PWM = 100% (Note 23)
tbrise
Turn−on transient time, between
10% and 90%, IMD = 300 mA,
VBB = 13.5 V, 1 nF at motor pins
tbfall
UVtime
PWM frequency
Turn−off transient time, between
10% and 90%, IMD = 200 mA,
VBB = 13.5 V, 1 nF at motor pins
MOTxx
Under−voltage debounce time
(Note: H−bridge off)
28.4
SPI bit PWMJen = 1
(Note 23)
kHz
20
SPI bit OpenDet [1:0] = 00
5
SPI bit OpenDet [1:0] = 01
25
SPI bit OpenDet [1:0] = 10
50
SPI bit OpenDet [1:0] = 11
200
SPI bit EMC [1:0] = 00
150
SPI bit EMC [1:0] = 01
300
SPI bit EMC [1:0] = 10
1000
SPI bit EMC [1:0] = 11
2000
SPI bit EMC [1:0] = 00
150
SPI bit EMC [1:0] = 01
300
SPI bit EMC [1:0] = 10
1000
SPI bit EMC [1:0] = 11
2000
SPI bit UVtime [1:0] = 00
0
SPI bit UVtime [1:0] = 01
5
SPI bit UVtime [1:0] = 10
10
SPI bit UVtime [1:0] = 11
30
%
ms
ns
ns
ms
DIGITAL OUTPUTS
tH2L
DO,
ERRB
Output fall−time (90% to 10%)
from VInH to VInL
Capacitive load 200 pF
and pull−up 1.5 kW
50
ns
Hard reset trigger time (Note 23)
See hard reset function
20
ms
Hard reset DIR pulse width
(Note 23)
2.5
ms
NXT set−up time
(Note 23)
2.5
Hard reset error indication
(Note 23)
CSB wake−up low pulse width
(Note 23)
2
CSB no wake−up low pulse
width
(Note 23)
220
ms
See Sleep Mode
250
ms
NXT minimum, high pulse width
2
ms
NXT minimum, low pulse width
2
ms
HARD RESET FUNCTION
thr_trig
DIR
thr_dir
thr_set
NXT
thr_err
ERRB
tcsb_width
CSB
tcsb_no_wu
twu
Wake−up time
ms
50
ms
150
ms
NXT/DIR INPUTS
tNXT_HI
tNXT_LO
fNXT
tCSB_LO_WIDTH
NXT
NXT max repetition rate
fPWM/2
NXT pin trigger after SPI NXT
command
1
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9
kHz
ms
NCV70517
Table 7. AC PARAMETERS
Symbol
Pin(s)
Parameter
Test Conditions
Min
Typ
Max
Unit
NXT, DIR
NXT set time, following change
of DIR
25
ms
NXT hold time, before change
of DIR
25
ms
NXT/DIR INPUTS
tDIR_SET
tDIR_HOLD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
23. Derived from the internal oscillator.
Table 8. SPI INTERFACE
Symbol
Parameter
Min
Typ
Max
Unit
tCSS
CSB setup time (Note 24)
0.5
ms
tCSH
CSB hold time
0.5
ms
tCS
CSB high time
1
ms
tWL
CLK low time
0.5
ms
tWH
CLK high time
0.5
ms
tSU
DI set up time, valid data before rising edge of CLK
0.25
ms
tH
DI hold time, hold data after rising edge of CLK
0.275
tCSDO
ms
CSB low to DO valid
tDIS
Output (DO) disable time (Note 25)
0.08
0.23
ms
0.32
ms
tV1→0
Output (DO) valid (Note 25)
0.32
ms
tV0→1
Output (DO) valid (Note 26)
0.32 + t(RC)
ms
24. After leaving sleep mode an additional wait time of 250 ms is needed before pulling CSB low.
25. SDO low–side switch activation time.
26. Time depends on the SDO load and pull–up resistor.
tCS
VIH
CSB
VIL
tCSS
tWH
t CSH
tWL
VIH
CLK
VIL
tSU
tH
VIH
DI
VIL
DI14
DI15
DI13
DI1
DI0
tDIS
tV
tCSDO
VIH
DO HI−Z
DO15
DO14
DO13
DO1
VIL
Figure 7. SPI Timing
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DO0
HI−Z
NCV70517
DETAILED OPERATING DESCRIPTION
H−Bridge Drivers with PWM Control
In order to reduce the radiated/conducted emission,
voltage slope control is implemented in the output switches.
A protection against shorts on motor lines is implemented.
When excessive voltage is sensed across a MOSFET for a
time longer than the required transition time, then the
MOSFET is switched−off.
Two H−bridges are integrated to drive a bipolar stepper
motor. Each H−bridge consists of two low−side N−type
MOSFET switches and two high−side P−type MOSFET
switches. One PWM current control loop with on−chip
current sensing is implemented for each H−bridge.
Depending on the desired current range and the micro−step
position at hand, the RDS(on) of the low−side transistors will
be adapted to maintain current−sense accuracy.
A comparator compares continuously the actual winding
current with the requested current and feeds back the
information to generate a PWM signal, which turns on/off
the H−bridge switches. The switching points of the PWM
duty−cycle are synchronized to the on−chip PWM clock.
The PWM frequency will not vary with changes in the
supply voltage. Also variations in motor−speed or
load−conditions of the motor have no effect. There are no
external components required to adjust the PWM frequency.
In order to avoid large currents through the H−bridge
switches, it is guaranteed that the top− and bottom−switches
of the same half−bridge are never conductive
simultaneously (interlock delay).
Motor Enable−Disable
The H−bridges and PWM control can be disabled
(high−impedance state) by means of a bit in the
SPI control registers. =0 will only disable the
drivers and will not impact the functions of NXT, DIR, SPI
bus, etc. The H−bridges will resume normal PWM operation
by writing =1 in the SPI register. PWM current
control is then enabled again and will regulate current in
both coils corresponding with the position given by the
current translator.
Automatic Forward and Slow−Fast Decay
The PWM generation is in steady−state using
a combination of forward and slow−decay. For transition to
lower current levels, fast−decay is automatically activated to
allow high−speed response. The selection of fast or slow
decay is completely transparent for the user and no
additional parameters are required for operation.
Icoil
Set value
Actual value
t
0
TPWM
Forward & Slow Decay
Forward & Slow Decay
Fast Decay & Forward
Figure 8. Forward and Slow/Fast Decay PWM
Automatic Duty Cycle Adaptation
completely automatic and requires no additional parameters
for operation. The state of the duty cycle adaptation mode is
represented in the internal T/B bits for both motor windings
X and Y. Figure 9 gives a representation of the duty cycle
adaptation.
If during regulation the set point current is not reached
before 75% of tpwm, the duty cycle of the PWM is adapted
automatically to > 50% (top regulation) to maintain the
requested average current in the coils. This process is
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NCV70517
|Icoil |
Duty Cycle
< 50%
Duty Cycle > 50%
Duty Cycle < 50%
Actual value
Set value
0
TPWM
Bit T/B
Bottom reg. Bit T/B = 0
Top reg. Bit T/B = 1
Bottom reg. Bit T/B = 0
Figure 9. Automatic Duty Cycle Adaptation
Active Break
When the micro−step resolution is reduced, then the
corresponding least−significant bits of the translator
position are set to “0”. This means that the position in the
current table moves to the right and in the case that
micro−step position of desired new resolution does not
overlap the micro−step position of current resolution, the
closest value up or down in required column is set depending
on the direction of rotation.
When the micro−step resolution is increased, then the
corresponding least−significant bits of the translator
position are added as “0”: the micro−step position moves to
the left on the same row.
In general any change of SPI bits have no
effect on current micro−step position without consequent
occurrence of NXT pulse or SPI command (see
NXT input timing below). When NXT pulse or
SPI command arrives, the motor moves into next micro−step
position according to the current SPI bits value.
Besides the micro−step modes, also full step mode is
implemented. Full step mode activates always only one coil
at a time.
Whenever active break is activated ( bit is set),
both bottom drivers of active H−bridge (based on actual
MSP position) are switched on.
By this mean the position is frozen and current starts
recirculating through the bottom drivers, causing faster
stopping of the motor.
STEP TRANSLATOR
Step Mode
The step translator provides the control of the motor
by means of step mode SPI register SM[2:0], SPI bits DIRP,
NXTP and input pins DIR (direction of rotation) and NXT
(next pulse). It is translating consecutive steps
into corresponding currents in both motor coils for a given
step mode.
One out of five possible stepping modes can be selected
through SPI−bits SM[2:0]. After power−on or hard reset, the
coil−current translator is set to the default to 1/16
micro−stepping at position ‘8*’. When remaining in the
default step mode, subsequent translator positions are all in
the same column and increased or decreased with 1. Table 9
lists the output current versus the translator position.
www.onsemi.com
12
NCV70517
Table 9. TRANSLATOR TABLE
MSP[5:0]
Step mode SM[2:0]
% of Imax
MSP[5:0]
Step mode SM[2:0]
% of Imax
000
001
010
011
100
Coil Y Coil X
MSP[5:0]
1/16
1/8
1/4
1/2
FS
000
001
010
011
100
MSP[5:0]
1/16
1/8
1/4
1/2
FS
00 0000
0
0
0
0
0
0
100
10 0000
32
16
8
4
2
0
−100
00 0001
1
−
−
−
−
9,8
99,5
10 0001
33
−
−
−
−
−9,8
−99,5
00 0010
2
1
−
−
−
19,5
98,1
10 0010
34
17
−
−
−
−19,5
−98,1
Coil Y
Coil X
00 0011
3
−
−
−
−
29
95,7
10 0011
35
−
−
−
−
−29
−95,7
00 0100
4
2
1
−
−
38,3
92,4
10 0100
36
18
9
−
−
−38,3
−92,4
00 0101
5
−
−
−
−
47,1
88,2
10 0101
37
−
−
−
−
−47,1
−88,2
00 0110
6
3
−
−
−
55,6
83,1
10 0110
38
19
−
−
−
−55,6
−83,1
00 0111
7
−
−
−
−
63,4
77,3
10 0111
39
−
−
−
−
−63,4
−77,3
00 1000
8(*)
4
2
1
−
70,7
70,7
10 1000
40
20
10
5
−
−70,7
−70,7
00 1001
9
−
−
−
−
77,3
63,4
10 1001
41
−
−
−
−
−77,3
−63,4
00 1010
10
5
−
−
−
83,1
55,6
10 1010
42
21
−
−
−
−83,1
−55,6
00 1011
11
−
−
−
−
88,2
47,1
10 1011
43
−
−
−
−
−88,2
−47,1
00 1100
12
6
3
−
−
92,4
38,3
10 1100
44
22
11
−
−
−92,4
−38,3
00 1101
13
−
−
−
−
95,7
29
10 1101
45
−
−
−
−
−95,7
−29
00 1110
14
7
−
−
−
98,1
19,5
10 1110
46
23
−
−
−
−98,1
−19,5
00 1111
15
−
−
−
−
99,5
9,8
10 1111
47
−
−
−
−
−99,5
−9,8
01 0000
16
8
4
2
1
100
0
11 0000
48
24
12
6
3
−100
0
01 0001
17
−
−
−
−
99,5
−9,8
11 0001
49
−
−
−
−
−99,5
9,8
01 0010
18
9
−
−
−
98,1
−19,5
11 0010
50
25
−
−
−
−98,1
19,5
01 0011
19
−
−
−
−
95,7
−29
11 0011
51
−
−
−
−
−95,7
29
01 0100
20
10
5
−
−
92,4
−38,3
11 0100
52
26
13
−
−
−92,4
38,3
01 0101
21
−
−
−
−
88,2
−47,1
11 0101
53
−
−
−
−
−88,2
47,1
01 0110
22
11
−
−
−
83,1
−55,6
11 0110
54
27
−
−
−
−83,1
55,6
01 0111
23
−
−
−
−
77,3
−63,4
11 0111
55
−
−
−
−
−77,3
63,4
01 1000
24
12
6
3
−
70,7
−70,7
11 1000
56
28
14
7
−
−70,7
70,7
01 1001
25
−
−
−
−
63,4
−77,3
11 1001
57
−
−
−
−
−63,4
77,3
01 1010
26
13
−
−
−
55,6
−83,1
11 1010
58
29
−
−
−
−55,6
83,1
01 1011
27
−
−
−
−
47,1
−88,2
11 1011
59
−
−
−
−
−47,1
88,2
01 1100
28
14
7
−
−
38,3
−92,4
11 1100
60
30
15
−
−
−38,3
92,4
01 1101
29
−
−
−
−
29
−95,7
11 1101
61
−
−
−
−
−29
95,7
01 1110
30
15
−
−
−
19,5
−98,1
11 1110
62
31
−
−
−
−19,5
98,1
01 1111
31
−
−
−
−
9,8
−99,5
11 1111
63
−
−
−
−
−9,8
99,5
*Default position after reset of the translator position.
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13
NCV70517
Translator Position
The translator position can be read and set by the SPI
register . This is a 6−bit number equivalent to
the 1/16th micro−step from Table 9: Translator Table. The
translator position is updated immediately following a next
micro−step trigger (see below).
0.8 VCC
CSB
t CSB_LO_WIDTH
NXT
0.2 VCC
NXT
Figure 11. NXT Input Non Overlapping Zone with
the SPI Command
Update
Translator Position
Update
Translator Position
For control by means of I/O’s, the NXT pin operation with
respect to DIR pin should be in a non−overlapped way. See
also the timing diagram below (refer to the Table 7 − AC
Parameters for the timing values). The SPI bits
setting, when changed, is accepted upon the consequent
either NXT pin rising edge or SPI command write
only. On the other hand, the SPI bits ,
and can change state at the same time in the same
SPI command: the next micro−step will be applied with the
new settings. Writing to the SPI register is
accepted and applied to translator table immediately, does
not taking actual step mode into account.
Figure 10. Translator Position Timing Diagram
Direction
The direction of rotation is selected by means of input pin
DIR and its “polarity bit” (SPI register). The
polarity bit allows changing the direction of
rotation by means of only SPI commands instead of the
dedicated input pin.
Direction = DIR−pin EXOR
Positive direction of rotation means counter−clockwise
rotation of electrical vector Ix + Iy. Also when the motor is
disabled (=0), both the DIR pin and
will have an effect on the positioner. The logic state of the
DIR pin is visible as a flag in SPI status register.
t NXT_HI
Next Micro−Step Trigger
tDIR_SET
DIR
tDIR_HOLD
VALID
Figure 12. NXT input Timing Diagram
Motor Current
On cold temperatures below Tlow (see Table 6 − DC
Parameters) the current can be boosted to higher values by
SPI bit . After reaching temperature of thermal
warning Ttw, current is automatically decreased to
unboosted level. Status of the boost function can be read in
SPI bit. The motor current settings correspond
to the following current levels:
• Also when the motor is disabled (=0),
•
0,5 VCC
NXT
Positive edges on the NXT input − or activation of the
“NXT pushbutton” in the SPI input register − will
move the motor current one step up/down in the Table 9 −
Translator table. The bit in SPI is used to move
positioner one (micro−)step by means of only SPI
commands. If the bit is set to “1”, it is reset automatically to
“0” after having advanced the positioner with one
micro−step.
Trigger “Next micro−step” = (positive edge on NXT−pin)
OR (=1)
tNXT_LO
NXT/DIR functions will move the positioner according
to the logic (only if =0).
In order to be sure that both the NXT pin and the
SPI command are individually attended, the
following non overlapping zone has to be respected.
In this case it is guaranteed that both triggers will have
effect (2 steps are taken).
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14
NCV70517
Stall and Motion Detection
Table 10. IMOT VALUES (4BIT)
Register
Value
Peak Motor
Current IMOT (mA)
Peak Boost Motor
Current IMOT (mA)
0
59
81
1
71
98
2
84
116
3
100
138
4
119
164
5
141
194
6
168
231
7
200
275
8
238
327
Motion detection is based on the Back Electromotive
Force (BEMF or back emf) generated into the running
motor. When the motor is blocked, e.g. when it hits the
end−position, the velocity and as a result also the generated
back emf, is disturbed. The NCV70517 measures the back
emf during the current zero crossing phase and makes it
available in the SPI status register SR5. The back emf
voltage is measured several times in each PWM cycle during
zero crossing phase. Samples taken during PWM ON phase
of the switches in the second coil are discarded not to add
noise to measurement (see Figure 13). Results are then
converted into a 5−bits word with the
following formula:
9
283
389
BEMF_code(dec) + V_MOT_XorY_diff(V)
A
336
462
B
400
550
C
476
655
D
566
778
E
673
925
F
800
1100
When the result is ready, it is indicated by bit
in status register.
When using normal mode of back emf measurement
( = 0), last sample before end of current zero
crossing phase becomes available in register
(see the red circle on Figure 13).
When the enhanced back emf measurement mode is set by
bit, all non discarded results are
continuously available in register (see red and
all black circles on Figure 13). This allows microcontroller
(when reading content of the register fast enough) to follow
back emf signal and its shape during zero crossing phase and
use more complex algorithms to optimize the work of driven
stepper motor.
Whenever is changed, the new coil currents
will be updated immediately at the next PWM period.
In case the motor is disabled (=0), the logic is
functional and will have effect on NXT/DIR operation (not
on the H−bridges). When the chip is in sleep mode, the logic
is not functional and as a result, the NXT pin and DIR pin
will have no effect.
Note: The hard−reset function is embedded by means of a
special sequence on the DIR pin and NXT pin, see also
Hard−Reset Function chapter.
Gain
5
( )
4
25
2.41
I coil X
Ideal Coil Current
0
Under−voltage Detection
The NCV70517 has one undervoltage threshold level UV
(see Table 6 − DC Parameters).
Undervoltage warning bit is activated as when
the UV comparator threshold is hit (cleared by read as when
the undervoltage condition disappears). This allows the
MCU taking actions at system level if required.
When supply voltage VBB drops below UV threshold and
stays there longer than set undevoltage debounce time, the
undervoltage detection flag is set and ERRB pin is
pulled down. Undervoltage debounce time can be selected
by means of register.
Only if the =0 the motor can be enabled again
by writing =1 in the control register.
Behavior of the H-bridge after UV detection can be
selected by bit. When = 0, H-bridge
goes to Hi-Z state. When = 1, H-bridge motor
brake (shorted to GDN).
Note: When Next pulse is applied (by means of NXT pin or
bit via SPI) during undervoltage condition, the
step loss bit is set.
Real Coil Current
Current Decay
Zero crossing position
(0;32 )
NXT
t
NXT
Pins MXP/MXN in HiZ state
V MXP/MXN
MXN
MXN
MXP
VBB + 0.6 V
Voltage Transient
V MYP/MYN
MYP MYP
MYP
MYP
MYP
MYP
Figure 13. Back Emf Sampling
15
MXP
t
t
BEMF
sampling
www.onsemi.com
MXP
VBEMF
NCV70517
current. Sign is determined by comparator, which compares
the polarity of voltage measured over the coil with expected
polarity of voltage.
For slow speed or when a motion ends at a full step
position (there is an absence of next NXT trigger), the end
of the zero crossing is taking too long or is non−existing. In
this case, the back emf voltage is taken the latest at “stall
time−out” time and this value is used also for comparison
with stall threshold to detect stall situation.
The “stall time−out” is set in SPI by means of
register and is expressed in counts of 4/fpwm (See AC
Parameters), roughly in steps of 0.2 ms. If = 0,
time−out is not active.
At the end of the current zero crossing phase the internal
circuitry compares measured back emf voltages
with register, which determines threshold for
stall detection. The last sample of back emf taken before end
of zero crossing phase is used for stall detection in normal
mode as well as in enhanced back emf mode. When
= 0 then stall detection is disabled. When
value of is different from 0 and measured back
emf signal is lower than threshold for 2
succeeding coil current zero−crossings (including both X
and Y coil), then the bit in SPI status register 1
is set, the current translator table goes 135 degrees
in opposite direction and the ERRB pin is pulled down,
IMOT is maintained. Direction has to change its state at least
once and then bit can be cleared by reading the
status register 1. With stall bit cleared, the chip reacts on
“Next Micro−step Triggers” and ERRB pin becomes
inactive again.
Notes:
1. Used stall detection is covered by patent US
8,058,894B2
2. As the stall threshold register is 4
bits wide, the 4 MSBs of 5−bit
register are taken for comparison
H−bridge
HiZ state
VXP
VXN
VBEMF
NXT
NXT
XP
XN
2 mA
BEMF polarity
Expected polarity
XOR
Bemfs
Figure 14. Back Emf Sign Value
The last measured back emf value , sign flag
and coil where the last back emf sample was taken
can be read out via SPI.
Table 11. STALL THRESHOLDS SETTINGS (4BIT)
StThr Index
Stall detection and Bemf measurement are performed
only when Speed register value is less than or
equal to Speed threshold register value .
Stall detection is disabled if time between two consecutive
NXT pulses is lower than 74.5 ms (PWMJen = 0) or 80 ms
(PWMJen = 1).
Range and resolution of Speed register and Speed
threshold register are 0 to 5100 us and 20 us/digit for half
stepping mode. Accuracy of speed (time) measurement is
given by the accuracy of the internal oscillator.
If measured back emf voltage has not expected polarity,
the back emf sign flag is set. Motor pin, where
lower voltage is expected, is tied to GND by pull down
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16
StThr Level (V)
StThr Level (V)
BemfGain = 0
BemfGain = 1
0
Disable
Disable
1
0.48
0.24
2
0.96
0.48
3
1.44
0.72
4
1.92
0.96
5
2.4
1.2
6
2.88
1.44
7
3.36
1.68
8
3.84
1.92
9
4.32
2.16
A
4.8
2.4
B
5.28
2.64
C
5.76
2.88
D
6.24
3.12
E
6.72
3.36
F
7.2
3.6
NCV70517
WARNING, ERROR DETECTION AND
DIAGNOSTICS FEEDBACK
to protect the integrated circuit. Each driver stage has
an individual detection bit for the N side and the P side.
When short circuit is detected, is set to 0. The
positioner, the NXT and DIR stay operational. The flag
(result of OR−ing the latched flags:
OR OR OR
OR OR OR
OR OR OR
) is reset when the microcontroller reads out the
short circuit or open coil status flags in status registers.
To enable the motor again after reading out of the status
flags, =1 has to be written.
Notes:
1. Successive reading of the flags and
re−enabling the motor in case of a short circuit
condition may lead to damage of the drivers.
2. Example: SHRTXPT means: Short at X coil,
Positive output pin, Top transistor.
3. In case of the short from any stepper motor pin
to the top side during switching event from bottom
to top on motor pin, the flag “short to bottom side”
is set instead of the expected “short to top side”
flag.
Open & Short Circuit Diagnostic
The NCV70517 stepper driver features an enhanced
diagnostic detection and feedback, to be read by the external
microcontroller unit (MCU). Among the main items of
interest for the application and typical failures, are open coil
and the short circuit condition, which may be to ground
(chassis), or to supply (battery line).
When in normal mode, the device will continuously check
upon errors with respect to the expected behavior.
The open load condition is determined by the fact that the
PWM duty cycle keeps 100% value for a time longer than set
by register. This is valid of course only for
the X/Y coil where the current is supposed to circulate,
meaning that in full step positions (MSP[5:0] = {0; 16; 32;
48} (dec)) the open load can be detected only for one of the
coil at a time (respectively {X; Y; X; Y}). The same
reasoning applies for the short circuits detection.
Due to the timeout value set by , the open
coil detection is dependent on the motor speed. In more
detail, there is a maximum speed at which it can be done.
Table 12 specifies these maxima for the different step
modes. For practical reasons, all values are given in full
steps per second.
Step Loss Detection
When Next pulse is applied (by means of NXT pin or
bit via SPI) or register is written during
error condition, the step loss bit is set.
= ( OR OR ) AND ((NXT
OR ) OR write)
Step loss bit is cleared after read out.
Table 12. MAXIMUM VELOCITIES FOR OPEN COIL
DETECTION
Step Mode
Speed [FS/s] for given
00
01
10
11
Full Step
200
40
20
5
1/2
300
60
30
7.5
1/4
350
70
35
8.8
1/8
375
75
37.5
9.4
1/16
387.5
77.5
38.8
9.7
Thermal Warning and Shutdown
When junction temperature is above Ttw, the thermal
warning bit is set (SPI register) and the ERRB pin is
pulled down (*). If junction temperature increases
above thermal shutdown level, then also the flag is
set, the ERRB pin is pulled down, the motor is disabled
( = 0) and the hardware reset is disabled. If Tj <
Ttw level and bit has been read−out, the status
of is cleared and the ERRB pin is released.
Only if the ==0, the motor can be enabled
again by writing =1 in the control register 1.
During the over temperature condition the hardware reset
will not work until Tj < Ttw and the readout is done.
In this way it is guaranteed that after a =1 event,
the die−temperature decreases back to the level of .
After reaching temperature of thermal warning Ttw, motor
current is automatically decreased to unboosted level.
Note (*): During the situation the motor is not
disabled while the ERRB is pulled down. To be informed
about other error situations it is recommended to poll the
status registers on a regular base (time base driven
by application software in the millisecond domain).
When Open coil condition is detected, the appropriate bit
( or ) together with bit in
the SPI status register are set. Reaction of the H−bridge to
Open coil condition depends on the settings of
and bits.
When both and bits are 0,
bit stays in 1 and only H−bridge where open coil
is detected is disabled. When bit is set, both
H−bridges are disabled (=0) in case of Open coil
detection. When bit is set, drivers remain active
for both coils independently of bit.
The short circuit detection monitors the load current in
each activated output stage. The current is measured in terms
of voltage drop over the MOSFETS’ RDS(ON). If the load
current exceeds the over−current detection threshold, the
appropriate over−current flag together with
bit are set and the drivers are switched off
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17
NCV70517
Error Output
Notes:
• The hard−reset function is disabled in sleep mode.
• The CSB low pulse width has to be within tcsb_with,
(see Table 7 − AC Parameters) to guarantee a correct
wake−up.
This is an open drain output to flag a problem to the
external microcontroller. The signal on this output is active
low and the logic combination of:
NOT(ERRB) = ( OR OR OR
OR OR (BemfIntEn AND BemfRes) OR
OR (*)reset state) AND not (**)sleep mode
Note (*) reset state: After a power−on or a hard−reset, the
ERRB is pulled low during thr_err (Table 7 − AC
Parameters).
Note (**) sleep mode: In sleep mode the ERRB is always
inactive (high).
Power−on Reset, Hard−Reset Function
After a power−on or a hard−reset, a flag in the SPI
status register is set and the ERRB is pulled low. The ERRB
stays low during this reset state. The typical power−on reset
time is given by thr_err (Table 7 − AC Parameters). After the
reset state the device enters sleep mode and the ERRB pin
goes high to indicate the motor controller is ready for
operation.
By means of a specific pattern on the DIR pin and NXT
pin, the complete digital part of driver can be reset without
a power−cycle. This hard−reset function is activated when
the input pin DIR changes logic state “0 → 1 → 0 → 1” in
five consecutive patterns during NXT pin being at high
level. See figure below and Table 7 − AC Parameters.
The operation of all analog circuits is suspended during
the reset state of the digital. Similar as for a normal
power−on, the flag is set in the SPI register after a
hard−reset and the ERRB pin is pulled low during thr_err
(Table 7 − AC Parameters).
Sleep Mode
The motor driver can be put in a low−power consumption
mode (sleep mode). The sleep mode is entered automatically
after a power−on or hard reset and can also be activated by
means of SPI bit . In sleep−mode, all analog circuits
are suspended in low−power, logic output pin ERRB is
disabled (ERRB has no function) and none of the input pins
is functional with the exception of pin CSB. Only CSB pin
can wake−up the chip to normal mode (i.e. clear bit )
by means of a low pulse with a specified width within
tcsb_with time. Time twu (see Table 7 − AC Parameters) is
needed to restore all analog and digital circuits
after wake−up.
thr_trig
DIR
thr_set
thr_dir
NXT
thr_err
ERRB
Figure 15. Hard Reset Timing Diagram
SPI INTERFACE
and sampling of the information on the two serial data lines:
DO and DI. The DO signal is the output from the Slave
(NCV70517), and the DI signal is the output from the
Master.
A slave or chip select line (CSB) allows individual
selection of a slave SPI device in a time multiplexed
multiple−slave system.
The CSB line is active low. If an NCV70517 is not
selected, DO is in high impedance state and it does not
interfere with SPI bus activities. Since the NCV70517
always clocks data out on the falling edge and samples data
General
The serial peripheral interface (SPI) is used to allow
an external microcontroller (MCU) to communicate
with the device. NCV70517 acts always as a slave and it
cannot initiate any transmission. The operation of the device
is configured and controlled by means of SPI registers,
which are observable for read and/or write from the master.
The NCV70517 SPI transfer size is 16 bits.
During an SPI transfer, the data is simultaneously
transmitted (shifted out serially) and received (shifted in
serially). A serial clock line (CLK) synchronizes shifting
www.onsemi.com
18
NCV70517
in on rising edge of clock, the MCU SPI port must be
configured to match this operation.
The implemented SPI allows connection to multiple
slaves by means of star connection (CSB per slave) or by
means of daisy chain.
An SPI star connection requires a bus = (3 + N) total lines,
where N is the number of Slaves used, the SPI frame length
is 16 bits per communication.
NCV70517 dev#1
(SPI Slave )
MCU
(SPI Master )
CSB1
CSB2
MCU
(SPI Master )
CSBN
MOSI
MISO
NCV70517 dev#1
(SPI Slave )
SDO1
SDI2
NCV70517 dev#2
(SPI Slave )
NCV70517 dev#2
(SPI Slave )
SDO2
SDIN
NCV70517 dev#N
(SPI Slave )
NCV70517 dev#N
(SPI Slave )
SDON
Figure 16. SPI Star vs. Daisy Chain Connection
SPI Daisy chain mode
SPI Transfer Format
SPI daisy chain connection bus width is always four lines
independently on the number of slaves. However, the SPI
transfer frame length will be a multiple of the base frame
length so N x 16 bits per communication: the data will be
interpreted and read in by the devices at the moment the CSB
rises.
A diagram showing the data transfer between devices in
daisy chain connection is given further: CMDx represents
the 16−bit command frame on the data input line transmitted
by the Master, shifting via the chips’ shift registers through
the daisy chain. The chips interpret the command once the
chip select line rises.
Two types of SPI commands (to DI pin of NCV70517)
from the micro controller can be distinguished: “Write to a
control register” and “Read from register (control or
status)”.
The frame protocol for the write operation:
Write; CMD = ‘1’
High
Low
C
A A A A
D D D D D D D D D D
M
P
3 2 1 0
9 8 7 6 5 4 3 2 1 0
D
DI
DO
CLK
P
=
S
P
I
E
R
R
C
A A A A D D D D D D D D D D
M
3 2 1 0 9 8 7 6 5 4 3 2 1 0
D
S
P
I
E
R
R
C
A A A A A
M
0 1 1 1 0
P
4 3 2 1 0
D
U
V
E
L
D
E
F
T
S
D
T
W
Low
Previous SPI WRITE command
resp. “SPIERR + 0x000hex”
after POR or SPI Command
HIGH−Z PARITY/FRAMING Error
Previous SPI READ command
& NCV70516 status bits resp.
“SPIERR + 0x000hex” after
POR or SPI Command
PARITY/FRAMING Error
Low
not(CMD xor A3 xor A2 xor A1 xor A0 xor D9 xor D8 xor D7 xor
D6 xor D5 xor D4 xor D3 xor D2 xor D1 xor D0)
Figure 18. SPI Write Frame
Referring to the previous picture, the write frame coming
from the master (into the DI) is composed from the
following fields:
• Bit[15] (MSB): CMD bit = 1 for write operation,
• Bits[14:11]: 4 bits WRITE ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
• Bits[9:0]: 10 bit DATA to write
Figure 17. SPI Daisy Chain Data Shift Between
Slaves. The symbol ‘x’ represents the previous
content of the SPI shift register buffer.
The NCV70517 default power up communication mode
is “star”. In order to enable daisy chain mode, a multiple of
16 bits clock cycles must be sent to the devices, while the
SDI line is left to zero.
Note: to come back to star mode the NOP register (address
0x0000) must be written with all ones, with the proper data
parity bit and parity framing bit: see SPI protocol for details
about parity and write operation.
Device in the same time replies to the master (on the DO):
• If the previous command was a write and no SPI error
•
had occurred, a copy of the command, address and data
written fields,
If the previous command was a read, the response
frame summarizes the address used and an overall
www.onsemi.com
19
NCV70517
•
diagnostic check (copy of the main detected errors, see
Figure 18 and Figure 19 for details),
In case of previous SPI error or after power−on−reset,
only the MSB bit will be 1, followed by zeros.
Referring to the previous picture, the read frame coming
from the master (into the DI) is composed from the
following fields:
• Bit[15] (MSB): CMD bit = 0 for read operation,
• Bits[14:10]: 5 bits READ ADDRESS field,
• Bit[10]: frame parity bit. It is ODD parity formed by
the negated XOR of all other bits in the frame,
• Bits [8:0]: 9 bits zeroes field.
If parity bit in the frame is wrong, device will not perform
command and flag will be set.
The frame protocol for the read operation:
Read ; CMD = ‘0’
Device in the same frame provides to the master (on the DO)
data from the required address (in frame response), thus
achieving the lowest communication latency.
High
TW, TSD, ELDEF , UV:
immediate value of STATUS BITS ;
dedicated SPI READ Command of STATUS
Register has to be performed to clear
the value of read −by−clear STATUS bits
Low
C
A A A A A
P
M
4 3 2 1 0
D
DI
S
P
I
E
R
R
DO
0
U
V
E
L
D
E
F
T
S
D
T
W
D D D D D D D D D D
9 8 7 6 5 4 3 2 1 0
=
SPI communication framing error is detected by the
NCV70517 in the following situations:
• Not an integer multiple of 16 CLK pulses are received
during the active−low CSB signal;
• LSB bits (8..0) of a read command are not all zero;
• SPI parity errors, either on write or read operation.
Data from address A [4:0]
shall be returned
HIGH −Z
CLK
P
SPI Framing and Parity Error
Low
Low
Low
not(CMD xor A 4 xor A 3 xor A 2 xor A 1 xor A 0)
Once an SPI error occurs, the flag can be reset only
by reading the status register in which it is contained (using
in the read frame the right communication parity bit). This
request will reset the SPI error bit and release the ERRB pin
(high).
Figure 19. SPI Read Frame
SPI Control Registers (CR)
All SPI control registers have Read/Write access.
Table 13. SPI CONTROL REGISTERS (CR)
5−bit
Address
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
after Res.
00h
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
00 0000
0000
01h (CR1)
NXTfilter
NXTP
MOTEN
DIRP
IBOOST
ACTBR
IMOT3
IMOT2
IMOT1
IMOT0
00 0000
0000
02h (CR2)
−
PWMJen
OpenDet1
OpenDet0
OpenDis
OpenHiZ
SLP
SM2
SM1
SM0
00 1000
1000
03h (CR3)
UVact
UVtime1
UVtime0
BemfIntEn
EnhBemfEn
BemfGain
StThr3
StThr2
StThr1
StThr0
00 0000
0000
04h (CR4)
−
−
−
−
MSP5
MSP4
MSP3
MSP2
MSP1
MSP0
00 0000
1000
0Bh (CR5)
EMC1
EMC0
StTo7
StTo6
StTo5
StTo4
StTo3
StTo2
StTo1
StTo0
01 0001
0000
0Ch (CR6)
−
−
SpThr7
SpThr6
SpThr5
SpThr4
SpThr3
SpThr2
SpThr1
SpThr0
00 0000
0000
Table 14. BIT DEFINITION
Symbol
MAP position
NOP
Bits [9:0] – ADDR_0x00
NXTfilter
Bit 9 – ADDR_0x01 (CR1)
Filters out pulses coming from the NXT pin when the motor (H−bridge) is disabled
NXTP
Bit 8 – ADDR_0x01 (CR1)
Push button pin, generating next step in position table
MOTEN
Bit 7 – ADDR_0x01 (CR1)
Enables the H−bridges (motor activated)
DIRP
Bit 6 – ADDR_0x01 (CR1)
Polarity of DIR pin, which controls direction status; DIRP = 1 inverts the logic
polarity of the DIR pin)
IBOOST
Bit 5 – ADDR_0x01 (CR1)
Current boost function activation and status
ACTBR
Bit 4 – ADDR_0x01 (CR1)
Active break
Description
NOP register (read/write operation ignored)
www.onsemi.com
20
NCV70517
Table 14. BIT DEFINITION (continued)
IMOT[3:0]
Bits [3:0] – ADDR_0x01 (CR1)
Current amplitude
PWMJen
Bit 8 – ADDR_0x02 (CR2)
OpenDet[1:0]
Bits [7:6] – ADDR_0x02 (CR2)
Enable PWM jittering function to spread spectrum of PWM modulation
OpenDis
Bit 5 – ADDR_0x02 (CR2)
When bit is set, Open Coil detection status is flagged, but drivers control remain
active for both coils, bit setting has higher priority than bit
OpenHiZ
Bit 4 – ADDR_0x02 (CR2)
When bit is set, during Open Coil detection both drivers are deactivated
(MOTEN=0)
Places device in sleep mode with low current consumption (when 1)
Open Coil detection time setting bits (see Table 7 − AC Parameters)
SLP
Bit 3 – ADDR_0x02 (CR2)
SM[2:0]
Bits [2:0] – ADDR_0x02 (CR2)
UVact
Bit 9 – ADDR_0x03 (CR3)
UVtime[1:0]
Bits [8:7] – ADDR_0x03 (CR3)
BemfIntEn
Bit 6 – ADDR_0x03 (CR3)
BEMF result interrupt enable
EnhBemfEn
Bit 5 – ADDR_0x03 (CR3)
Enhanced BEMF measurement functionality is activated when bit is set
BemfGain
Bit 4 – ADDR_0x03 (CR3)
Gain of BEMF measurement channel = “0”: gain 0.5, “1”: gain 0.25
StThr[3:0]
Bits [3:0] – ADDR_0x03 (CR3)
Threshold level for stall detection, when “0”, stall detection is disabled
MSP[5:0]
Bit [5:0] – ADDR_0x04 (CR4)
Setting or status of translator micro−step position
EMC[1:0]
Bits [9:8] – ADDR_0x0B (CR5)
Voltage slope defining bits for motor driver switching (see Table 7 − AC Parameters)
StTo[7:0]
Bits [7:0] – ADDR_0x0B (CR5)
tall time−out. Max difference between two successive full step next pulse periods
(time−out), after this time the BEMF sample is taken to verify stall
SpThr[7:0]
Bits [7:0] – ADDR_0x0C (CR6)
Speed threshold register, BEMF measurement and stall detection is activated
when Speed register value is less than or equal to value
Step mode selection
“0”: H bridge left open upon under voltage detection;
“1”: H bridge motor brake (shorted to GND), when undervoltage is detected
Under−voltage filter (debounce) time (see Table 7 − AC Parameters)
SPI Status Registers (SR)
All SPI status registers have Read Only Access, with the odd parity on Bit8. Parity bit makes the numbers of 1 in the byte
odd.
Table 15. SPI STATUS REGISTERS (SR)
5−bit
Address
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h (SR1)
0x0
PAR
SL,L
HR,L
ELDEF,R*
TAMB,R
UVW,L
TW,R
UV,L
Stall,L
06h (SR2)
0x0
PAR
0x0
SPI,L
TSD,L
07h (SR3)
0x0
PAR
0x0
08h (SR4)
0x0
PAR
DEVID4
DEVID3
DEVID2
DEVID1
DEVID0
REVID2
REVID1
REVID0
09h (SR5)
0x0
PAR
Bemf
−Res,L
Bemf
−Coil,R
Bemfs,R
Bemf4, R
Bemf3, R
Bemf2, R
Bemf1, R
Bemf0, R
0Ah (SR6)
0x0
PAR
Sp7,R
Sp6,R
Sp5,R
Sp4,R
Sp3,R
Sp2,R
Sp1,R
Sp0,R
NXTpin, R DIRpin, R
Default
after
Res.
OPENX,L SHRTXPB,L SHRTXNB,L SHRTXPT,L SHRTXNT,L
OPENY,L SHRTYPB,L SHRTYNB,L SHRTYPT,L SHRTYNT,L
Flags have “,L” for latched information or “,R” for real time information. All latched flags are “cleared upon read”.
X = value after reset is defined during reset phase (diagnostics)
R* = real time read out of values of other latches. Reading out this R* value does not reset the bit, and does not reset the values of the
latches this bit reads out.
www.onsemi.com
21
NCV70517
Table 16. BIT DEFINITION
Symbol
MAP Position
Description
PAR
Bit 8 – ADDR_0x05 (SR1)
Parity bit for SR1
SL
Bit 7 – ADDR_0x05 (SR1)
Step loss register
HR
Bit 6 − ADDR_0x06 (SR2)
Hard reset flag: 1 indicates a hard reset has occurred
ELDEF
Bit 5 – ADDR_0x05 (SR1)
Eletrical defect: Short circuit was detected (at least one of the SHORTij
individual bits is set) or Open Coil X or Y was detected
TAMB
Bit 4 – ADDR_0x05 (SR1)
Temperature below Tlow level − Iboost function can be activated
UVW
Bit 3 – ADDR_0x06 (SR2)
Under−voltage warning – UV threshold hit
TW
Bit 2 – ADDR_0x05 (SR1)
Thermal warning
UV
Bit 1 – ADDR_0x05 (SR1)
Under voltage detection – action taken according to UVact bit
Stall
Bit 0 – ADDR_0x05 (SR1)
Stall detected by the internal algorithm
PAR
Bit 8 – ADDR_0x06 (SR2)
Parity bit for SR2
SPI
Bit 6 – ADDR_0x05 (SR1)
SPI error: no multiple of 16 rising clock edges between falling and rising
edge of CSB line
TSD
Bit 5 – ADDR_0x05 (SR1)
Thermal shutdown
OPENX
Bit 4 – ADDR_0x06 (SR2)
Open Coil X detected
SHRTXPB
Bit 3 – ADDR_0x06 (SR2)
Short circuit detected at XP pin towards ground (Bottom)
SHRTXNB
Bit 2 – ADDR_0x06 (SR2)
Short circuit detected at XN pin towards ground (Bottom)
SHRTXPT
Bit 1 – ADDR_0x06 (SR2)
Short circuit detected at XP pin towards supply (Top)
SHRTXNT
Bit 0 – ADDR_0x06 (SR2)
Short circuit detected at XN pin towards supply (Top)
PAR
Bit 8 – ADDR_0x07 (SR3)
Parity bit for SR3
NXTpin
Bit 6 – ADDR_0x07 (SR3)
Read out of NXT pin logic status
DIRpin
Bit 5 – ADDR_0x07 (SR3)
Read out of DIR pin logic status
OPENY
Bit 4 – ADDR_0x07 (SR3)
Open Coil Y detected
SHRTYPB
Bit 3 – ADDR_0x07 (SR3)
Short circuit detected at YP pin towards ground (Bottom)
SHRTYNB
Bit 2 – ADDR_0x07 (SR3)
Short circuit detected at YN pin towards ground (Bottom)
SHRTYPT
Bit 1 – ADDR_0x07 (SR3)
Short circuit detected at YP pin towards supply (Top)
SHRTYNT
Bit 0 – ADDR_0x07 (SR3)
Short circuit detected at YN pin towards supply (Top)
Parity bit for SR4
PAR
Bit 8 – ADDR_0x08 (SR4)
DEVID[4:0]
Bits [7:3] – ADDR_0x08 (SR4)
Device ID
REVID[2:0]
Bits [2:0] – ADDR_0x08 (SR4)
Revision ID
PAR
Bit 8 – ADDR_0x09 (SR5)
Parity bit for SR5
BemfRes
Bit 7 – ADDR_0x09 (SR5)
BEMF result ready at register
BemfCoil
Bit 6 – ADDR_0x09 (SR5)
Last BEMF measurement was done on coil: 0 = X, 1 = Y
BEMF measured voltage has expected polarity (Yes = 0, No = 1)
Bemfs
Bit 5 – ADDR_0x09 (SR5)
Bemf[4:0]
Bits [4:0] – ADDR_0x09 (SR5)
BEMF value measured during zero crossing
Sp[7:0]
Bits [7:0] – ADDR_0x0A (SR6)
Speed register
DEVID [4:0] for NCV70517 device is (17)dec.
REVID [2:0] for N70517−2 device is (3)dec.
www.onsemi.com
22
NCV70517
APPLICATION EXAMPLES FOR MULTI−AXIS CONTROL
The wiring diagrams below show possible connection of
multiple slaves to one microcontroller. In these examples,
all movements of the motors are synchronized by means of
a common NXT wire. The direction and Run/Hold
activation is controlled by means of an SPI bus.
Further I/O reduction is accomplished in case the ERRB
is not connected. This would mean that the microcontroller
operates while polling the error flags of the slaves.
Ultimately, one can operate multiple slaves by means of only
4 SPI connections: even the NXT pin can be avoided if the
microcontroller operates the motors by means of the
“NXTP” bit.
Microcontroller
IC1 NCV70517
NXT
CSB1
DI/DO/CLK
ERRB
NXT
CSB
3
DI/DO/CLK
ERRB
3
IC2 NCV70517
NXT
CSB2
CSB
DI/DO/CLK
ERRB
“Multiplexed SPI”
3
IC3 NCV70517
NXT
CSB3
CSB
DI/DO/CLK
ERRB
Rpu
vcc
Figure 20. Examples of Wiring Diagrams for Multi−axis Control
ELECTRO MAGNETIC COMPATIBILITY
Special care has to be taken into account with long wiring
to motors and inductors. A modern methodology to regulate
the current in inductors and motor windings is based on
controlling the motor voltage by PWM. This low frequency
switching of the battery voltage is present at the wiring
towards the motor or windings. To reduce possible radiated
transmission, it is advised to use twisted pair cable and/or
shielded cable.
The NCV70517 has been developed using
state−of−the−art design techniques for EMC. The overall
system performance depends on multiple aspects of the
system (IC design & lay−out, PCB design and layout …..)
of which some are not solely under control of the IC
manufacturer. Therefore, meeting system EMC
requirements can only happen in collaboration with all
involved parties.
ORDERING INFORMATION
Device
Peak Current
End Market/Version
Package*
Shipping†
NCV70517MW002R2G
800/1100 mA
(Note 27)
Automotive
High Temperature
Version
QFNW32 5x5 with step−cut
wettable flank (Pb−Free)
5000 / Tape & Reel
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
27. The device boost current. This applies for operation under the thermal warning level only.
www.onsemi.com
23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFNW32 5x5, 0.5P
CASE 484AB
ISSUE D
DATE 07 SEP 2018
1 32
SCALE 2:1
L3
A
B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
L3
L4
L4
PIN ONE
REFERENCE
L
L
ALTERNATE
CONSTRUCTION
DETAIL A
E
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
EXPOSED
COPPER
DIM
A
A1
A3
A4
b
D
D2
E
E2
e
K
L
L3
L4
A4
A1
TOP VIEW
A
DETAIL B
0.10 C
ALTERNATE
CONSTRUCTION
DETAIL B
(A3)
C
C
0.08 C
L3
A4
C
SIDE VIEW
NOTE 4
PLATED
SURFACES
D2
9
SECTION C−C
17
8
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
E2
1
32
25
32X
e
e/2
BOTTOM VIEW
b
0.10
M
C A B
0.05
M
C
XXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
5.30
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
32X
0.63
3.35
1
3.35
PACKAGE
OUTLINE
GENERIC
MARKING DIAGRAM*
1
L
K
A3
SEATING
PLANE
DETAIL A
32X
PLATING
A1
A4
MILLIMETERS
MIN
NOM
MAX
0.80
0.90
1.00
−−−
−−−
0.05
0.20 REF
0.10
−−−
−−−
0.20
0.25
0.30
4.90
5.00
5.10
3.00
3.10
3.20
4.90
5.00
5.10
3.00
3.10
3.20
0.50 BSC
0.35
−−−
−−−
0.30
0.40
0.50
−−−
−−−
0.10
0.08 REF
5.30
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON14940G
QFNW32 5x5, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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