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NCV7428
System Basis Chip with
Integrated LIN and Voltage
Regulator
Description
NCV7428 is a System Basis Chip (SBC) integrating functions
typically found in automotive Electronic Control Units (ECUs).
NCV7428 provides and monitors the low−voltage power supply for
the application microcontroller and other loads and includes a LIN
transceiver.
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8
1
Features
• Control Logic
♦
•
•
•
•
Quality
• NCV Prefix for Automotive and Other Applications Requiring
•
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
November, 2018 − Rev. 7
MARKING DIAGRAMS
8
1
NV7428xx
ALYW G
G
NV7428xx
ALYWG
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
1
8
2
7
VS
EN
VOUT
3
GND
5
4
LIN
RSTN
6
TxD
RxD
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 17 of this data sheet.
• Automotive
• Industrial Networks
© Semiconductor Components Industries, LLC, 2016
DFN8
MW SUFFIX
CASE 506DG
NCV7428
Ensures safe power−up sequence and the correct reaction to
different supply conditions
♦ Controls mode transitions including the power management and
bus wakeup treatment
♦ Generates reset
3.3 V or 5 V VOUT Supply depending on the Version from a
Low−drop Voltage Regulator
♦ Can deliver up to 70 mA with accuracy of ±2%
♦ Supplies typically the ECU’s microcontroller
♦ Undervoltage detector with a reset output to the supplied
microcontroller
LIN Transceiver
♦ LIN2.x and J2602 compliant
♦ TxD dominant timeout protection
♦ Transceiver mode controlled by dedicated input pin
Protection and Monitoring Functions
♦ Thermal shutdown protection
♦ Load dump protection (45 V)
♦ LIN Bus pin protected against transients in an automotive
environment
♦ ESD protection level for LIN and VS > ±8 kV
Wettable Flank Package for Enhanced Optical Inspection
1
SOIC−8
D SUFFIX
CASE 751AZ
1
Publication Order Number:
NCV7428/D
NCV7428
Block Diagram
VOUT
VS
NCV7428
REF
V−reg
OSC
VOUT
VS
VOUT
Undervoltage
Detection
RSTN
Thermal
Shutdown
Control Logic
VS
EN
Wakeup
Detection
VOUT
LIN Wakeup
RxD
Receiver
LIN Active
LIN
VOUT
TxD
Driver &
Slope
Control
Timeout
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
Pin Type
Pin Function
1
VS
Battery supply input
Principle power supply of the device
2
EN
LV LIN enable input;
internal pull−down
Input of the LIN block enable signal
3
GND
Ground connection
Ground connection
4
LIN
LIN bus interface
LIN bus line
5
RxD
LV digital output; push−pull
Output of data received on LIN bus
6
TxD
LV digital input; internal pull−up
Input of the data to be transmitted from LIN bus
7
RSTN
LV digital output;
open drain; internal pull−up
System reset
8
VOUT
LV supply output
Output of the 5 V or 3.3 V/70 mA low−drop regulator (for the MCU)
EP
EP
Exposed Pad
Connect to GND or leave floating
NOTE:
(LV = Low Voltage; HV = High Voltage)
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NCV7428
Application Information
ECU1 (MASTER)
CVOUT
VBAT
LIN
LIN
CLIN_M
CVOUT
VCC
VS
VOUT
NCV7428
RPU_LIN
CVS
RSTN
EN
MCU
TxD
LIN
RxD
LIN
CLIN_S
GND
GND
VCC
VOUT
NCV7428
VS
DPU_LIN
ECU2 (SLAVE)
DREV
RPU_RSTN
CVS
RPU_RSTN
VBAT
DREV
RSTN
EN
TxD
MCU
RxD
GND
GND
GND
GND
KL30
LIN−BUS
KL31
Figure 2. Example Application Diagram
External Components
Overview of external components from application schematic in Figure 2 is given in Table 2 together with their recommended
or required values.
Table 2. EXTERNAL COMPONENTS OVERVIEW
Component
Name
Description
Value
Note
required values and types
depend on the VOUT load
and the application needs
DREV
Reverse polarity protection diode
parameters application−specific;
e.g. 0.5 A / 50 V
CVS
Filtering capacitor for the battery input
recommended >100 nF ceramic
CVOUT
Voltage regulator output filtering and
stabilization capacitor
> 1.8 mF, ESR < 7 W
DPU_LIN
Master node Pull−up diode on LIN line
RPU_LIN
Master node Pull−up resistor on LIN line
1 kW nominal, ≥500 mW
CLIN_M
Filtering capacitor on LIN line (Master node)
typically 1 nF
optional; is function of the
entire LIN network
CLIN_S
Filtering capacitor on LIN line (Slave node)
typically 100 pF – 220 pF
optional; is function of the
entire LIN network
RPU_RSTN
Pull−up resistor at RSTN pin
recommended 10 kW nominal
optional; depends on
application needs
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3
required only for master
LIN node
NCV7428
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VS
Maximum DC voltage at VS pin
−0.3
45
V
VOUT
Maximum voltage at VOUT pin
−0.3
6
V
VLIN
Maximum voltage at LIN bus pin
−45
45
V
VDig_IO_inputs
Maximum voltage at digital input pins (TxD, EN)
−0.3
45
V
VDig_IO_outputs
Maximum voltage at digital output pins (RxD, RSTN)
−0.3
VOUT+0.3
V
TAMB
Ambient temperature range
−40
+125
°C
TJ
Junction temperature range
−40
+170
°C
TSTG
Storage temperature range
−55
+150
°C
VESD
System ESD at pins VS, LIN as per IEC 61000−4−2: 330 W / 150 pF
(Verified by external test house)
≥ ±14
kV
Human body model at pins VS, LIN stressed towards GND with 1500 W / 100 pF
≥ ±8
kV
Human body model at all pins as per JESD22−A114 / AEC−Q100−002
≥ ±4
kV
≥ ±500
V
±200
V
2
1
−
260
°C
Charge device model at all pins as per JESD22−C101 / AEC−Q100−011
Machine model; (200 pF; 0.75 mH; 10 W) as per JESD22−A115 / AEC−Q100−003
MSL
Moisture Sensitivity Level
SOIC
DFN
TSLD
Lead temperature Soldering − Reflow (SMD styles only), Pb−Free (Note 1)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. OPERATING RANGES
Symbol
VS
Parameter
VS operating voltage for parametric operation (Note 2)
VS operating voltage for limited operation (Note 2)
VOUT5
Regulated voltage at VOUT supply output for 5 V versions
VOUT33
Regulated voltage at VOUT supply output for 3.3 V versions
Min
Max
Units
5.5
28
V
4
28
V
4.9
5.1
V
3.234
3.366
V
IVOUT
Current delivered by the VOUT regulator
70
mA
VLIN
Operating voltage at LIN bus pin
0
VS
V
VDig_IO_inputs
Operating voltage at digital input pins (TxD, EN)
0
5.5
V
VDig_IO_outputs
Operating voltage at digital output pins (RxD, RSTN)
0
VOUT
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Below 5.5 V at VS pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time
specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 28 V at VS pin, LIN communication is
operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 28 V, LIN pull−up resistor
must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.
Table 5. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOIC−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
RqJA
RqJA
125
75
°C/W
°C/W
Thermal Characteristics, DFN−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
RqJA
RqJA
133
55
°C/W
°C/W
3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
4. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
5. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.
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NCV7428
Definitions
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 4, unless stated
otherwise. All voltages are referenced to GND (Pin 3). Positive currents flow into the respective pin.
Table 6. DC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise
specified. Typical values are given at VS = 12 V and TJ = 25°C, unless otherwise specified.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY MONITORING
VS_PORH
VS threshold for the power−up
of the circuit
VS rising
3.3
4
V
VS_PORL
VS threshold for the Shutdown
of the circuit
VS falling
2.2
3
V
VOUT_RES_5
VOUT monitoring threshold
NV7428−5
VOUT falling
4.55
4.75
V
VOUT_RES_33
VOUT monitoring threshold
NV7428−3
VOUT falling
2.97
3.135
V
VOUT_RES_hys5
VOUT monitoring threshold
hysteresis for NV7428−5
0.1
V
VOUT_RES_hys33
VOUT monitoring threshold
hysteresis for NV7428−3
0.06
V
CURRENT CONSUMPTION
IVS_LIN_Active_rec
VS supply current
LIN Active, LIN bus recessive
1.8
mA
IVS_LIN_Wakeup
VS supply current (Note 8)
Standby mode; LIN Wakeup,
LIN bus recessive; IVOUT = 0 mA
VS = 13.5 V, TJ < 105°C
25
33
mA
IVS_Sleep
VS supply current (Note 8)
Sleep mode; LIN Wakeup, LIN bus
recessive; VOUT off, VOUT < 0.5 V
VS = 13.5 V, TJ < 105°C
12
18
mA
VOUT REGULATOR
VOUT_5
VOUT regulator output voltage
(Note 6)
VOUT regulator active,
0 < IVOUT < 70 mA, Static
regulation, VS = 5.5 V to 28 V
4.9
5
5.1
V
VOUT_33
VOUT regulator output voltage
(Note 6)
VOUT regulator active,
0 < IVOUT < 70 mA, Static
regulation, VS = 4.5 V to 28 V
3.234
3.3
3.366
V
VOUT_5_EMC
VOUT regulator output voltage
under EMC (Note 8)
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
4.85
5
5.15
V
VOUT_33_EMC
VOUT regulator output voltage
under EMC (Note 8)
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
3.201
3.3
3.399
V
VOUT current limitation
VOUT regulator active;
current flowing to VOUT load
70
120
350
mA
Drop−out voltage between VS
and VOUT
5.5 V < VS < 40 V;
IVOUT = 70 mA
0.55
V
VOUT sink current
VOUT regulator active, current
flowing into the VOUT pin
100
240
400
mA
VOUT regulator filtering
capacitance (Note 9)
Equivalent series resistance < 7 W
1.8
10
ILIM_VOUT
VDROP_VOUT
ISINK_VOUT
CVOUT
mF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used VOUT_5_EMC and VOUT_33_EMC needs to be taken into account.
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10. The voltage drop in Normal mode between LIN and VS pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
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NCV7428
Table 6. DC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise
specified. Typical values are given at VS = 12 V and TJ = 25°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1.2
V
2.0
V
VS
V
LIN TRANSMITTER
VLIN_dom_LoSup
LIN dominant output voltage
TxD = Low; VS = 7.3 V
VLIN_dom_HiSup
LIN dominant output voltage
TxD = Low; VS = 18 V
VLIN_REC
LIN recessive output voltage
TxD = High; ILIN = 10 mA (Note 10)
ILIN_lim
Short circuit current limitation
VLIN = VS = 18 V
40
Rslave
Internal Pull−up Resistance
LIN Normal or Receive−only mode
20
CLIN
VS – 1.5
Capacitance at pin LIN (Note 8)
200
mA
33
47
kW
20
30
pF
0.4
VS
LIN Receiver
Vbus_dom
Bus voltage for Dominant state
Vbus_rec
Bus voltage for Recessive state
Vrec_dom
Receiver threshold
LIN bus going from Recessive to
Dominant
0.6
0.4
0.6
VS
Vrec_rec
Receiver threshold
LIN bus going from Dominant to
Recessive
0.4
0.6
VS
Vrec_cnt
Receiver center voltage
(Vrec_dom + Vrec_rec)/2
0.475
0.525
VS
Vrec_hys
0.05
0.175
Receiver hysteresis
Vrec_rec − Vrec_dom
ILIN_off_dom
LIN output current,
Bus in dominant state
LIN Active Mode, Driver Off;
VS = 12 V, VLIN = 0 V
−1
ILIN_off_dom_wake
LIN output current,
Bus in dominant state
LIN Wakeup Mode;
VS = 12 V, VLIN = 0 V
−20
ILIN_off_rec
LIN output current,
Bus in recessive state
Driver Off; VS < 18 V;
VS < VLIN < 18 V
ILIN_no_GND
LIN current with missing GND
VS = GND = 12 V; 0 < VLIN < 18 V
ILIN_no_VBB
LIN current with missing VS
VS = GND = 0 V; 0 < VLIN < 18 V
VS
VS
mA
−15
−1
−2
mA
1
mA
1
mA
5
mA
0.8
V
PIN EN
VIL_EN
Low−level input voltage
VIH_EN
High−level input voltage
2
Pull−down resistance to GND
55
Rpulldown_EN
−0.3
100
5.5
V
185
kW
PIN TxD
VIL_TxD
Low−level input voltage
−0.3
0.8
V
VIH_TxD
High−level input voltage
2
5.5
V
Rpullup_TxD
55
100
185
kW
Leakage current
VTxD = VOUT = 5.5 V
−1
0
1
mA
IOL_RSTN
Low−level output driving current
VS = 4 V to 28 V; VRSTN = 0.4 V
4
30
mA
VOL_RSTN
Low−level output voltage
VS = 2 V to 4 V; VOUT = 0 V to
5.5 V; IRSTN = 100 mA
0.1
VOUT
VS < 2 V; VOUT = 1 V to 5.5 V;
IRSTN = 100 mA
0.1
VOUT
185
kW
Ileak_TxD
Pull−up resistance to VOUT
PIN RSTN
Rpullup_RSTN
Pull−up resistance to VOUT
55
100
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used VOUT_5_EMC and VOUT_33_EMC needs to be taken into account.
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10. The voltage drop in Normal mode between LIN and VS pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
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NCV7428
Table 6. DC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; Bus Load = 500 W (VS to LIN); unless otherwise
specified. Typical values are given at VS = 12 V and TJ = 25°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2
V
PIN RSTN
VS level guaranteeing Low level
at RSTN pin
Shutdown mode; Low level guaranteed for VS > VS_DigOut_Low
IOL_RXD
Low−level output driving current
VRxD = 0.4 V
IOH_RXD
High−level output driving current
VRXD = VOUT − 0.4 V
VS_DigOut_Low
PIN RxD
0.4
mA
−0.16
mA
200
°C
THERMAL SHUTDOWN
TJ_SD
Junction temperature for thermal Shutdown
TJ_SD_hys
Thermal Shutdown hysteresis
160
180
10
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used VOUT_5_EMC and VOUT_33_EMC needs to be taken into account.
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10th, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10. The voltage drop in Normal mode between LIN and VS pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
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NCV7428
Table 7. AC CHARACTERISTICS (VS = 5.5 V to 28 V; TJ = −40°C to +150°C; unless otherwise specified. For the transmitter
parameters, the following bus loads are considered: L1 = 1 kW / 1 nF; L2 = 660 W / 6.8 nF; L3 = 500 W / 10 nF)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LIN TRANSMITTER
D1
Duty Cycle 1 =
tBUS_REC(min) / (2 x tBIT)
THREC(max) = 0.744 x VS
THDOM(max) = 0.581 x VS
tBIT = 50 ms
VS = 7 V to 18 V
0.396
0.5
D2
Duty Cycle 2 =
tBUS_REC(max) / (2 x tBIT)
THREC(min) = 0.422 x VS
THDOM(min) = 0.284 x VS
tBIT = 50 ms
VS = 7.6 V to 18 V
0.5
0.581
D3
Duty Cycle 3 =
tBUS_REC(min) / (2 x tBIT)
THREC(max) = 0.778 x VS
THDOM(max) = 0.616 x VS
tBIT = 96 ms
VS = 7 V to 18 V
0.417
0.5
D4
Duty Cycle 4 =
tBUS_REC(max) / (2 x tBIT)
THREC(min) = 0.389 x VS
THDOM(min) = 0.251 x VS
tBIT = 96 ms
VS = 7.6 V to 18 V
0.5
0.590
tfallNS
LIN falling edge normal slope
Normal Mode; VS = 12 V
22.5
ms
triseNS
LIN rising edge normal slope
Normal Mode; VS = 12 V
22.5
ms
tsymNS
LIN slope symmetry normal slope
Normal Mode; VS = 12 V
4
ms
tfallLS
LIN falling edge low slope (Note 12)
Normal Mode; VS = 12 V
45
ms
triseLS
LIN rising edge low slope (Note 12)
Normal Mode; VS = 12 V
45
ms
ttx_prop_down
Propagation Delay of TxD to LIN.
TxD high to low
(Note 11)
10
ms
ttx_prop_up
Propagation Delay of TxD to LIN.
TxD low to high
(Note 11)
10
ms
tTxD_timeout
TxD dominant timeout
TxD = Low; LIN dominant
timeout enabled
24
ms
−4
9
0
13
LIN RECEIVER
trec_prop_down
Propagation delay of receiver falling
edge
0.1
6
ms
trec_prop_up
Propagation delay of receiver rising
edge
0.1
6
ms
2
ms
trec_sym
Propagation delay symmetry
trec_prop_down −
trec_prop_up
−2
tLIN_wake
Dominant duration for wakeup
LIN in wakeup mode
30
80
150
ms
Low power mode entry EN to TxD
sampling point delay
Normal mode:
Figure 9, Figure 10
13
25
55
ms
Normal mode or Reset mode transition time
Low power mode:
Figure 9, Figure 10
13
25
55
ms
Low power mode transition time
(Standby or Sleep)
Normal mode:
Figure 9, Figure 10
27
45
91
ms
RSTN pulse extension
Figure 6, Figure 7, Figure
8
3
5
10
ms
Undervoltage detection filter time
Figure 6
13
25
55
ms
MODE TRANSITIONS AND TIMEOUTS
tsample_txd
tmode
tlp_mode
treset
tVOUT_RES_filt
11. Values based on design and characterization. Not tested in production.
12. For low slope versions only (NV7428L5 and NV7428L3)
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8
NCV7428
Functional Description
VS Supply Input
LIN Operating Modes
VS pin of NCV7428 is typically connected to the car
battery through a reverse−protection diode and can be
exposed to all relevant automotive disturbances (ISO7637
pulses, system ESD ...). VS supplies mainly the integrated
LIN transceiver. Filtering capacitors should be connected
between VS and GND.
During power−up of the battery supply, VS pin must reach
VS_PORH level in order for the circuit to become functional
– the internal state machine is initiated and the VOUT
regulator is activated. The circuit remains functional until
VS falls back below VS_PORL level, when the device enters
the Shutdown mode.
In LIN Active mode the transceiver can transmit and
receive data via LIN bus with speed up to 20 kBaud for
normal slope mode and 10 kBaud/s for low slope version.
The transmit data stream of the LIN protocol is present on
the TxD pin and converted by the transmitter into a LIN bus
signal with controlled slew rate to minimize EMC emission.
The receiver consists of the comparator that has a threshold
with hysteresis in respect to the supply voltage and an input
filter to remove bus noise. The LIN output is pulled HIGH
via an internal pull−up resistor (typ. 30 kW). For master
applications, it is needed to put an external resistor (typ.
1 kW) with a serial diode between LIN and VS. The mode
selection is done by EN = High.
The transmission is only initiated with the TxD falling
edge in LIN Active mode. Entering this mode with TxD
already Low will not lead to transmitting bus Dominant
signal.
When leaving Normal mode (EN pin falling edge), the
transmitter is deactivated immediately.
The LIN Wakeup mode can be entered if the EN pin is
Low. The LIN receiver stays active to be able to detect a
remote wake−up via bus. The LIN transmitter is disabled
and the slave internal termination resistor of 30 kW between
LIN and VS is disconnected in order to minimize current
consumption. Only a pull−up current source between Vs and
LIN is active. The valid LIN wakeup event causes driving
RxD Low until EN pin is pulled High.
A Wakeup pattern that is initiated in LIN Active mode and
ends in LIN Wakeup mode is also considered a valid Wakeup
event.
The LIN Wakeup mode is also forced if the device enters
to the Sleep operating mode.
The LIN Off mode provides extreme low current
consumption, LIN transceiver is fully deactivated. Pin RxD
stays High (as long as VOUT is provided) and logical level
on TxD is ignored.
The bus pin is internally pulled to VS with a current source
(thus limiting VS consumption in case of a permanent LIN
short to GND).
This mode is entered when NCV7428 is in Shutdown
mode (VS < VS_PORL ) or in Thermal Shutdown mode (TJ >
TJ_SD).
VOUT Low−drop Voltage Regulator
The application low−voltage supply is provided by an
integrated low−drop voltage regulator delivering a 5 V or
3.3 V output VOUT. It is able to deliver up to 70 mA with
given precision and is primarily intended to supply the
application microcontroller unit (MCU) and related 5 V or
3.3 V loads (e.g. its own MCU−related digital inputs/
outputs). An external capacitor needs to be connected on
VOUT pin in order to ensure the regulator’s stability and to
filter the disturbances caused by the connected loads.
All low−voltage digital pins are related to VOUT.
LIN Transceiver
NCV7428 integrates on−chip LIN transceiver interface
between physical LIN bus and the LIN protocol controller.
This LIN physical layer is compatible to LIN2.x and
J2602 specifications.
NCV7428 LIN2.2 compliant physical layer can be
combined on the network with all previous LIN physical
layers.
NCV7428 LIN transceiver consists of a transmitter,
receiver and wakeup detector. The LIN transceiver can be
connected to the bus line via LIN pin, and to the digital
control through pins TxD and RxD. The functional mode of
the LIN transceiver depends on the operating mode and on
EN pin state – see Figure 3. The LIN transceiver is supplied
directly from the VS pin.
www.onsemi.com
9
NCV7428
LIN Mode
LIN Off
Bus Pin
Pull−up
LIN Wakeup
LIN Active
Current Source
30 kW Resistor
recessive
LIN
dominant
TxD
RxD
EN
ignored
tTxD_timeout
LIN Wakeup
detected
LIN Active
mode set
Figure 3. LIN Modes
< tLIN_wake
tLIN_wake
recessive
LIN
dominant
RxD
EN
LIN Wakeup
detected
Figure 4. LIN Wakeup Detection
www.onsemi.com
10
LIN Active
mode restored
NCV7428
Operating Modes
The principal operating modes of NCV7428 are shown in Figure 5 and described in the following paragraphs.
Any mode
(except for shutdown)
Any mode
VS < VS_PORL
TJ > T J_SD
THERMAL
SHUTDOWN
−VOUT: off
−RSTN: Low
−LIN: Wakeup mode
−RxD: Low after Wakeup/
pulled to VOUT otherwise
SHUTDOWN
VS power−up
−VOUT: off
−RSTN: Low
−LIN: Off mode
−RxD: pulled to VOUT
V S > VS_PORH
and TJ < TJ_SD
TJ < T J_SD
RESET
−VOUT : on
−RSTN: Low
−LIN: Wakeup mode
−RxD: Low after Wakeup/
High otherwise
STANDBY
−VOUT: on
−RSTN: High
−LIN: Wakeup mode
−RxD: Low after Wakeup/
High otherwise
NORMAL
EN = 1
−VOUT: on
−RSTN: High
−LIN: Active mode
−RxD: Received LIN Data
EN = 0
and
TxD = 1
LIN_EN = 0
and
TxD = 0
SLEEP
−VOUT: off
−RSTN: Low
−LIN: Wakeup mode
−RxD: pulled to VOUT
Figure 5. Operating Modes
www.onsemi.com
11
LIN wakeup
or
EN = 1
NCV7428
Shutdown Mode
High when leaving Reset mode – treset time elapsed
(Figure 8).
LIN transceiver is in Active mode. VOUT is kept on. Pin
RSTN remains High.
The Shutdown mode is a passive state, in which all
NCV7428 resources are inactive. The Shutdown mode
provides a defined starting point for the circuit in case of
supply undervoltage, thermal Shutdown or the first supply
connection.
On−chip power−supply VOUT is switched off and the LIN
pin remains passive so that it does not disturb the
communication of other nodes connected to the LIN bus.
RxD pin stays pulled to VOUT. No wakeups can be detected.
RSTN pin is forced Low – RSTN Low level is guaranteed
for VS supply above VS_DigOut_Low.
The Shutdown mode is entered asynchronously whenever
the VS level falls below the power−on−reset level VS_PORL .
The Shutdown mode is left only when the VS supply
exceeds the high power−on−reset level VS_PORH while
junction temperature is below TJ_SD . When exiting the
Shutdown mode, NCV7428 always enters the Reset mode.
Standby Mode
Standby mode is entered from Normal mode after host
request – EN pin falling edge followed by TxD pin High.
TxD is sampled tsample_txd after EN edge (Figure 9). Standby
mode is also entered if EN pin is Low when leaving Reset
mode – treset time elapsed (Figure 7).
LIN transceiver is in Wakeup mode – RxD pin is latched
Low after valid Wakeup recognition until Normal mode is
requested. VOUT is kept active. Pin RSTN remains High.
Sleep Mode
Sleep mode can be only entered from Normal mode after
a host request – EN pin falling edge followed by TxD pin
Low. LIN transmitter is blocked immediately after EN pin
falling edge, therefor TxD pin and EN pin can be set Low at
the same moment. TxD is sampled tsample_txd after EN pin
edge (Figure 10).
VOUT regulator is switched off, LIN transceiver is in the
Wakeup mode.
If LIN wakeup is detected or EN goes High, Reset mode
is entered. LIN wakeup is signaled by RxD, which remains
Low until Normal mode is restored (EN is High).
RESET Mode
The Reset mode is a transient mode providing a defined
RSTN pulse for the application microcontroller.
VOUT supply is kept active. The LIN pin is passive so that
it does not disturb the communication of other nodes
connected to the bus. RxD pin is High if no wakeup was
detected, RxD Low level indicates pending LIN wakeup.
Pin RSTN is forced Low.
Reset mode will be entered as a consequence of one of the
following events:
• Shutdown mode is exited
• Thermal Shutdown mode is exited
• VOUT voltage falls below VOUT_RES level
• LIN wakeup or EN = High was detected in Sleep mode
Normally, the Reset mode is left when VOUT voltage is
above VOUT_RES threshold and defined time treset elapses.
The RSTN pin is internally released to High and the chip
then goes to the Normal or Standby mode, depending on EN
state.
Thermal Shutdown
The device junction temperature is monitored in order to
avoid permanent degradation or damage of the chip.
Junction temperature exceeding the Shutdown level TJ_SD
puts the chip into Thermal Shutdown mode.
In Thermal Shutdown mode, VOUT regulator is switched
off. LIN transceiver is in Wakeup mode and can detect bus
Wakeup. RxD pin stays pulled to VOUT or is driven Low
after valid Wakeup recognition. RSTN pin is pulled low. The
mode is automatically left only when the junction cools
down below the TJ_SD threshold.
Normal Mode
Normal mode is entered from Standby mode after a host
request – driving EN pin High (Figure 9), or if EN pin is
www.onsemi.com
12
NCV7428
VS
VOUT
VS
t VOUT_RES_ filt
t VOUT_RES_ filt
tVOUT_ RES_ filt
< t VOUT_ RES_filt
V OUT
VOUT_RES
VS_PORH
treset
treset
RSTN
EN
Operating
Shutdown
mode
Reset
Standby
Reset
Standby
Figure 6. VOUT Regulator Voltage Monitoring
EN
ignored
TxD
ignored
RxD
LIN wakeup indication
treset
RSTN
Operating
mode
Reset
VOUT > VOUT_RES
Standby
RSTN pulse released
EN sampled
Figure 7. Operating Modes, Transition from Reset to Standby Mode
www.onsemi.com
13
NCV7428
ignored
EN
TxD
ignored
RxD
LIN wakeup indication
treset
tmode
RSTN
Operating
mode
Reset
Normal
RSTN pulse released
EN sampled
VOUT > VOUT_RES
Mode change
LIN wakeup flag cleared
Figure 8. Operating Modes, Transition from Reset to Normal Mode
EN
TxD sampling point
TxD
LIN
ignored
ignored
LIN transmission
blocked
RxD
LIN wakeup indication
RSTN
Operating
mode
Normal
Standby
tsample_txd
Normal
tmode
tlp_mode
Figure 9. Operating Modes, Transition from Normal to Standby Mode
www.onsemi.com
14
NCV7428
EN
TxD sampling point
ignored
TxD
ignored
LIN transmission
blocked
LIN
RxD
LIN wakeup
indication
VOUT OFF
RSTN
Operating
mode
Normal
Sleep
Reset
tmode
tsample_txd
tlp_mode
Figure 10. Operating Modes, Transition from Normal to Sleep Mode
TxD
t BIT
tBIT
50%
LIN
t
t BUS_dom(max)
tBUS_rec(min)
THREC(max)
THDOM(max)
Thresholds of
receiving node 1
THREC(min)
THDOM(min)
Thresholds of
receiving node 2
tBUS_dom(min)
tBUS_rec(max)
Figure 11. Definition of LIN Duty Cycle Parameters
www.onsemi.com
15
t
NCV7428
LIN
100%
60%
60%
40%
40%
0%
tfall
t
trise
Figure 12. Definition of LIN Edge Parameters
TxD
tBIT
tBIT
50%
t
LIN
VS
60% VS
40% VS
t tx_prop_down
t
ttx _prop_up
Figure 13. Definition of LIN Transmitter Timing Parameters
LIN
VS
60% VS
40% VS
RxD
trec_prop_down
trec_prop_up
t
50%
Figure 14. Definition of LIN Receiver Timing Parameters
www.onsemi.com
16
t
NCV7428
ORDERING INFORMATION
Part Number
Description
Marking
NCV7428D15R2G
LIN transceiver with 5 V regulator
NV7428−5
NCV7428D13R2G
LIN transceiver with 3.3 V regulator
NV7428−3
NCV7428D1L5R2G
LIN transceiver with 5 V regulator,
low slope LIN
NV7428L5
NCV7428D1L3R2G
LIN transceiver with 3.3 V regulator,
low slope LIN
NV7428L3
NCV7428MW5R2G
LIN transceiver with 5 V regulator
NV7428−5
NCV7428MW3R2G
LIN transceiver with 3.3 V regulator
NV7428−3
NCV7428MWL5R2G
LIN transceiver with 5 V regulator,
low slope LIN
NV7428L5
NCV7428MWL3R2G
LIN transceiver with 3.3 V regulator,
low slope LIN
NV7428L3
Package
Shipping †
SOIC−8
(Pb−Free)
3000 / Tape & Reel
DFN8
Wettable Flanks
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 3x3, 0.65P
CASE 506DG
ISSUE A
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.10 C
2X
DETAIL A
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
L
ALTERNATE TERMINAL
CONSTRUCTION
E
A
A3
SIDE VIEW
SEATING
PLANE
1
D2
DETAIL A
1
8X
C
A1
4
L
e/2
8
5
8X
b
0.10 C A B
e
BOTTOM VIEW
0.05 C
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
2.56
1.70
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
1
0.65
PITCH
XXXXXX
XXXXXX
ALYWG
G
XXXXXX= Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
3.00 BSC
2.30
2.50
3.00 BSC
1.50
1.70
0.65 BSC
0.30 TYP
0.35
0.45
GENERIC
MARKING DIAGRAM*
0.05 C
NOTE 4
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.05 C
DATE 28 APR 2016
8X
0.60
3.30
8X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527G
DFN8 3X3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
8
1
SCALE 1:1
NOTES 4&5
0.10 C D
45 5 CHAMFER
D
h
NOTE 6
D
A
8
DATE 18 MAY 2015
H
2X
5
0.10 C D
E
E1
NOTES 4&5
L2
1
0.20 C D
4
8X
B
NOTE 6
TOP VIEW
b
0.25
M
L
C
DETAIL A
C A-B D
NOTES 3&7
NOTE 7
c
0.10 C
e
A1
C
SIDE VIEW
NOTE 8
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
DETAIL A
A2
A
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
SEATING
PLANE
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
--1.75
0.10
0.25
1.25
--0.31
0.51
0.10
0.25
4.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.25
0.41
0.40
1.27
0.25 BSC
GENERIC
MARKING DIAGRAM*
8X
0.76
8
8X
1.52
1
7.00
XXXXX
A
L
Y
W
G
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34918E
SOIC−8
XXXXX
ALYWX
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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