NCV7513BFTR2G

NCV7513B FLEXMOSt Hex Low-Side MOSFET Pre-Driver The NCV7513B programmable six channel low−side MOSFET pre−driver is one of a family of FLEXMOSTM automotive grade products for driving logic−level MOSFETs. The product is controllable by a combination of serial SPI and parallel inputs. It features programmable fault management modes and allows power−limiting PWM operation with programmable refresh time. The device offers 3.3 V/5.0 V compatible inputs and the serial output driver can be powered from either 3.3 V or 5.0 V. Power−on reset provides controlled powerup and two enable inputs allow all outputs to be simultaneously disabled. Each channel independently monitors its external MOSFET’s drain voltage for fault conditions. Shorted load fault detection thresholds are fully programmable using an externally programmed reference voltage and a combination of four discrete internal ratio values. The ratio values are SPI selectable and allow different detection thresholds for each group of three output channels. Fault information for each channel is 2−bit encoded by fault type and is available through SPI communication. Fault recovery operation for each channel is programmable and may be selected for latch−off or automatic retry. The FLEXMOS family of products offers application scalability through choice of external MOSFETs. Features • • • • • • • • • 16−Bit SPI with Frame Error Detection 3.3 V/5.0 V Compatible Parallel and Serial Control Inputs 3.3 V/5.0 V Compatible Serial Output Driver Two Enable Inputs Open−Drain Fault and Status Flags Programmable − Shorted Load Fault Detection Thresholds − Fault Recovery Mode − Fault Retry Timer − Flag Masking Load Diagnostics with Latched Unique Fault Type Data − Shorted Load − Open Load − Short to GND NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAM LQFP32 FT SUFFIX CASE 561AB A WL YY WW G NCV7513B AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NCV7513BFTG LQFP (Pb−Free) 250 Units/Tray NCV7513BFTR2G LQFP 2000 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Benefits • Scalable to Load by Choice of External MOSFET © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 2 1 Publication Order Number: NCV7513B/D NCV7513B IN5 IN4 IN3 IN2 IN1 IN0 ENA2 VCC2 NCV7513B CHANNEL 0 Hex MOSFET Pre−Driver DRN0 FAULT DETECT POWER ON RESET & BIAS VCC1 VSS POR VCC2 DRIVER ENA1 GATE SELECT GAT0 VSS FLAG MASK ENA ENA VCC2 DRN 1 2 REF DISABLE DISABLE MODE REFRESH/REF CSB PARALLEL SERIAL IREF 6 ENA ENA VCC2 DRN 1 2 REF DISABLE PARALLEL SERIAL VCC SCLK POR CSB SCLK SI CHANNEL 1 CHANNEL 2 IREF SI VSS VSS DRN1 GAT1 DRN2 GAT2 SPI ENA ENA VCC2 DRN 1 2 REF DISABLE 16 BIT VDD CHANNEL 3 PARALLEL SERIAL SO DRIVER IREF SO DRN VSS ENA ENA VCC2 1 2 REF DISABLE PARALLEL SERIAL 12 FAULT BITS 2 GND + OA − ENA ENA VCC2 DRN 1 2 REF DISABLE FAULT LOGIC & REFRESH TIMER ENA1 4 FLTREF CHANNEL 4 IREF FLTB VSS CHANNEL 5 PARALLEL SERIAL IREF CLOCK FAULT REFERENCE GENERATOR VSS DRN 0:5 CH 0−2 MASK 0:5 CH 3−5 POR Figure 1. Block Diagram www.onsemi.com 2 ENA 1 VSS DRN3 GAT3 DRN4 GAT4 DRN5 GAT5 VSS DRAIN FEEDBACK MONITOR STAB M +5V 14W UNCLAMPED LOAD VLOAD 14W 28W 28W 5W NCV7513B RFILT CB1 +5V OR +3.3V RX1 POWER−ON RESET VCC1 VCC2 FLTREF DRN0 ENA1 GAT0 ENA2 DRN1 IN0 GAT1 IN1 DRN2 RD0 NID9N05CL RD1 NID9N05CL RD2 IN2 SPI IN3 IN4 IN5 NCV7513B HOST CONTROLLER PARALLEL RX2 RST NID9N05CL GAT2 RD3 CB2 DRN3 NID9N05CL GAT3 RD4 DRN4 NID9N05CL IRQ FLTB GAT4 I/O CSB DRN5 SCLK GAT5 RD5 NID9N05CL RFPU SI VDD STAB SO GND VSS RSPU Figure 2. Application Diagram www.onsemi.com 3 NCV7513B PIN FUNCTION DESCRIPTION Symbol FLTREF Description Analog Fault Detect Threshold: 5.0 V Compliant DRN0 – DRN5 Analog Drain Feedback: Internally Clamped GAT0 – GAT5 Analog Gate Drive: 5.0 V Compliant ENA1, ENA2 Digital Master Enable Inputs: 3.3 V/5.0 V (TTL) Compatible Digital Parallel Input: 3.3 V/5.0 V (TTL) Compatible Digital Serial Data Output: 3.3 V/5.0 V Compliant STAB Digital Open−Drain Output: 3.3 V/5.0 V Compliant FLTB Digital Open−Drain Output: 3.3 V/5.0 V Compliant VCC1 Power Supply − Low Power Path GND Power Return − Low Power Path – Device Substrate VCC2 Power Supply − Gate Drivers VDD Power Supply − Serial Output Driver VSS Power Return – VCC2, VDD, Drain Clamps DRN5 SO GAT4 Digital Serial Data Input: 3.3 V/5.0 V (TTL) Compatible DRN4 SI GAT3 Digital Shift Clock Input: 3.3 V/5.0 V (TTL) Compatible DRN3 SCLK GAT2 Digital Chip Select Input: 3.3 V/5.0 V (TTL) Compatible DRN2 CSB GAT5 IN0 – IN5 24 23 22 21 20 19 18 17 GAT1 25 16 VSS DRN1 26 15 STAB GAT0 27 14 VDD DRN0 28 13 SO VCC2 29 12 SI VCC1 30 11 SCLK FLTREF 31 10 CSB GND 32 9 FLTB 4 5 6 7 8 IN4 IN5 ENA2 ENA1 IN1 3 IN3 2 IN2 1 IN0 NCV7513B Figure 3. 32 Pin LQFP Pinout (Top View) www.onsemi.com 4 NCV7513B MAXIMUM RATINGS (Voltages are with respect to device substrate.) Rating Value Unit −0.3 to 6.5 V Difference Between VCC1 and VCC2 "0.3 V Difference Between GND (Substrate) and VSS "0.3 V Output Voltage (Any Output) −0.3 to 6.5 V Drain Feedback Clamp Voltage (Note 1) −0.3 to 47 V Drain Feedback Clamp Current (Note 1) 10 mA Input Voltage (Any Input) −0.3 to 6.5 V Junction Temperature, TJ −40 to 150 °C Storage Temperature, TSTG −65 to 150 °C Peak Reflow Soldering Temperature: Lead−Free 60 to 150 seconds at 217°C (Note 2) 260 peak °C DC Supply (VCC1, VCC2, VDD) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ATTRIBUTES Characteristic Value ESD Capability Human Body Model Machine Model w " 2.0 kV w " 200 V Moisture Sensitivity (Note 2) MSL2 Package Thermal Resistance (Note 3) Junction–to–Ambient, RqJA Junction–to–Pin, RYJL 86.0 °C/W 58.5 °C/W 1. An external series resistor must be connected between the MOSFET drain and the feedback input in the application. Total clamp power dissipation is limited by the maximum junction temperature, the application environment temperature, and the package thermal resistances. 2. For additional information, see or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D, and Application Note AND8003/D. 3. Values represent still air steady−state thermal performance on a 4 layer (42 x 42 x 1.5 mm) PCB with 1 oz. copper on an FR4 substrate, using a minimum width signal trace pattern (384 mm2 trace area). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 4.75 5.25 V VCC1 − 0.3 VCC1 + 0.3 V VCC1 Main Power Supply Voltage VCC2 Gate Drivers Power Supply Voltage VDD Serial Output Driver Power Supply Voltage 3.0 VCC1 V VIN High Logic High Input Voltage 2.0 VCC1 V VIN Low Logic Low Input Voltage TA Ambient Still−Air Operating Temperature 0 0.8 V −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 5 NCV7513B ELECTRICAL CHARACTERISTICS (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 4) Characteristic Symbol Conditions Min Typ Max Unit ENAX = 0 ENA1 = ENA2 = VCC1, VDRNX = 0 V, GATX drivers off ENA1 = ENA2 = VCC1, GATX drivers on – – 2.80 3.10 5.0 5.0 mA – 2.80 5.0 3.65 4.20 4.60 V 0.150 0.385 – V 2.0 – – V VCC1 Supply Operating Current – VCC1 = 5.25 V, VFLTREF = 1.0 V Power−On Reset Threshold VCC1 Rising Power−On Reset Hysteresis − Digital I/O VIN High ENAX, INX, SI, SCLK, CSB VIN Low ENAX, INX, SI, SCLK, CSB – – 0.8 V VIN Hysteresis ENAX, INX, SI, SCLK, CSB 100 330 500 mV Input Pullup Current CSB VIN = 0 V −25 −10 – mA Input Pulldown Current ENA2, INX, SI, SCLK, VIN = VCC1 – 10 25 mA Input Pulldown Resistance ENA1 SO Low Voltage VDD = 3.3 V, ISINK = 5.0 mA SO High Voltage VDD = 3.3 V, ISOURCE = 5.0 mA SO Output Resistance Output High or Low SO Tri−State Leakage Current CSB = 3.3 V STAB Low Voltage STAB Leakage Current 100 150 200 kW – 0.11 0.25 V VDD − 0.25 VDD − 0.11 – V – 22 – W −10 – 10 mA STAB Active, ISTAB = 1.25 mA – 0.1 0.25 V VSTAB = VCC1 – – 10 mA FLTB Low Voltage FLTB Active, IFLTB = 1.25 mA – 0.1 0.25 V FLTB Leakage Current VFLTB = VCC1 – – 10 mA FLTREF Input Current VFLTREF = 0 V −1.0 – – mA FLTREF Input Linear Range (Note 5) 0 – VCC1 − 2.0 V (Note 5) 30 – – dB IDRNX = 10 mA IDRNX = ICL(MAX) = 10 mA 27 – 34 42 – 47 V Register 2: R1 = 0, R0 = 0 or R4 = 0, R3 = 0 20 25 30 % VFLTREF Register 2: R1 = 0, R0 = 1 or R4 = 0, R3 = 1 45 50 55 % VFLTREF Register 2: R1 = 1, R0 = 0 or R4 = 1, R3 = 0 70 75 80 % VFLTREF Register 2: R1 = 1, R0 = 1 or R4 = 1, R3 = 1 95 100 105 % VFLTREF VCC1 = VCC2 = VDD = 5.0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) VCC1 = VCC2 = VDD = 0 V, ENAX = INX = 0 V, VDRNX = VCL(MIN) −1.0 – 1.0 mA Fault Detection – GATX ON FLTREF Op−amp VCC1 PSRR DRNX Clamp Voltage DRNX Shorted Load Threshold GATX Output High VFLTREF = 1.0 V DRNX Input Leakage Current VCL Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 5. Guaranteed by design. www.onsemi.com 6 NCV7513B ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 6) Characteristic Symbol Conditions Min Typ Max Unit Fault Detection – GATX OFF DRNX Diagnostic Current DRNX Fault Threshold Voltage DRNX Off State Bias Voltage ISG Short to GND Detection, VDRNX = 0.30 VCC1 −27 −20 −10 mA IOL Open Load Detection, VDRNX = 0.75 VCC1 30 60 80 mA VSG Short to GND Detection 27 30 33 %VCC1 VOL Open Load Detection 72 75 78 %VCC1 – 50 – %VCC1 1.0 1.80 2.5 kW −5.25 – −1.9 mA 1.9 – 5.25 mA – – 1.0 – – 1.0 – – 1.40 ms – – 1.40 ms VCTR − Gate Driver Outputs GATX Output Resistance Output High or Low GATX High Output Current VGATX = 0 V GATX Low Output Current VGATX = VCC2 Turn−On Propagation Delay tP(ON) ms INX to GATX (Figure 4) CSB to GATX (Figure 5) Turn−Off Propagation Delay tP(OFF) ms INX to GATX (Figure 4) CSB to GATX (Figure 5) Output Rise Time tR 20% to 80% of VCC2, CLOAD = 400 pF (Figure 4, Note 5) Output Fall Time tF 80% to 20% of VCC2, CLOAD = 400 pF (Figure 4, Note 5) Fault Timers Channel Fault Blanking Timer tBL(ON) VDRNX = 5.0 V; INX rising to FLTB falling (Figure 6) 30 45 60 ms tBL(OFF) VDRNX = 0 V; INX falling to FLTB falling (Figure 6) 90 120 150 ms Channel Fault Filter Timer tFF Figure 7 7.0 12 17 ms Global Fault Refresh Timer (Auto−retry Mode) tFR Register 2: Bit R2 = 0 or R5 = 0 7.5 10 12.5 ms Register 2: Bit R2 = 1 or R5 = 1 30 40 50 ms ENA1 = 1 – 500 – kHz 3.0 3.3 3.6 V 4.5 5.0 5.5 V – 250 – ns Timer Clock Serial Peripheral Interface (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF SO Supply Voltage VDD 3.3 V Interface 5.0 V Interface SCLK Clock Period − Maximum Input Capacitance Sl, SCLK (Note 7) – – 12 pF SCLK High Time SCLK = 2.0 V to 2.0 V 125 – – ns SCLK Low Time SCLK = 0.8 V to 0.8 V 125 – – ns Sl Setup Time Sl = 0.8 V/2.0 V to SCLK = 2.0 V (Note 7) 25 – – ns Sl Hold Time SCLK = 2.0 V to Sl = 0.8 V/2.0 V (Note 7) 25 – – ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 7. Guaranteed by design. www.onsemi.com 7 NCV7513B ELECTRICAL CHARACTERISTICS (continued) (4.75 VvVCCXv5.25 V, VDD = VCCX, −40°CvTJv125°C, unless otherwise specified.) (Note 8) Characteristic Symbol Conditions Min Typ Max Unit Serial Peripheral Interface (continued) (Figure 9) Vccx = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF SO Rise Time (20% VSO to 80% VDD) CLOAD = 200 pF (Note 9) – 25 50 ns SO Fall Time (80% VSO to 20% VDD) CLOAD = 200 pF (Note 9) – – 50 ns CSB Setup Time CSB = 0.8 V to SCLK = 2.0 V (Note 9) 60 – – ns CSB Hold Time SCLK = 0.8 V to CSB = 2.0 V (Note 9) 75 – – ns CSB to SO Time CSB = 0.8 V to SO Data Valid (Note 9) – 65 125 ns SO Delay Time SCLK = 0.8 V to SO Data Valid (Note 9) – 65 125 ns Transfer Delay Time CSB Rising Edge to Next Falling Edge (Note 9) 1.0 – – ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. Designed to meet these characteristics over the stated voltage and temperature recommended operating ranges, though may not be 100% parametrically tested in production. 9. Guaranteed by design. www.onsemi.com 8 NCV7513B INX 50% tP(OFF) GAT X tR 80% 50% 20% tP(ON) Figure 4. Gate Driver Timing Diagram – Parallel Input CSB 50% GX tP(OFF) GAT X 50% tP(ON) Figure 5. Gate Driver Timing Diagram – Serial Input DRNX INX 50% tBL(ON) FLTB tBL(OFF) 50% 50% Figure 6. Blanking Timing Diagram www.onsemi.com 9 tF NCV7513B OPEN LOAD THRESHOLD SHORTED LOAD THRESHOLD DRNX INX tFF FLTB tFF 50% 50% Figure 7. Filter Timing Diagram GAT X tBL(ON) tFR tFF DRNX tFR tBL(ON) tFR SHORTED LOAD THRESHOLD (FLTREF) INX Figure 8. Fault Refresh Timing Diagram CSB SETUP TRANSFER DELAY CSB SI SETUP SCLK CSB HOLD 1 16 SI HOLD SI MSB IN SO DELAY CSB to SO VALID SO LSB IN BITS 14...1 MSB OUT SO RISE,FALL BITS 14...1 LSB OUT SEE NOTE 80% VDD 20% VDD Note: Not defined but usually MSB of data just received. Figure 9. SPI Timing Diagram www.onsemi.com 10 NCV7513B DETAILED OPERATING DESCRIPTION General The NCV7513B is a six channel general purpose low−side pre−driver for controlling and protecting N−type logic level MOSFETs. While specifically designed for driving MOSFETs with resistive, inductive or lamp loads in automotive applications, the device is also suitable for industrial and commercial applications. Programmable fault detection and protection modes allow the NCV7513B to accommodate a wide range of external MOSFETs and loads, providing the user with flexible application solutions. Separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. ON Semiconductor’s SMARTDISCRETES TM clamp MOSFETs, such as the NID9N05CL, are recommended when driving unclamped inductive loads. The active−low CSB chip select input has a pullup current source. The SI and SCLK inputs have pulldown current sources. The recommended idle state for SCLK is low. The tri−state SO line driver can be supplied with either 3.3 or 5.0 V and is powered via the device’s VDD and VSS pins. The NCV7513B employs frame error detection that requires integer multiples of 16 SCLK cycles during each CSB high−low−high cycle (valid communication frame.) A frame error does not affect the flags. The CSB input controls SPI data transfer and initializes the selected device’s frame error and fault reporting logic. The host initiates communication when a selected device’s CSB pin goes low. Output (fault) data is simultaneously sent MSB first from the SO pin while input (command) data is received MSB first at the SI pin under synchronous control of the master’s SCLK signal while CSB is held low (Figure 10). Fault data changes on the falling edge of SCLK and is guaranteed valid before the next rising edge of SCLK. Command data received must be valid before the rising edge of SCLK. When CSB goes low, frame error detection is initialized, latched fault data is transferred to the SPI, and the FLTB flag is disabled and reset if previously set. Data for faults detected while CSB is low are ignored but will be captured if still present after CSB goes high. If a valid frame has been received when CSB goes high, the last multiple of 16 bits received is decoded into command data, and FLTB is re−enabled. Latched (previous) fault data is cleared and current fault data is captured. The FLTB flag will be set if a fault is detected. If a frame error is detected when CSB goes high, new command data is ignored, and previous fault data remains latched and available for retrieval during the next valid frame. The FLTB flag will be set if a fault (not a frame error) is detected. Power Up/Down Control The NCV7513B’s powerup/down control prevents spurious output operation by monitoring the VCC1 power supply. An internal Power−On Reset (POR) circuit causes all GATX outputs to be held low until sufficient voltage is available to allow proper control of the device. All internal registers are initialized to their default states, fault data is cleared, and the open−drain fault (FLTB) and status (STAB) flags are disabled. When VCC1 exceeds the POR threshold, outputs and flags are enabled and the device is ready to accept input data. When VCC1 falls below the POR threshold during power down, flags are reset and disabled and all GATX outputs are driven and held low until VCC1 falls below about 0.7 V. SPI Communication The NCV7513B is a 16−bit SPI slave device. SPI communication between the host and the NCV7513B may either be parallel via individual CSB addressing or daisy−chained through other devices using a compatible SPI protocol. CSB MSB SCLK LSB 1 2 4 − 13 3 14 15 16 SI X B15 B14 B13 B12 − B3 B2 B1 B0 SO Z B15 B14 B13 B12 − B3 B2 B1 B0 Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data Figure 10. SPI Communication Frame Format www.onsemi.com 11 X UKN Z NCV7513B Serial Data and Register Structure The 16−bit data sent by the NCV7513B is always the encoded 12−bit fault information, with the upper 4 bits forced to zero. The 16−bit data received is decoded into a 4−bit address and a 6−bit data word (see Figure 11). The upper four bits, beginning with the received MSB, are fully decoded to address one of four programmable registers and the lower six bits are decoded into data for the addressed register. Bit B15 must always be set to zero. The valid register addresses are shown in Table 1. Each register is next described in detail. MSB LSB B15 B14 B13 B12 B11 B10 0 0 0 0 B9 CH5 B8 B7 CH4 B6 CH3 B5 B4 CH2 B3 B2 CH1 B1 B0 CH0 CHANNEL FAULT OUTPUT DATA REGISTER SELECT COMMAND INPUT DATA MSB LSB B15 B14 B13 B12 B11 B10 0 A2 A1 A0 X X B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X D5 D4 D3 D2 D1 D0 Figure 11. SPI Data Format Table 1. Register Address Definitions 4−BIT ADDRESS 6−BIT INPUT DATA B15 A2 A1 A0 D5 D4 D3 D2 0 0 0 0 Gate Select 0 0 0 1 Disable Mode 0 0 1 0 Refresh & Reference 0 0 1 1 Flag Mask 0 1 X X Null D1 D0 16−BIT OUTPUT DATA B15 B14 B13 B12 B11 0 0 0 0 D11 B0 12−bit Fault Data Gate Select – Register 0 Each GATX output is turned on/off by programming its respective GX bit (see Table 2). Setting a bit to 1 causes the selected GATX output to drive its external MOSFET’s gate to VCC2 (ON). Setting a bit to 0 causes the selected GATX output to drive its external MOSFET’s gate to VSS (OFF). Note that the actual state of the output depends on POR, ENAX and shorted load fault states as later defined by Equation 1. At powerup, each bit is set to 0 (all outputs OFF). to 1 causes the selected GATX output to latch−off when a fault is detected. Setting a bit to 0 causes the selected GATX output to auto−retry when a fault is detected. At powerup, each bit is set to 0 (all outputs in auto−retry mode). Table 3. Disable Mode Register A1 A0 D5 D4 D3 D2 D1 D0 0 0 0 G5 G4 G3 G2 G1 G0 A2 A1 A0 D5 D4 D3 D2 D1 D0 0 0 1 M5 M4 M3 M2 M1 M0 0 = AUTO−RETRY 1 = LATCH OFF Table 2. Gate Select Register A2 D0 Refresh and Reference – Register 2 Refresh time (auto−retry mode) and shorted load fault detection references are programmable in two groups of three channels. Refresh time and the fault reference for channels 5−3 is programmed by RX bits 5−3. Refresh time and the fault reference for channels 2−0 is programmed by RX bits 2−0 (see Table 4). At powerup, each bit is set to 0 (VFLT = 25% VFLTREF , tFR = 10 ms). 0 = GATX OFF 1 = GATX ON Disable Mode – Register 1 The disable mode for shorted load faults is controlled by each channel’s respective MX bit (see Table 3). Setting a bit www.onsemi.com 12 NCV7513B Table 4. Refresh and Reference Register A2 A1 A0 D5 D4 D3 D2 D1 D0 0 1 0 R5 R4 R3 R2 R1 R0 CHANNELS 5−3 CHANNELS 2−0 25% VFLTREF X 0 0 X 0 0 50% VFLTREF X 0 1 X 0 1 75% VFLTREF X 1 0 X 1 0 VFLTREF X 1 1 X 1 1 tFR = 10 ms X X X 0 X X tFR = 40 ms X X X 1 X X tFR = 10 ms 0 X X X X X tFR = 40 ms 1 X X X X X Flag Mask – Register 3 The drain feedback from each channel’s DRNX input is combined with the channel’s KX mask bit (Table 5). When KX = 1, a channel’s mask is cleared and its feedback to the FLTB and STAB flags is enabled. At powerup, each bit is set to 0 (all masks set). Gate Driver Control and Enable Each GATX output may be turned on by either its respective parallel INX input or the internal GX (Gate Select) register bit via SPI communication. The device’s common ENAX enable inputs can be used to implement global control functions, such as system reset, overvoltage or input override by a watchdog controller. Each parallel input and the ENA2 input have individual internal pulldown current sources. The ENA1 input has an internal pulldown resistor. Unused parallel inputs should be connected to GND and unused enable inputs should be connected to VCC1. Parallel input is recommended when low frequency (v2.0 kHz) PWM operation of the outputs is desired. ENA2 disables all GATX outputs when brought low. When ENA1 is brought low, all GATX outputs, the timer clock, and the flags are disabled. The fault and gate registers are cleared and the flags are reset. New serial GX data is ignored while ENA1 is low but other registers can be programmed. When both the ENA1 and ENA2 inputs are high, the outputs will reflect the current parallel or serial input states. This allows ENA1 to be used to perform a soft reset and ENA2 to be used to disable the GATX outputs during initialization of the NCV7513B. The INX input state and the GX register bit data are logically combined with the internal (active low) power−on reset signal (POR), the ENAX input states, and the shorted load state (SHRTX) to control the corresponding GATX output such that: Table 5. Flag Mask Register A2 A1 A0 D5 D4 D3 D2 D1 D0 0 1 1 K5 K4 K3 K2 K1 K0 0 = MASK SET 1 = MASK CLEAR The STAB flag is influenced when a mask bit changes CLR→SET after one valid SPI frame. FLTB is influenced after two valid SPI frames. This is correct behavior for FLTB since, while a fault persists, the FLTB will be set when CSB goes LO→HI at the end of an SPI frame. The mask instruction is decoded after CSB goes LO→HI so FLTB will only reflect the mask bit change after the next SPI frame. Both FLTB and STAB require only one valid SPI frame when a mask bit changes SET→CLR. Null Register – Register 4 Fault information is always returned when any register is addressed. The null register (Table 6) provides a way to read back fault information without regard to the content of DX. Table 6. Null Register A2 A1 A0 D5 D4 D3 D2 D1 D0 1 X X X X X X X X GATX + POR · ENA1 · ENA2 · SHRTx · (INx ) Gx) (eq. 1) www.onsemi.com 13 NCV7513B The GATX state truth table is given in Table 7. On−state faults will initiate MOSFET protection behavior, set the FLTB flag and the respective channel’s DX bits in the device’s fault latches. Off−state faults will simply set the FLTB flag and the channel’s DX bits. Fault types are uniquely encoded in a 2−bit per channel format. Fault information for all channels simultaneously is retrieved by SPI read (Figure 11). Table 8 shows the fault−encoding scheme for channel 0. The remaining channels are identically encoded. Table 7. Gate Driver Truth Table POR ENA1 ENA2 SHRTX INX GX GATX 0 X X X X X L 1 0 0 X X X L 1 0 1 X X X L 1 1 0 X X X L 1 1 1 1 0 0 L 1 1 1 1 1 X H 1 1 1 1 X 1 H 1 1 1 0 X X L 1 1→0 1 X X →0 →L 1 1 1→0 X X GX 1 1 0→1 X 0 GX Table 8. Fault Data Encoding CHANNEL 0 D1 D0 0 0 NO FAULT →L 0 1 OPEN LOAD →GX 1 0 SHORT TO GND 1 1 SHORTED LOAD Gate Drivers The non−inverting GATX drivers are symmetrical resistive switches (1.80 kW typ.) to the VCC2 and VSS voltages. While the outputs are designed to provide symmetrical gate drive to an external MOSFET, load current switching symmetry is dependent on the characteristics of the external MOSFET and its load. Figure 12 shows the gate driver block diagram. DX0 DX1 tFR R2 | R 5 MX IN X GX ENA1 ENA2 POR FILTER TIMER ENCODING LOGIC S LATCH OFF / AUTO RE−TRY _ EN R FAULT DETECTION SHRTX Blanking and Filter Timers Blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. Filter timers are used to suppress glitches while a channel is in a stable state. A turn−on blanking timer is started when a channel is commanded on. Drain feedback is sampled after tBL(ON). A turn−off blanking timer is started when a channel is commanded off. Drain feedback is sampled after tBL(OFF). A filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. Drain feedback is sampled after tFF. Blanking timers for all channels are started when both ENA1 and ENA2 go high or when either ENAX goes high while the other is high. The blanking time for each channel depends on the commanded state when ENAX goes high. While each channel has independent blanking and filter timers, the parameters for the tBL(ON), tBL(OFF), and tFF times are the same for all channels. 50 DRNX BLANKING TIMER STATUS VSS VCC2 1800 DRIVER GAT X VSS Figure 12. Gate Driver Channel Fault Diagnostics and Behavior Each channel has independent fault diagnostics and employs blanking and filter timers to suppress false faults. An external MOSFET is monitored for fault conditions by connecting its drain to a channel’s DRNX feedback input through an external series resistor. When either ENA1 or ENA2 is low, diagnostics are disabled. When both ENA1 and ENA2 are high, diagnostics are enabled. Shorted load (or short to VLOAD) faults can be detected when a driver is on. Open load or short to GND faults can be detected when a driver is off. Shorted Load Detection An external reference voltage applied to the FLTREF input serves as a common reference for all channels (Figure 13). The FLTREF voltage must be within the range of 0 to VCC1−2.0 V and can be derived via a voltage divider between VCC1 and GND. Shorted load detection thresholds can be programmed via SPI in four 25% increments that are ratiometric to the applied FLTREF voltage. Separate thresholds can be selected for channels 0−2 and for channels 3−5 (Table 4). www.onsemi.com 14 NCV7513B Fault Recovery Refresh Time Refresh time for shorted load faults is SPI programmable to one of two values for channels 0−2 (register bit R2) and for channels 3−5 (register bit R5) via the Refresh and Reference register (Table 4). A global refresh timer with taps at nominally 10 ms and 40 ms is used for auto−retry timing. The first faulted channel triggers the timer and the full refresh period is guaranteed for that channel. An additional faulted channel may initially retry immediately after its turn−on blanking time, but subsequent retries will have the full refresh time period. If all channels in a group (e.g. channels 0−2) become faulted, they will become synchronized to the selected refresh period for that group. If all channels become faulted and are set for the same refresh time, all will become synchronized to the refresh period. A shorted load fault is detected when a channel’s DRNX feedback is greater than its selected fault reference after either the turn−on blanking or the filter has timed out. VCC1 CHANNELS 0−2 FLTREF RX1 0 − 3V 3 VCC1 2 1 0 + RX2 2X4 DECODER OA − R R1 R0 75% KELVIN REGISTER 2 BITS R 50% R R4 R3 25% R 3 2 1 0 2X4 DECODER CHANNELS 3−5 Figure 13. Shorted Load Reference Generator Open Load and Short to GND Detection A window comparator with fixed references proportional to VCC1 along with a pair of bias currents is used to detect open load or short to GND faults when a channel is off. Each channel’s DRNX feedback is compared to the references after either the turn−off blanking or the filter has timed out. Figure 14 shows the DRNX bias and fault detection zones. The diagnostics are disabled and the bias currents are turned off when ENAX is low. No fault is detected if the feedback voltage at DRNX is greater than the VOL open load reference. If the feedback is less than the VSG short to GND reference, a short to GND fault is detected. If the feedback is less than VOL and greater than VSG, an open load fault is detected. Shorted Load Fault Recovery Shorted load fault disable mode for each channel is individually SPI programmable via the MX bits in the device’s Disable Mode register (Table 3). When latch−off mode is selected the corresponding GATX output is turned off upon detection of a fault. Fault recovery is initiated by toggling (ON→OFF→ON) the channel’s respective INX parallel input, serial GX bit, or ENA2. When auto−retry mode is selected (default mode) the corresponding GATX output is turned off for the duration of the programmed fault refresh time (tFR) upon detection of a fault. The output is automatically turned back on (if still commanded on) when the refresh time ends. The channel’s DRNX feedback is resampled after the turn−on blanking time. The output will automatically be turned off if a fault is again detected. This behavior will continue for as long as the channel is commanded on and the fault persists. In either mode, a fault may exist at turn−on or may occur some time afterward. To be detected, the fault must exist longer than either tBL(ON) at turn−on or longer than tFF some time after turn−on. The length of time that a MOSFET stays on during a shorted load fault is thus limited to either tBL(ON) or tFF. In auto−retry mode, a persistent shorted load fault will result in a low duty cycle (tFD [ tBL(ON)/tFR) for the affected channel and help prevent thermal failure of the channel’s MOSFET. CAUTION − CONTINUOUS INPUT TOGGLING VIA INX, GX or ENA2 WILL OVERRIDE EITHER DISABLE MODE. Care should be taken to service a shorted load fault quickly when one has been detected. I DRNX Short to GND Open Load No Fault I OL 0 −ISG VDRNX VSG VCTR VOL Figure 14. DRNX Bias and Fault Detection Zones Figure 15 shows the simplified detection circuitry. Bias currents ISG and IOL are applied to a bridge along with bias voltage VCTR (50% VCC1 typ.). www.onsemi.com 15 NCV7513B Status Flag (STAB) The open−drain active−low status flag output can be used to provide a host controller with information about the state of a channel’s DRNx feedback. Feedback from all channels is logically ORed to the flag (Figure 16). The STAB outputs from several devices can be wire−ORed to a common pullup resistor connected to the controller’s 3.3 or 5.0 V VDD supply. When ENA1 is high, the drain feedback from a channel’s DRNx input is compared to the VOL reference without regard to ENA2 or the commanded state of the channel’s driver. The flag is reset and disabled when ENA1 is low or when all mask bits are set. See Table 9 for additional details. The flag is set (low) when the feedback voltage is less than VOL, and the channel’s mask bit (Table 5) is cleared. The flag is reset (hi−Z) when the feedback voltage is greater than VOL, and the channel’s mask bit is cleared. VCC1 I SG VLOAD A − CMP1 VOL D3 D1 + 50 + B DZ1 D4 CMP2 − 1600 D2 (VCL) RLOAD DRNX VX RDX RSG VSG VCTR + _ I OL +VOS Figure 15. Short to GND/Open−Load Detection When a channel is off and VLOAD and RLOAD are present, RSG is absent, and VDRNX >> VCTR, bias current IOL is supplied from VLOAD to ground through external resistors RLOAD and RDX, and through the internal 1650 W resistance and bridge diode D2. Bias current ISG is supplied from VCC1 to VCTR through D3. No fault is detected if the feedback voltage (VLOAD minus the total voltage drop caused by ISG and the resistance in the path) is greater than VOL. When either VLOAD or RLOAD and RSG are absent, the bridge will self−bias so that the voltage at DRNX will settle to about VCTR. An open load fault can be detected since the feedback is between VSG and VOL. Short to GND detection can tolerate up to a 1.0 V offset (VOS) between the NCV7513B’s GND and the short. When RSG is present and VDRNX VOL L − Z − STAB RESET 1 1 0 X 1 X X < VOL L − L − STAB SET 1 1 0 X 1→0 X X < VOL L − L→Z − STAB RESET 1 1 0 X 0→1 X X < VOL L − Z→L − STAB SET 1 1 1 X 1 0 0 > VOL L Z Z 00 FLAGS RESET 1 1 1 1 1 0 0 VSG