NCV7518MWATXG

NCV7518, NCV7518A FLEXMOS] Hex Low‐side MOSFET Pre‐driver The NCV7518 / NCV7518A programmable six channel low-side MOSFET pre-driver is one of a family of FLEXMOS automotive grade products for driving logic-level MOSFETs. The product is controllable by a combination of serial SPI and parallel inputs. The device offers 3.3 V/ 5 V compatible inputs and the serial output driver can be powered from either 3.3 V or 5 V. An internal power-on reset provides controlled power up. A reset input allows external re-initialization and an enable input allows all outputs and diagnostics to be simultaneously disabled. Each channel independently monitors its external MOSFET’s drain voltage for fault conditions. Shorted load fault detection thresholds are fully programmable using an externally programmed reference voltage and a combination of discrete internal ratio values. The ratio values are SPI selectable and allow different detection thresholds for each channel. Fault recovery operation for each channel is programmable and may be selected for latch-off or automatic retry. Status information for each channel is 3-bit encoded by fault type and is available through SPI communication. The FLEXMOS family of products offers application scalability through choice of external MOSFETs. Features • • • • • • • • • • • 16-bit SPI with Parity and Frame Error Detection 3.3 V/5 V Compatible Parallel and Serial Control Inputs 3.3 V/5 V Compatible Serial Output Driver Reset and Enable Inputs Open-drain Fault Flag Priority Encoded Diagnostics with Latched Unique Fault Type Data ♦ Shorted Load, Short to GND ♦ Open Load with Fast Charge Option ♦ On and Off State Pulsed Mode Diagnostics Ratiometric Diagnostic References and Currents Programmable ♦ Shorted Load Fault Detection Thresholds ♦ Fault Recovery Mode ♦ Blanking Timers Wettable Flanks Pb-Free Packaging NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable This is a Pb-Free Device www.onsemi.com QFN32 MW SUFFIX CASE 485CZ MARKING DIAGRAM 1 1 NCV7518 AWLYYWWG G A WL YY WW G NCV7518A AWLYYWWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NCV7518MWTXG QFN32 (Pb-Free) 5,000 / Tape & Reel NCV7518MWATXG QFN32 (Pb-Free) 5,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Benefits • Scalable to Load by Choice of External MOSFET © Semiconductor Components Industries, LLC, 2016 October, 2016 − Rev. 3 1 Publication Order Number: NCV7518/D NCV7518, NCV7518A IN5 IN4 IN3 IN2 IN1 IN0 ENB NCV7518 VCC2 RAIL Hex MOSFET Pre-Driver VREG 3V INTERNAL RAIL CHANNEL0 DRN0 POWER ON RESET & POR BIAS VCC1 FAULT DETECT DRN VSS VCC2 REF DISABLE DRIVER ENB RST RSTB VSS CONTROL REGISTERS RAIL GAT0 DRN RST ENB VCC2 REF CHANNEL1 DRN1 DISABLE PARALLEL SERIAL CSB IREF DRN RST ENB VCC2 REF SCLK SI RST DISABLE CSB PARALLEL SCLK SERIAL VSS CHANNEL2 GAT1 DRN2 GAT2 SI SPI 16 BIT DRN RST ENB VCC2 CHANNEL3 REF VDD DRN3 DISABLE PARALLEL SERIAL SO DRIVER GAT3 SO DRN VSS RST ENB VCC2 REF CHANNEL4 DRN4 DISABLE RST PARALLEL FAULT DATA SERIAL IREF FLTB CSB DRN FAULT LOGIC & REFRESH TIMER RST DISABLE DRN RST ENB VCC2 REF CHANNEL5 RST GAT4 DRN5 DISABLE PARALLEL SERIAL GND VSS GAT5 CLOCK RST ENB RST VCC1 FLTREF + OA − FAULT REFERENCE GENERATOR REF REF Figure 1. Block Diagram www.onsemi.com 2 OFF−STATE DIAGNOSTICS GENERATOR VSS VLOAD NCV7518, NCV7518A VLOAD CB3 VBAT UNCLAMPED LOAD REVERSE BATTERY & TRANSIENT PROTECTION M +5V +5V OR +3.3V PARALLEL HOST CONTROLLER RST VLOAD VCC2 VCC1 DRN0 RSTB GAT0 ENB DRN1 IN0 GAT1 IN1 DRN2 IN2 GAT2 IN3 SPI IN4 IN5 RX1 IRQ RFPU NCV7518 POWER-ON RESET CB1 RFILT DRN3 RD1* RD2* RD3* GAT3 DRN4 FLTB GAT4 CSB DRN5 SCLK GAT5 SI RD4* RD5* VDD FLTREF RX2 RD0* SO GND VSS * Optional R DX - See Application Guidelines Figure 2. Application Diagram www.onsemi.com 3 CB2 NCV7518, NCV7518A PACKAGE PIN DESCRIPTION 32 PIN QFN EXPOSED PAD PACKAGE Label FLTREF Description Analog Fault Detect Threshold: 5 V Compliant DRN0 − DRN5 Analog Drain Feedback GAT0 − GAT5 Analog Gate Drive: 5 V Compliant RSTB Digital Master Reset Input: 3.3 V/5 V (TTL) Compatible ENB Digital Master Enable Input: 3.3 V/5 V (TTL) Compatible IN0 − IN5 Digital Parallel Input: 3.3 V/5 V (TTL) Compatible CSB Digital Chip Select Input: 3.3 V/5 V (TTL) Compatible SCLK Digital Shift Clock Input: 3.3 V/5 V (TTL) Compatible SI Digital Serial Data Input: 3.3 V/5 V (TTL) Compatible SO Digital Serial Data Output: 3.3 V/5 V Compliant FLTB Digital Open-Drain Output: 3.3 V/5 V Compliant VLOAD Power Supply − Diagnostic References and Currents VCC1 Power Supply − Low Power Path GND Power Return − Low Power Path − Device Substrate VCC2 Power Supply − Gate Drivers VDD Power Supply − Serial Output Driver VSS Power Return − VLOAD, VCC2, VDD EP Exposed Pad − Connected to GND − Device Substrate NCV7518 Figure 3. 32 Pin QFN Exposed Pad Pinout (Top View) www.onsemi.com 4 NCV7518, NCV7518A MAXIMUM RATINGS (Voltages are with respect to device substrate.) Rating Value Unit DC Supply − VLOAD −0.3 to 40 V DC Supply − VCC1, VCC2, VDD −0.3 to 5.8 V Difference Between VCC1 and VCC2 ±0.3 V Difference Between GND (Substrate) and VSS ±0.3 V 78 V Drain Input Clamp Forward Voltage Transient (≤2 ms, ≤1% duty) Drain Input Clamp Forward Current Transient (≤2 ms, ≤1% duty) 10 mA Drain Input Clamp Energy Repetitive (≤2 ms, ≤1% duty) 1.56 mJ Drain Input Clamp Reverse Current VDRNX ≥ −1.0 V −50 mA Input Voltage (Any Input Other Than Drain) −0.3 to 5.8 V Output Voltage (Any Output) −0.3 to 5.8 V Junction Temperature, TJ −40 to 150 °C Storage Temperature, TSTG −65 to 150 °C 260 peak °C Peak Reflow Soldering Temperature: Lead-free 60 to 150 seconds at 217°C (Note 1) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ATTRIBUTES Characteristic Value ESD Capability Human Body Model per AEC−Q100−002 Drain Feedback Pins (Note 3) VLOAD Pin All Other Pins ≥ ±4.0 kV ≥ ±1.5 kV ≥ ±2.0 kV (Note 2) MSL3 (Note 4) (Note 5) 95°C/W 46°C/W 3.2°C/W Moisture Sensitivity Package Thermal Resistance − Still-air Junction-to-Ambient, RqJA Junction-to-Exposed Pad, RYJPAD 2. 3. 4. 5. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. With GND & VSS pins tied together − path between drain feedback pins and GND, or between drain feedback pins. Based on JESD51−3, 1.2 mm thick FR4, 2S0P PCB, 2 oz. signal, 20 thermal vias to 400 mm2 spreader on bottom layer. Based on JESD51−7, 1.2 mm thick FR4, 1S2P PCB, 2 oz. signal, 20 thermal vias to 80 x 80 mm 1 oz. internal spreader planes. RECOMMENDED OPERATING CONDITIONS Symbol Parameter MIN MAX Unit VLOAD Diagnostic References and Currents Power Supply Voltage 7.5 18.0 V VDRNX Drain Input Feedback Voltage −0.3 60 V VCC1 Main Power Supply Voltage 4.75 5.25 V VCC2 Gate Drivers Power Supply Voltage VCC1 − 0.3 VCC1 + 0.3 V VDD Serial Output Driver Power Supply Voltage 3.0 VCC1 V VFLTREF Fault Detect Threshold Reference Voltage 0.35 2.75 V VIN High Logic High Input Voltage 2.0 VCC1 V VIN Low Logic Low Input Voltage 0 0.8 V Ambient Still-air Operating Temperature −40 125 °C Startup Delay at Power-on Reset (POR) (Note 6) 500 − ms TA tRESET 6. Minimum wait time until device is ready to accept serial input data. www.onsemi.com 5 NCV7518, NCV7518A PARAMETRIC TABLES ELECTRICAL CHARACTERISTICS (4.75 V ≤ VCCX ≤ 5.25 V, VDD = VCCX, 4.5 V ≤ VLOAD ≤ 18 V, RSTB = VCCX, ENB = 0, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 7) Characteristic Symbol Conditions Min Typ Max Unit ICC1A RSTB = 0 − 2.80 5.0 mA ICC1B ENB = 0, RSTB = VCC1, VDRNX=0 V, GATX Drivers Off − 3.10 5.0 mA VCC1 SUPPLY Operating Current − VCC1 = 5.25 V, VFLTREF = 2.75 V ICC1C ENB = 0, RSTB = VCC1, GATX Drivers On − 2.80 5.0 mA Power-On Reset Threshold POR VCC1 Rising 3.65 4.125 4.60 V Power-On Reset Hysteresis PORH 0.150 0.385 − V VCC2 SUPPLY ICC2 VCC2 = 5.25 V, ENB = 0, RSTB = VCC1 = 5.25 V VDRNX = 0 V, GATX Drivers Off − 2.80 5.0 mA Standby Current IDD1 VDD = 5.25V, ENB = 0, RSTB = VCC1 = 5.25 V SO = Z − 25.0 34.0 mA Operating Current IDD2 VDD = 5.25V, ENB = 0, RSTB = VCC1 = 5.25 V SO = H or L − 625 850 mA Standby Current VLDSBY VLOAD = 13.2 V, 0 ≤ VCC1 ≤ 5.25, ENB = RSTB = VCC1, TA ≤ 85°C − − 5.0 mA Operating Current VLDOP VLOAD = 18 V, ENB = 0, RSTB = VCC1, VDRNX = 0 V − 11 15 mA VIN High VIHX RSTB, ENB, INX, SI, SCLK, CSB 2.0 − − V VIN Low VILX RSTB, ENB, INX, SI, SCLK, CSB − − 0.8 V VIN Hysteresis INHY RSTB, ENB, INX, SI, SCLK, CSB 100 330 500 mV Input Pullup Resistance RPUX ENB, CSB, VIN = 0 V 50 125 200 kW Input Pulldown Resistance RPDX RSTB, INX, SI, SCLK, VIN = VCC1 50 125 200 kW SO Low Voltage VSOL VDD = 3.0 V, ISINK = 2 mA − − 0.4 V SO High Voltage VSOH VDD = 3.0 V , ISOURCE = 2 mA VDD − 0.6 − − V SO Output Resistance RSO Output High or Low − 25 − W Operating Current VDD SUPPLY VLOAD SUPPLY DIGITAL I/O SO Tri-State Leakage Current SOLKG CSB = 3.0 V −5.0 − 5.0 mA FLTB Low Voltage VFLTB FLTB Active, IFLTB = 1.25 mA − − 0.4 V IFLTLKG VFLTB = VCC1 − − 10 mA FLTREF Input Current IFLTREF 0 V ≤ VFLTREF ≤ 2.75 V −1.0 − 1.0 mA FLTREF Input Linear Range VREFLIN (Note 8) 0.35 − 2.75 V PSRR (Note 8) 30 − − dB FLTB Leakage Current FAULT DETECTION − GATX ON FLTREF Op-amp VCC1 PSRR 7. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. 8. Guaranteed by design. www.onsemi.com 6 NCV7518, NCV7518A ELECTRICAL CHARACTERISTICS (continued) (4.75 V ≤ VCCX ≤ 5.25 V, VDD = VCCX, 4.5 V ≤ VLOAD ≤ 18 V, RSTB = VCCX, ENB = 0, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 7) Characteristic Symbol Conditions Min Typ Max Unit V25 Register R2.C[11:9] = 000 (DEFAULT) 20 25 30 V40 Register R2.C[11:9] = 001 35 40 45 % VFLTREF V50 Register R2.C[11:9] = 010 45 50 55 V60 Register R2.C[11:9] = 011 55 60 65 V70 Register R2.C[11:9] = 100 65 70 75 V80 Register R2.C[11:9] = 101 75 80 85 V90 Register R2.C[11:9] = 110 85 90 95 V100 Register R2.C[11:9] = 111 95 100 105 IDLKG 0 V ≤ VCC1 = VCC2 = VDD ≤ 5.25 V, RSTB = 0 V, VDRNX = 32 V TA ≤ 25°C −5.0 −1.0 − − 5.0 1.0 60 − 78 V FAULT DETECTION − GATX ON DRNX Shorted Load Threshold VFLTREF = 0.35V DRNX Input Leakage Current DRNX Clamp Voltage VCL IDRNX= ICL(MAX) =10 mA; Transient (≤2 ms, ≤1% Duty) mA Fault Detection − GATX OFF (7.5 V ≤ VLOAD ≤ 18 V, Register R3.D[11:0] = 1) ISG Short to GND Detection, VDRNX = 43%VLOAD − 81 −60 − 39 mA / V IOL Open Load Detection, VDRNX = 61%VLOAD 2.73 4.20 5.67 mA / V ICHG Transient Fast Charge Current, 0 < VDRNX < VCTR, t < tBL(OFF) −270 −200 −130 mA / V Diagnostic Current Limit Point VLIM Current Clamped and No Longer Proportional to VLOAD 20 − − V DRNX Fault Threshold Voltage VSG Short to GND Detection 39.56 43 46.44 %VLOAD VOL Open Load Detection 56.12 61 65.88 %VLOAD 46.92 51 55.08 %VLOAD DRNX Diagnostic Current − Proportional to VLOAD DRNX Off State Bias Voltage VCTR VLOAD Undervoltage Threshold VLDUV VLOAD Decreasing 4.1 6.3 7.5 V tBL(ON) VDRNX = VLOAD; INX rising to FLTB Falling Register R2.C[6:5] = 00 4.8 6 7.2 ms Register R2.C[6:5] = 01 9.6 12 14.4 Register R2.C[6:5] = 10 (DEFAULT) 19.2 24 28.8 Register R2.C[6:5] = 11 28.8 48 57.6 VDRNX = 0V; INX falling to FLTB Falling Register R2.C[8:7] = 00 44 55 66 Register R2.C[8:7] = 01 65 81 97 Register R2.C[8:7] = 10 (DEFAULT) 130 162 195 Register R2.C[8:7] = 11 260 325 390 2.0 44 3.0 55 4.0 66 ms FAULT TIMERS Channel Fault Blanking Timers (Figure 6) tBL(OFF) Channel Fault Filter Timer (Figure 7) tFF(ON) tFF(OFF) ms Global Fault Retry Timer (Figure 8) tFR Register R0.M[5:0] = 1 6 8 10 ms Timer Clock fCLK RSTB = VCC1 − 4.0 − MHz 7. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. 8. Guaranteed by design. www.onsemi.com 7 NCV7518, NCV7518A ELECTRICAL CHARACTERISTICS (continued) (4.75 V ≤ VCCX ≤ 5.25 V, VDD = VCCX, 4.5 V ≤ VLOAD ≤ 18 V, RSTB = VCCX, ENB = 0, −40°C ≤ TJ ≤ 150°C, unless otherwise specified.) (Note 7) Characteristic Symbol Conditions Min Typ Max Unit GATX Output Resistance RGATX Output High or Low 200 350 500 W GATX High Output Current IGSRC VGATX = 0 V −26.25 − −9.5 mA GATX Low Output Current IGSNK VGATX = VCC2 9.5 − 26.25 mA Turn-On Propagation Delay tP(ON) − − 1.0 ms Turn-Off Propagation Delay tP(OFF) − − 1.0 ms GATE DRIVER OUTPUTS INX to GATx (Figure 4) CSB to GATX (Figure 5) INX to GATX (Figure 4) CSB to GATX (Figure 5) Output Rise Time tR 20% to 80% of VCC2, CLOAD = 400 pF (Figure 4, Note 8) − − Output Fall Time tF 80% to 20% of VCC2, CLOAD = 400 pF (Figure 4, Note 8) − − 277 277 ns ns SERIAL PERIPHERAL INTERFACE (Figure 9) VCCX = 5.0 V, VDD = 3.3 V, FSCLK = 4.0 MHz, CLOAD = 200 pF 3.3 V Interface 3.0 3.3 3.6 V 5 V Interface 4.5 5.0 5.5 V − 250 − ns Sl, SCLK (Note 8) − − 12 pF SCLK = 2.0 V to 2.0 V 125 − − ns tCLKL SCLK = 0.8 V to 0.8 V 125 − − ns tSISU Sl = 0.8 V/2.0 V to SCLK = 2.0 V (Note 8) 25 − − ns Sl Hold Time tSIHD SCLK = 2.0 V to Sl = 0.8 V/2.0 V (Note 8) 25 − − ns SO Rise Time tSOR (20% VSO to 80% VDD) CLOAD = 200 pF (Note 8) − 25 50 ns SO Fall Time tSOF (80% VSO to 20% VDD) CLOAD = 200 pF (Note 8) − − 50 ns CSB Setup Time tCSBSU CSB = 0.8 V to SCLK = 2.0 V (Note 8) 60 − − ns CSB Hold Time tCSBHD SCLK = 0.8 V to CSB = 2.0 V (Note 8) 75 − − ns CSB to SO Time tCS−SO CSB = 0.8 V to SO Data Valid (Note 8) − 65 125 ns SO Delay Time SODLY SCLK = 0.8 V to SO Data Valid (Note 8) − 65 125 ns Transfer Delay Time CSDLY CSB Rising Edge to Next Falling Edge (Note 8) 1.6 − − ms SO Supply Voltage VDD SCLK Clock Period tSCLK Maximum Input Capacitance CINX SCLK High Time tCLKH SCLK Low Time Sl Setup Time 7. Min/Max values are valid for the temperature range −40°C ≤ TJ ≤ 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. 8. Guaranteed by design. INX 50% tP(OFF) GAT X tR 80% 20% 50% tP(ON) Figure 4. Gate Driver Timing Diagram − Parallel Input www.onsemi.com 8 tF NCV7518, NCV7518A CSB 50% DRNX GX INX 50% tP(OFF) GAT X tBL(ON) 50% FLTB tBL(OFF) 50% 50% tP(ON) Figure 5. Gate Driver Timing Diagram − Serial Input DRNX Figure 6. Blanking Timing Diagram OPEN LOAD THRESHOLD SHORTED LOAD THRESHOLD INX tFF(ON) FLTB tFF(OFF) 50% 50% Figure 7. Filter Timing Diagram GATX tBL(ON) tFR tFF tFR tBL(ON) tFR (ON) DRNX SHORTED LOAD THRESHOLD (FLTREF) INX Figure 8. Fault Retry Timing Diagram www.onsemi.com 9 NCV7518, NCV7518A CSB SETUP TRANSFER DELAY CSB SI SETUP SCLK CSB HOLD 1 16 SI HOLD SI MSB IN SO DELAY CSB to SO VALID SO LSB IN BITS 14...1 MSB OUT SO RISE,FALL BITS 14...1 LSB OUT SEE NOTE 80% VDD 20% VDD Note: Not defined but usually MSB of data just received. Figure 9. SPI Timing Diagram DETAILED OPERATING DESCRIPTION General The active-low ENB input with resistive pull-up provides a global enable. ENB disables all GATX outputs and diagnostics, and resets the auto-retry timer when brought high. The SPI is enabled, fault data is not cleared and registers remain as programmed. Faulted outputs are re-enabled when ENB goes low. The NCV7518 is a six channel general-purpose low-side pre-driver for controlling and protecting N-type logic level MOSFETs. Programmable fault detection and protection modes allow the device to accommodate a wide range of external MOSFETs and loads, providing flexible application solutions. Separate power supply pins are provided for low and high current paths to improve analog accuracy and digital signal integrity. SPI Communication The NCV7518 is a 16-bit slave device. Communication between the host and the device may either be parallel via individual CSB addressing or daisy-chained through other devices using a compatible SPI protocol. The active-low CSB chip select input has a pull-up resistor. The SI and SCLK inputs have pull-down resistors. The recommended idle state for SCLK is low. The tri-state SO line driver is powered via the VDD and the VSS pins, and can be supplied with either 3.3 V or 5 V. The device employs odd parity, and frame error detection that requires integer multiples of 16 SCLK cycles during each CSB high-low-high cycle (valid communication frame.) A parity or frame error does not affect the FLTB flag. The host initiates communication when a selected device’s CSB pin goes low. Output data is simultaneously sent MSB first from the SO pin while input data is received MSB first at the SI pin under synchronous control of the master’s SCLK signal while CSB is held low (Figure 10). Output data changes on the falling edge of SCLK and is guaranteed valid before the next rising edge of SCLK. Input data received must be valid before the rising edge of SCLK. Power Up/Down Control An internal Power-On Reset (POR) monitors VCC1 and causes all GATX outputs to be held low until sufficient voltage is available to allow proper control of the device. All internal registers are initialized to their defaults, status data is cleared, and the open-drain fault flag (FLTB) is disabled. When VCC1 exceeds the POR threshold, the device is initialized and ready to accept input data. When VCC1 falls below the POR threshold during power down, FLTB is disabled and all GATX outputs are driven and held low until VCC1 falls below about 1.5 V. RSTB and ENB Inputs The active-low RSTB input with a resistive pull-down allows device reset by an external signal. When RSTB is brought low, all GATX outputs, the timer clock, the SPI, and the FLTB flag are disabled. All internal registers are initialized to their default states, status data is cleared, and the SPI and FLTB are enabled when RSTB goes high. www.onsemi.com 10 NCV7518, NCV7518A remains latched and available for retrieval during the next valid frame. The FLTB flag will be set if a fault (not a frame or parity error) is detected. The interaction between CSB and FLTB facilitates fault polling. When multiple NCV7518 devices are configured for parallel SPI access with individual CSB addressing, the device reporting a fault can be identified by pulsing each CSB in turn. When CSB goes low, frame error detection is initialized, output data is transferred to the SPI, and the FLTB flag is disabled and reset if previously set. If a valid frame has been received when CSB goes high, the last multiple of 16 bits received is decoded into command data, and FLTB is re-enabled. The FLTB flag will be set if a fault is detected. If a frame or parity error is detected when CSB goes high, new command data is ignored, and previous fault data CSB MSB SCLK LSB 1 2 4 − 13 3 14 15 16 SI X B15 B14 B13 B12 − B3 B2 B1 B0 SO Z B15 B14 B13 B12 − B3 B2 B1 B0 X UKN Z Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data Figure 10. SPI Communication Frame Format Serial Data and Register Structure registers. The valid register addresses are shown in Table 1. The input command structure is shown in Table 3. Each register is later described in detail. The 16-bit data received by the NCV7518 is decoded into a 3-bit address, a 12-bit data word, and an odd parity bit (Figure 11). The upper three bits, beginning with the received MSB, are fully decoded to address one of eight B15 B14 B13 B12 B11 A2 A1 A0 D11 D10 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB P LSB ADDRESS INPUT DATA + PARITY ADDRESS ECHO OUTPUT DATA + PARITY MSB LSB B15 B14 B13 B12 B11 A2 B0 A1 A0 D11 D10 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P Figure 11. SPI Data Format www.onsemi.com 11 NCV7518, NCV7518A Table 1. VALID REGISTER ADDRESSES Type Alias A2 A1 A0 GATE & MODE SELECT Function W R0 0 0 0 DIAGNOSTIC PULSE W R1 0 0 1 DIAGNOSTIC CONFIG 1 W R2 0 1 0 DIAGNOSTIC CONFIG 2 W R3 0 1 1 STATUS CH2:0 R R4 1 0 0 STATUS CH5:3 R R5 1 0 1 REVISION INFO R R6 1 1 0 TEST R7 1 1 1 RESERVED The 16-bit data sent by the NCV7518 is an echo of the previously received 3-bit address with the remainder of the 12-bit data and parity bit formatted into one of four response types − an echo of the previously received input data, the diagnostic status information, the device revision information, or a transmission error (Table 2). The first response frame sent after reset (via POR or RSTB) is the device revision information. Table 2. OUTPUT RESPONSE TYPES ECHO RESPONSE A2 A1 A0 D11 D10 D9 D8 D7 D6 ADDRESS ECHO D5 D4 D3 D2 D1 D0 INPUT DATA ECHO P ? DIAGNOSTIC STATUS RESPONSE 1 0 0 0 0 ENB CH2 CH1 CH0 CH2 CH1 CH0 CH2 CH1 CH0 ? 1 0 1 0 0 ENB CH5 CH4 CH3 CH5 CH4 CH3 CH5 CH4 CH3 ? D0 ? ST2 ST1 ST0 DEVICE REVISION RESPONSE 1 1 0 0 0 0 0 0 0 D5 D4 D3 DIE REVISION D2 D1 MASK REVISION TRANSMISSION ERROR RESPONSE 1 1 1 0 1 0 1 0 1 0 1 0 1 0 PARITY ERROR 1 1 1 0 1 0 1 0 1 FRAME ERROR www.onsemi.com 12 0 1 0 1 0 D0 P 1 0 D0 P 0 1 NCV7518, NCV7518A Table 3. INPUT COMMAND STRUCTURE OVERVIEW ALIAS 3-BIT ADDR 12-BIT COMMAND INPUT DATA ODD PARITY A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 0 0 M5 M4 M3 M2 M1 M0 G5 G4 G3 G2 G1 G0 ? R0 GATE & MODE SELECT 1 = AUTO RETRY DEFAULT = LATCH OFF 1 = GATx ON DEFAULT = ALL OFF A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 0 1 F5 F4 F3 F2 F1 F0 N5 N4 N3 N2 N1 N0 ? R1 DIAGNOSTIC PULSE 1 = DIAGNOSTIC OFF PULSE DEFAULT = 0 1 = DIAGNOSTIC ON PULSE DEFAULT = 0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 1 0 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 ? R2 DIAGNOSTIC CONFIG 1 A2 A1 %VFLTREF SELECT A0 D11 D10 TBLANK OFF D9 D8 D7 CH2 CH 1 R3 0 1 1 CH5 CH4 CH3 TBLANK ON D6 CH0 NOT USED D5 D4 D3 D2 D1 D0 P CH5 CH 4 CH 3 CH 2 CH 1 CH 0 ? 1 = ENABLE FAST CHARGE DEFAULT = DISABLE DIAGNOSTIC CONFIG 2 CHANNEL SELECT 1 = ENABLE DIAGNOSTIC DEFAULT = ENABLE OPEN LOAD DIAGNOSTIC ENABLE/DISABLE A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 0 0 X X X X X X X X X X X X ? R4 DIAGNOSTIC STATUS CH2:CH0 RETURN ENB STATUS; D[9] = 0 = ENABLED RETURN CH2:CH0 STATUS; DEFAULT D[8:0] = 1 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 0 1 X X X X X X X X X X X X ? R5 DIAGNOSTIC STATUS CH5:CH3 RETURN ENB STATUS; D[9] = 0 = ENABLED RETURN CH5:CH3 STATUS; DEFAULT D[8:0] = 1 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 1 0 X X X X X X X X X X X X ? R6 REVISION INFORMATION RETURN REVISION INFORMATION A2 A1 A0 D11 D10 D9 D8 1 1 1 T11 T10 T9 T8 D7 D6 D5 D4 D3 D2 D1 D0 P T7 T6 T5 T4 T3 T2 T1 T0 ? R7 RESERVED RESERVED FOR TEST MODE Gate & Mode Select − Register R0 The disable mode for shorted load (on-state) faults is controlled by each channel’s respective MX bit. Setting R0.MX = 0 causes the selected GATX output to latch-off when a fault is detected. Setting R0.MX = 1 causes the selected GATX output to auto-retry when a fault is detected. Recovery from latch-off is performed for all channels by disabling then re-enabling the device via the ENB input. Recovery for selected channels is performed by reading the status registers (R4, R5) for the faulted channels then executing a diagnostic ON or OFF pulse for the desired channels. Each GATX output is turned on/off serially by programming its respective GX bit (Table 4). When parallel inputs INX = 0, setting R0.GX = 1 causes the selected GATX output to drive its external MOSFET’s gate to VCC2 (ON). Setting R0.GX = 0 causes the selected GATX output to drive its external MOSFET’s gate to VSS (OFF.) Note that the actual state of the output depends on POR, RSTB, ENB and shorted load fault states (SHRTX) as later defined by Equation 1. Default after reset is R0.D[11:0] = 0 (all channels latch-off mode, all outputs OFF.) R0 is an echo type response register. www.onsemi.com 13 NCV7518, NCV7518A When auto-retry is selected, input changes for turn-on time are ignored while the retry timer is active. Once active, the timer will run to completion of the programmed time. The output will follow the input at the end of the retry interval. The timer is reset when ENB = 1 or when the mode is changed to latch-off. Table 4. GATE & MODE SELECT REGISTER R0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 0 0 M5 M4 M3 M2 M1 M0 G5 G4 G3 G2 G1 G0 ? 1 = AUTO RETRY DEFAULT = LATCH OFF Diagnostic Pulse Select − Register R1 1 = GATx ON DEFAULT = ALL OFF timer is active); the selected channels are currently under auto-retry control (i.e. refresh timer is active). When R1.FX = 1, the diagnostic OFF pulse command is executed. The open load diagnostic is turned on if disabled (see Diagnostic Config 2 − R3), the output changes state for the programmed tBL(OFF) blanking period, and the diagnostic status is latched if of higher priority than the previous status. ICHG current is turned on if enabled via R3. The output assumes the currently commanded state at the end of the pulse. When R1.NX = 1, the diagnostic ON pulse command is executed. The output changes state for the programmed tBL(ON) blanking period, and the diagnostic status is latched if of higher priority than the previous status. The output assumes the currently commanded state at the end of the pulse. A flowchart for the diagnostic pulse is given in Figure 16. The NCV7518 has functionality to perform either on-state or off-state diagnostic pulses (Table 5) The function is provided for applications having loads normally in a continuous on or off state. The diagnostic pulse function is available for both latch-off and auto-retry modes. The pulse executes for the selected channel(s) on low-high transition on CSB. Default after reset is R1.D[11:0] = 0. R1 is an echo type response register. Diagnostic pulses have priority and are not dependant on the input (INX, GX) or the output (GATX) states. The pulse does not execute if: ENB =1 (device is disabled); both an ON and OFF pulse is simultaneously requested for the same channel; an ON or OFF pulse is requested and a SCB (shorted load) diagnostic code is present for the selected channels; an ON or OFF pulse is requested while a pulse is currently executing in the selected channels (i.e. a blanking Table 5. DIAGNOSTIC PULSE SELECT REGISTER R1 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 0 1 F5 F4 F3 F2 F1 F0 N5 N4 N3 N2 N1 N0 ? 1 = DIAGNOSTIC OFF PULSE DEFAULT = 0 Diagnostic Config 1 − Register R2 1 = DIAGNOSTIC ON PULSE DEFAULT = 0 select the fault reference (Table 9). Default after reset is indicated by “(DEF)” in the tables. R2 is an echo type response register. If a blanking timer is currently running when the register is changed, the new value is accepted but will not take effect until the next activation of the timer. The diagnostic Config 1 register programs the turn-on/off blanking time and shorted load fault detection references for each channel (Table 6) Bits R2.C[2:0] select which channels receive the configuration data (Table 7). Bits R2.C[8:5] select turn-on/off blanking time (Table 8). Bits R2.C[11:9] Table 6. DIAGNOSTIC CONFIG 1 REGISTER R2 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 1 0 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 ? %VFLTREF SELECT TBLANK OFF TBLANK ON www.onsemi.com 14 NOT USED CHANNEL SELECT NCV7518, NCV7518A Table 7. CHANNEL SELECT C2 C1 C0 CHANNEL SELECT 0 0 0 NONE 0 0 1 CHANNEL 0 0 1 0 CHANNEL 1 0 1 1 CHANNEL 2 1 0 0 CHANNEL 3 1 0 1 CHANNEL 4 1 1 0 CHANNEL 5 1 1 1 ALL (DEF) Table 8. BLANKING TIME SELECT C8 C7 C6 C5 C4 C3 X X TBLANK OFF TBLANK ON 6 ms 0 0 0 1 12 ms 1 0 24 ms (DEF) 1 1 48 ms 0 0 55 ms 0 1 81 ms 1 0 162 ms (DEF) 1 1 325 ms Table 9. FAULT REFERENCE SELECT C11 C10 C9 %VFLTREF SELECT 0 0 0 25 (DEF) 0 0 1 40 0 1 0 50 0 1 1 60 1 0 0 70 1 0 1 80 1 1 0 90 1 1 1 100 Diagnostic Config 2 − Register R3 status (OLF) information is suppressed when the diagnostic is turned off via R3. Open load diagnostic and OLF status is temporarily enabled when a diagnostic off pulse is executed via R1. Default after reset is R3.D[11:6] = 0 and R3.D[5:0] = 1. R3 is an echo type response register. Off-state open load diagnostic currents for each channel can be enabled or disabled for LED loads. Short to GND diagnostic is unaffected. Fast charge current (ICHG) can be enabled or disabled for capacitive loads. Channels are selected by bit positions in the register (Table 10.) Open load www.onsemi.com 15 NCV7518, NCV7518A Table 10. DIAGNOSTIC CONFIG 2 REGISTER R3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 0 1 1 CH5 CH4 CH3 CH2 CH1 CH0 CH5 CH4 CH3 CH2 CH1 CH0 ? 1 = ENABLE FAST CHARGE DEFAULT = DISABLE 1 = ENABLE DIAGNOSTIC DEFAULT = ENABLE OPEN LOAD DIAGNOSTIC ENABLE/DISABLE Diagnostic Status Registers − Register R4 & R5 encoded (Table 12). Bit D[9] returns the state of the ENB input e.g. D[9] = 0 when ENB = 0 (enabled). Default response after reset or SPI read is D[8:0] = 1 (“Diagnostic Not Complete”). Diagnostic status and ENB status information is returned when R4 or R5 is selected (Table 11) Diagnostic status information for each channel is 3-bit (ST2:0) priority Table 11. DIAGNOSTIC STATUS REGISTERS R4 R5 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 0 0 X X X X X X X X X X X X ? SI 1 0 0 0 0 ENB CH2 CH1 CH0 CH2 CH1 CH0 CH2 CH1 CH0 ? SO 1 0 1 X X X X X X X X X X X X ? SI 1 0 1 0 0 ENB CH5 CH4 CH3 CH5 CH4 CH3 CH5 CH4 CH3 ? SO ST2 ST1 ST0 Table 12. DIAGNOSTIC STATUS ENCODING ST2 ST1 ST0 0 0 0 INVALID 0 0 1 SCB − SHORT TO BATTERY 0 1 0 SCG − SHORT TO GROUND 0 1 1 OLF − OPEN LOAD 1 0 0 Diagnostic Complete − No Fault 4 1 0 1 No SCB Fault − ON State 5 1 1 0 No SCG/OLF Fault − OFF State 6 1 1 1 Diagnostic Not Complete (DEFAULT) NOTE: STATUS PRIORITY − 1 HIGHEST 2 3 (Note) 7 LOWEST OLF status report is suppressed when open load diagnostic is turned off via Diagnostic Config 2 − register R3 Status is latched for the currently higher priority fault and is not demoted if a fault of lower priority occurs. The status registers are reset to “Diagnostic Not Complete” after reading the registers, or by asserting a reset via RSTB. Status registers are not affected by ENB. bits D[5:3] are hard coded with the die (silicon) revision, and bits D[2:0] are hard coded with the mask (interconnect) revision. The first response frame sent after reset is the device revision information. The revision encoding scheme is shown in Table 14. Mask revision may be incremented when an interconnect revision is made. Die revision is incremented when a silicon revision is made. Mask revision is reset to “000” when a die revision is made. Revision Information − Register R6 Device revision information is returned when R6 is selected (Table 13). Output bits D[11:6] are hard coded to 0, Table 13. DEVICE REVISION INFORMATION R6 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 1 0 X X X X X X X X X X X X ? SI 1 1 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 ? SO DIE REV www.onsemi.com 16 MASK REV NCV7518, NCV7518A Table 14. DEVICE REVISION ENCODING D5 D4 D3 D2 DIE D1 REV D0 MASK REV 0 0 0 A 0 0 0 0 0 0 1 B 0 0 1 1 0 1 0 C 0 1 0 2 0 1 1 D 0 1 1 3 1 0 0 E 1 0 0 4 1 0 1 F 1 0 1 5 1 1 0 G 1 1 0 6 1 1 1 H 1 1 1 7 Reserved − Register R7 Register R7 is reserved for factory test use. Data sent to R7 is ignored. In normal operation, R7 is an echo type response register. In the event of a transmission error, R7 responds with either a parity or frame error on the next valid frame. Table 15. TEST MODE REGISTER R7 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 1 1 X X X X X X X X X X X X ? SI ? SO ECHO INPUT DATA ECHO PARITY ERR 0 1 0 1 0 1 0 1 0 1 0 1 0 SO FRAME ERR 0 1 0 1 0 1 0 1 0 1 0 0 1 SO Gate Driver Control and Enable The INX input state and the GX register bit data are logically combined with the internal (active low) power-on reset signal (POR), the RSTB and ENB input states, and the shorted load state (internal SHRTX) to control the corresponding GATX output such that: Each GATX output may be turned on by either its respective parallel INX input or the Gate & Mode Select register bits R0.G[5:0] via SPI communication. The device’s RSTB reset and ENB enable inputs can be used to implement global control functions, such as system reset, over-voltage or input override by a watchdog controller. The RSTB input has an internal pull-down resistor and the ENB input has an internal pull-up resistor. Each parallel input has an internal pull-down resistor. Parallel input is recommended when low frequency (≤ 10 kHz) PWM operation of the outputs is desired. Unused parallel inputs should be connected to GND. When RSTB is brought low, all GATX outputs, the timer clock, the SPI, and the FLTB flag are disabled. All internal registers are initialized to their default states, status data is cleared, and the SPI and FLTB are enabled when RSTB goes high. ENB disables all GATX outputs and diagnostics, and resets the auto-retry timer when brought high. The SPI is enabled, fault data is not cleared and registers remain as programmed. Faulted outputs are re-enabled when ENB goes low. (eq. 1) GAT X + POR @ RSTB @ ENB @ SHRT X @ ǒIN x ) G XǓ The GATX state truth table is given in Table 16. www.onsemi.com 17 NCV7518, NCV7518A Table 16. GATE DRIVER TRUTH TABLE POR RSTB ENB SHRTX INX GX GATX 0 X X X X X L 1 0 X X X X L 1 1 1 X X X L 1 1 0 1 0 0 L 1 1 0 1 1 X H 1 1 0 1 X 1 H 1 1 0 0 X X →L 1 1 0→1 X X GX →L 1 1 1→0 →1 0 GX →GX 1 1→0 X X X →0 →L Gate Drivers The non-inverting GATX drivers are symmetrical resistive switches (350 W typ.) to the VCC2 and VSS voltages. While the outputs are designed to provide symmetrical gate drive to an external MOSFET, load current R3.D[X,X+6] R2.C[11:9] STX[2:0] R0.M[X] R1.F|N[X] INX GX RSTB ENB POR FAULT DETECTION FILTER TIMER ENCODING LOGIC DRNX BLANKING TIMER R2.C[8:5] R2.C[4:3] switching symmetry is dependent on the characteristics of the external MOSFET and its load. Figure 12 shows the gate driver block diagram. LATCH OFF / AUTO RE−TRY EN SHRT X VSS VCC2 DRIVER DIAGNOSTIC PULSE EN 350 GAT X VSS Figure 12. Gate Driver Channel Blanking and Filter Timers If a blanking timer is currently running when the register is changed, the new value is accepted but will not take effect until the next activation of the timer. Blanking timers for all channels are started when both RSTB goes high and ENB goes low, when RSTB goes high while ENB is low, when ENB goes low while RSTB is high, or by POR. Blanking timers are used to allow drain feedback to stabilize after a channel is commanded to change states. Filter timers are used to suppress glitches while a channel is in a stable state. A turn-on blanking timer is started when a channel is commanded on. Drain feedback is sampled after tBL(ON). A turn-off blanking timer is started when a channel is commanded off. Drain feedback is sampled after tBL(OFF). A filter timer is started when a channel is in a stable state and a fault detection threshold associated with that state has been crossed. Drain feedback is sampled after tFF(ON|OFF). A filter timer may also be started while a blanking timer is active, so the blanking interval could be extended by the filter time. Each channel has independent blanking and filter timers. The parameters for the tFF(ON|OFF) filter timer are the same for all channels. The turn-on/off blanking time for each channel can be selected via the Diagnostic Config 1 register bits R2.C[8:5] (Tables 6 and 8). Fault Diagnostics and Behavior Each channel has independent fault diagnostics and employs blanking and filter timers to suppress false faults. An external MOSFET is monitored for fault conditions by connecting its drain to a channel’s DRNX feedback input through an optional external series resistor. Shorted load (or short to VLOAD) faults can be detected when a driver is on. Open load or short to GND faults can be detected when a driver is off. On-state faults will initiate MOSFET protection behavior, set the FLTB flag and the respective channel’s status bits in www.onsemi.com 18 NCV7518, NCV7518A range of 0.35 to 2.75 V and can be derived via a voltage divider between VCC1 and GND. Shorted load detection thresholds can be programmed via SPI in eight increments that are ratiometric to the applied FLTREF voltage. Separate thresholds can be selected for each channel via the Diagnostic Config 1 register bits R2.C[11:9] (Tables 6 and 9). A shorted load fault is detected when a channel’s DRNX feedback is greater than its selected fault reference after either the turn-on blanking or the filter has timed out. the device’s status registers. Off-state faults will simply set the FLTB flag and the channel’s status bits. Status information is retrieved by SPI read of registers R4 and R5 (Table 11). Status information for each channel is 3-bit priority encoded (Table 12). Shorted load fault has priority over open load and short to GND. Short to GND has priority over open load. Priority ensures that the most severe fault data is available at the next SPI read. Status is latched for the currently higher priority fault and is not demoted if a fault of lower priority occurs. The status registers are reset to “Diagnostic Not Complete” after reading the registers, or by asserting a reset via RSTB. Status registers are not affected by ENB. When either RSTB is low or ENB is high, diagnostics are disabled. When RSTB is high and ENB is low, open load diagnostics are enabled according to the state of the Diagnostic Config 2 register bits R3.D[5:0] (Table 10). Shorted Load Fault Disable and Recovery Shorted load fault disable mode for each channel is individually SPI programmable via the device’s Gate & Mode select register bits R0.M[5:0] (Table 4). When latch-off mode (default) is selected, the corresponding GATX output is latched off upon detection of a fault. Recovery from latch-off is performed for all channels by disabling then re-enabling the device via the ENB input. Recovery for selected channels is performed by reading the status registers (R4, R5) for the faulted channels then executing a diagnostic ON or OFF pulse for the desired channels. When auto-retry mode is selected the corresponding GATX output is turned off upon detection of a fault for the duration of the fault retry time (tFR). When auto-retry is selected, input changes for turn-on blanking time are ignored while the retry timer is active. Once active, the timer will run to completion of the programmed time. The output will follow the input at the end of the retry interval. The timer is reset when ENB = 1 or when the mode is changed to latch-off. The output is automatically turned back on (if still commanded on) when the retry time ends. The channel’s DRNX feedback is re-sampled after the turn-on blanking time. The output will automatically be turned off if a fault is again detected. This behavior will continue for as long as the channel is commanded on and the fault persists. In either mode, a fault may exist at turn-on or may occur some time afterward. To be detected, the fault must exist longer than either tBL(ON) at turn-on or longer than tFF(ON) some time after turn-on. The length of time that a MOSFET stays on during a shorted load fault is thus limited to either tBL(ON) or tFF(ON). Diagnostic Pulse Mode The NCV7518 has functionality to perform either on-state or off-state diagnostic pulses (Table 5). The function is provided for applications having loads normally in a continuous on or off state. The diagnostic pulse function is available for both latch-off and auto-retry modes. The pulse executes for the selected channel(s) on low-high transition on CSB. Diagnostic pulses have priority and are not dependant on the input (INX, GX) or the output (GATX) states. The pulse does not execute if: ENB =1 (device is disabled); both an ON and OFF pulse is simultaneously requested for the same channel; an ON or OFF pulse is requested and a SCB (shorted load) diagnostic code is present for the selected channels; an ON or OFF pulse is requested while a pulse is currently executing in the selected channels (i.e. a blanking timer is active); the selected channels are currently under auto-retry control (i.e. refresh timer is active). When R1.FX = 1, the diagnostic OFF pulse command is executed. The open load diagnostic is turned on if disabled (see Diagnostic Config 2 − R3), the output changes state for the programmed tBL(OFF) blanking period, and the diagnostic status is latched if of higher priority than the previous status. ICHG current is turned on if enabled via R3. The output assumes the currently commanded state at the end of the pulse. When R1.NX = 1, the diagnostic ON pulse command is executed. The output changes state for the programmed tBL(ON) blanking period, and the diagnostic status is latched if of higher priority than the previous status. The output assumes the currently commanded state at the end of the pulse. A flowchart for the diagnostic pulse is given in Figure 16. Recovery Retry Time A global retry timer is used for auto-retry timing. The first faulted channel triggers the timer and the full retry time is guaranteed for that channel. An additional faulted channel may initially retry immediately after its turn-on blanking time, but subsequent retries will have the full retry time. If all channels become faulted, they will become synchronized to the global retry timer. Shorted Load Detection An external reference voltage applied to the FLTREF input serves as a common reference for all channels (Figures 1 and 2). The FLTREF voltage should be within the www.onsemi.com 19 NCV7518, NCV7518A Open Load and Short to GND Detection less than the VSG short to GND reference, a short to GND fault is detected. If the feedback is less than VOL and greater than VSG, an open load fault is detected. When either RSTB is low or ENB is high, diagnostics are disabled. When RSTB is high and ENB is low, off-state diagnostics are enabled according to the content of the Diagnostic Config 2 register bits R3.D[11:0] (Tables 10 and 17.) A window comparator with references and bias currents proportional to VLOAD is used to detect open load or short to GND faults when a channel is off. Each channel’s DRNX feedback is compared to the references after either the turn-off blanking or the filter has timed out. Figure 13 shows the DRNX bias and fault detection zones. IDRNX IOL Short to GND Open Load Table 17. OPEN LOAD DIAGNOSTIC CONTROL (CH0 shown) No Fault ICHG CURRENT OPEN LOAD DIAGNOSTIC D6 D0 X 0 OFF X 1 ON 0 X OFF 1 X ON 0 -ISG (DEF) (DEF) VDRNX VSG V CTR V OL Figure 14 shows the simplified detection circuitry. Bias currents ISG and IOL are applied to a bridge along with bias voltage VCTR. Transient fast charge current ICHG is supplied to help charge any capacitance present at the DRNx node to suppress a false short to GND fault. Figure 13. DRNX Bias and Fault Detection Zones No fault is detected if the feedback voltage at DRNX is greater than the VOL open load reference. If the feedback is VBAT DX1 VLOAD RSTB ENB R1.D[6,0] R3.D[6,0] tBL(OFF) CONTROL LOGIC S1 S2 R1 A − VOL + R2 CMP1 S4 ISG VLD ICHG S5 D3 RLD D5 D1 DRNX + B CMP2 − + R3 VSG DZ1 OA − D4 D2 (VCL) R4 VCTR IOL VX RDX RSG CESD ±VOS S3 Figure 14. Short to GND/Open-Load Detection The transient current is started when a channel’s turn-off blanking time is started and terminated either when the DRNx voltage reaches VCTR or when the turn-off blanking time tBL(OFF) expires. VDRNX will remain at VCTR if an open load truly exists, otherwise the capacitance can continue to charge via RLD. When a channel is off and VLD and RLD are present, RSG is absent, and VDRNX >> VCTR, bias current IOL is supplied from VLD to ground through resistors RLD and optional RDX, and bridge diode D2. Bias current ISG is supplied from VLOAD to VCTR through D3. No fault is detected if the feedback voltage (VLD minus the total voltage drop caused by IOL and the resistance in the path) is greater than VOL. When RSG and either VLD or RLD are absent, the bridge will self-bias so that VDRNX will settle to about VCTR. An open load fault can be detected since the feedback is between VSG and VOL. Short to GND detection can tolerate up to a ±1.0 V offset (VOS) between the NCV7518’s GND and the short. When RSG is present and VDRNX VOL L Z ST[2:0] FLTB RESET 1 1 0 1 0 0 VSG < V < VOL L L → 011 FLTB SET − OLF 1 1 0 1→0 0 0 VSG < V < VOL L L→Z 011 FLTB RESET 1 1 0 0→1 0 0 VSG < V < VOL L Z→L 011 FLTB SET 1 1 0 1 0 0 < VSG L L → 010 FLTB SET − SCG 1 1 0 1→0 0 0 < VSG L L→Z 010 FLTB RESET 1 1 0 0→1 0 0 < VSG L Z→L 010 FLTB SET 1 1 0 X 1 X < VFLTREF H Z ST[2:0] FLTB RESET 1 1 0 1 1 X > VFLTREF L L → 001 FLTB SET − SCB 1 1 0 1→0 1 X > VFLTREF L L→Z 001 FLTB RESET 1 1 0 0→1 1 X > VFLTREF L Z→L 001 FLTB SET 1 1 0 1 X 1 < VFLTREF H Z ST[2:0] FLTB RESET 1 1 0 1 X 1 > VFLTREF L L → 001 FLTB SET − SCB 1 1 0 1→0 X 1 > VFLTREF L L→Z 001 FLTB RESET 1 1 0 0→1 X 1 > VFLTREF L Z→L 001 FLTB SET *Output states after blanking and filter timers end and when channel is set to latch-off mode. www.onsemi.com 25 NCV7518, NCV7518A APPLICATION GUIDELINES General Auto−retry and OFF Pulse Interaction Unused DRNX inputs should be connected to VLOAD to prevent false open load faults. Unused parallel inputs should be connected to GND and unused reset or enable inputs should be connected to VCC1 or GND respectively. The user’s software should be designed to ignore fault information for unused channels. For best shorted-load detection accuracy, the external MOSFET source terminals should be star-connected and the NCV7518’s GND pin, and the lower resistor in the fault reference voltage divider should be Kelvin connected to the star (see Figure 2). Consideration of auto-retry fault recovery behavior is necessary from a power dissipation viewpoint (for both the NCV7518 and the MOSFETs) and also from an EMI viewpoint. Driver slew rate and turn-on/off symmetry can be adjusted externally to the NCV7518 in each channel’s gate circuit by the use of series resistors for slew control, or resistors and diodes for symmetry. Any benefit of EMI reduction by this method comes at the expense of increased switching losses in the MOSFETs. The channel fault blanking timers must be considered when choosing external components (MOSFETs, slew control resistors, etc.) to avoid false faults. Component choices must ensure that gate circuit charge/discharge times stay within the turn-on/turn-off blanking times. The NCV7518 does not have integral drain-gate flyback clamps. Self-clamped MOSFET products, such as ON Semiconductor’s NIF9N05CL or NCV8440A devices, are recommended when driving unclamped inductive loads. This flexibility allows choice of MOSFET clamp voltages suitable to each application. A single hardware implementation serves as the global auto−retry (tFR) timer function for all channels and within each channel the turn−on (tBL(ON)) and turn−off (tBL(OFF)) blanking timers are shared (single hardware implementation) with tBL(ON) time dominant. These same blanking timers also generate the ON or OFF diagnostic pulses. If a channel configured for auto−retry is continuously commanded ON and becomes faulted (SCB), it remains ON and a turn−on blanking time is initiated every 8 ms for the faulted channel and also for each non−faulted ON channel configured for auto−retry. If a channel configured for auto−retry is commanded OFF, it remains OFF and no blanking timers are started. When a diagnostic OFF pulse request is received just prior to an auto−retry cycle, the channel’s tBL(OFF) timer can be interrupted by the auto−retry timer (tBL(ON) blanking time initiation). For example, a channel’s tBL(OFF) timer is programmed for 162 ms and an OFF pulse is requested and begins execution, but before it can complete its timeout, the auto−retry initiates a tBL(ON) blanking time. Due to the blanking timer sharing, the tBL(OFF) timer does not complete its timeout and the pulse request becomes locked out. The number of locked−out channels depends on which ones were programmed for auto−retry and which ones were requesting an OFF−pulse within the described zone of vulnerability. Further OFF pulse requests will fail to execute for each locked−out channel. This interaction can be avoided for channels operated in a constant−on state by selecting the latch−off recovery mode and emulating the auto−retry mode. This can be done by sending a series of read status and diagnostic pulse execution requests with appropriate delays on a scheduled (e.g. every 10 ms) basis. Global recovery may also be performed disabling then re−enabling the device via the ENB input. Latch−off Recovery and PWM Operation When a channel is latched off and the recovery method chosen is the diagnostic pulse, the recovery attempt can be blocked by a PWM or other signal transition at the channel’s parallel INx input. The transition starts an ON or OFF blanking timer which will prevent execution of a pulse request if the request via SPI is received while the timer is running. This can be overcome by first sending Gx = 1 via SPI (i.e. serial control) to override the channel’s INx input, reading the diagnostic registers, then sending a pulse request. The channel can then be released back to parallel control by sending Gx = 0. Delays are added as necessary for the appropriate blanking times between each step. Global recovery may also be performed disabling then re−enabling the device via the ENB input. Parity Error Handling The SPI input (SI) shift register is reset (forced to 0x00) in case of an invalid frame resulting from either an incorrect frame length or incorrect parity. The ‘live’ parity check hardware implementation of the SI register content is blocked during a frame by CSB. When CSB goes high and the frame length is correct but parity is incorrect, parity check inputs may change as the SI register is forced to 0x00 and register data may be affected. In the event a parity error occurs it is recommended to refresh all of the device’s configuration (write) registers. Register data is not affected if the frame length is incorrect. www.onsemi.com 26 NCV7518, NCV7518A Appendix A − Diagnostic and Protection Behavior Tutorial Initial Conditions: The following tutorial can be used together with Table 19 and the Statechart of Figure 17 to further understand how diagnostic status information is updated. ♦ Digital core is disabled if these conditions are not valid • VCC2 present and in specified range • VLOAD present and in specified range ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ VFLTREF present and in specified range INx OR Gx = 1 AND ENB 1 → 0 ENB = 0 AND INx OR Gx 0 → 1 ENB = 0 AND ON-State Diagnostic Pulse Request Blanking and/or Filter timer ran till end √ “Diagnostic Complete” • VCC1 > V(POR) AND RSTB = 1 ON-State Diagnostic: • SCB − Short Circuit to Battery • Qualifiers: OFF-State Diagnostic: • OLF/SCG − Open Load Fault / Short Circuit to GND • Qualifiers: VLOAD present and in specified range INx AND Gx = 0 AND ENB 1 → 0 ENB = 0 AND INx 1 → 0 AND Gx = 0 ENB = 0 AND INx = 0 AND Gx 1 → 0 ENB = 0 AND OFF-State Diagnostic Pulse Request Blanking and/or Filter timer ran till end √ “Diagnostic Complete” Transition Trigger Events: • Diagnostic status can transition from one state to another by several trigger events: ♦ ON and/or OFF state diagnostic completed ♦ SPI Read of the status register(s) ♦ Recovery from VLOAD undervoltage detected ♦ Reset via POR or RSTB Table 19. DIAGNOSTIC STATE TRANSITIONS Entering State Description Entering Criteria Exiting Criteria Exiting State 001 [SCB] − Short Circuit to Battery SCB Detected READ 111 010 [SCG] − Short Circuit to Ground SCG Detected SCB Detected READ 001 111 011 [OLF] − Open Load Failure OLF Detected SCB Detected SCG Detected READ 001 010 111 100 Diagnostic Complete − No Fault OFF State No Fault AND ON State No Fault SCB Detected SCG Detected OLF Detected READ 001 010 011 111 101 No SCB Detected ON State No Fault SCB Detected SCG Detected OLF Detected OFF State No Fault READ 001 010 011 100 111 www.onsemi.com 27 NCV7518, NCV7518A Table 19. DIAGNOSTIC STATE TRANSITIONS Entering State Description Entering Criteria Exiting Criteria Exiting State 110 No SCG/OLF Detected OFF State No Fault SCB Detected SCG Detected OLF Detected ON State No Fault READ 001 010 011 100 111 111 Diagnostic Not Complete READ SCB Detected & ENB = 0 SCG Detected & ENB = 0, VLOAD > VLDUV OLF Detected & ENB = 0, VLOAD > VLDUV ON State No Fault & ENB = 0 OFF State No Fault & ENB = 0, VLOAD > VLDUV 001 010 011 101 110 Diagnostic Status and Protection Interactions • ENB = 0 • SPI Response is shown in-frame The following figures are graphical representations of some interactions between diagnostics and protections. The following assumptions apply: ♦ Actual NCV7518 response is one frame behind • SPI Frames are always valid ♦ Integer multiples of 16 SCLK cycles ♦ No parity errors www.onsemi.com 28 NCV7518, NCV7518A 1 INx 0 1 DRNx GATx 0 VBAT VOL VOL FLTREF VSG 0 1 INTERNAL SIGNALS RSTB 0 BLANK 1 TIMER 0 tBL(ON) t BL(OFF ) FILTER 1 TIMER 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 DIAG 1 STATUS 0 NO FAULT 110 100 NO SCG/OLF FAULT 111 110 111 110 1 CSB 0 1 SO 100 0 110 1 FLTB 0 Start ON Normal Cycle1 Figure 18. Normal Start-up out of Reset with Input High − Diagnostics Complete, No Fault 1 INx 0 1 DRNx GATx 0 VBAT VOL VOL FLTREF VSG 0 1 RSTB 0 INTERNAL SIGNALS TRUNCATED BLANK 1 TIMER 0 tBL(ON ) t BL(OFF ) FILTER 1 TIMER 0 DIAG NOT COMPLETE DIAG 1 STATUS 0 NO SCG/OLF FAULT 111 NO SCG/OLF FAULT 110 111 110 111 110 1 CSB 0 1 SO 110 0 110 1 FLTB 0 Start ON Normal Cycle 2 Figure 19. Normal Start-up Out of Reset with Input High, tBL(ON) Truncated − SCB Not Checked www.onsemi.com 29 NCV7518, NCV7518A 1 INx 0 1 DRNx GATx 0 VBAT VOL VOL VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 BLANK 1 TIMER 0 tBL(ON ) t BL(OFF ) FILTER 1 TIMER 0 DIAG NOT COMPLETE DIAG 1 STATUS 0 111 NO SCG/OLF FAULT 110 NO FAULT 101 100 NO SCB FAULT 111 101 111 101 1 CSB 0 1 SO 100 0 101 1 FLTB 0 Start OFF Normal Cycle 1 Figure 20. Normal Start-up Out of Reset with Input Low − Diagnostics Complete, No Fault 1 INx 0 1 DRNx GATx 0 VBAT VOL VOL VSG FLTREF 0 1 RSTB 0 INTERNAL SIGNALS TRUNCATED BLANK 1 TIMER 0 tBL(OFF ) tBL(ON ) FILTER 1 TIMER 0 DIAG 1 STATUS 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 NO SCB FAULT 111 101 111 101 1 CSB 0 1 SO 101 0 101 1 FLTB 0 Start OFF Normal Cycle 2 Figure 21. Normal Start-up Out of Reset with Input Low, tBL(OFF) Truncated − SCG/OLF Not Checked www.onsemi.com 30 NCV7518, NCV7518A 1 INx Don’t Care 0 1 GATx 0 DRNx VBAT VOL VOL FLTREF VSG 0 1 RSTB 0 INTERNAL SIGNALS TRUNCATED BLANK 1 TIMER 0 tBL(OFF) FILTER 1 TIMER 0 tBL(ON) tBL(ON) tBL(OFF) tFF(ON) DIAG 1 STATUS 0 NO FAULT SCB FAULT DIAG NOT COMPLETE NO SCB FAULT 100 001 111 101 NO FAULT 110 100 1 CSB 0 ON Pulse Req 1 SO 001 0 ECHO 1 FLTB 0 SCB Latch & Clear 1 Figure 22. SCB Latch-off & Recovery − Read Status & Request ON Pulse 1 INx Don’t Care 0 1 GATx 0 DRNx VBAT VOL VOL FLTREF VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 BLANK 1 TIMER 0 tBL(OFF) FILTER 1 TIMER 0 DIAG 1 STATUS 0 tBL(ON) tFF(ON) NO FAULT SCB FAULT DIAG NOT COMPLETE NO SCG/OLF FAULT 100 001 111 110 NO FAULT 101 100 1 CSB 0 OFF Pulse Req 1 SO 0 001 ECHO 1 FLTB 0 SCB Latch & Clear 2 Figure 23. SCB Latch-off & Recovery − Read Status & Request OFF Pulse www.onsemi.com 31 NCV7518, NCV7518A 1 INx Don’t Care 0 1 GATx 0 DRNx VBAT VOL VOL FLTREF VSG 0 1 INTERNAL SIGNALS RSTB 0 BLANK/ 1 REFRESH TIMER 0 t FR FILTER 1 TIMER 0 DIAG 1 STATUS 0 tFF(ON) tBL(ON) t FR tFF(ON) NO FAULT SCB FAULT DIAG NOT COMPLETE SCB FAULT 100 001 111 001 1 CSB 0 ON/OFF Pulse Req Ignored During Retry 1 SO 001 0 ECHO 1 FLTB 0 Retry 1 Figure 24. Auto-retry Timer Started, INx Went Low During Second Retry − Retry Timer Runs to Completion 1 INx Don’t Care 0 1 DRNx GATx 0 VBAT VOL VOL FLTREF VSG 0 1 INTERNAL SIGNALS RSTB 0 BLANK/ 1 REFRESH TIMER 0 tFR FILTER 1 TIMER 0 DIAG 1 STATUS 0 tBL(ON ) tFR tFF(ON ) NO FAULT SCB FAULT DIAG NOT COMPLETE SCB FAULT NOT COMPLETE NO SCG/OLF 100 001 111 001 111 110 1 CSB 0 ON/OFF Pulse Req Ignored During Retry 1 SO 0 001 001 ECHO 1 FLTB 0 Retry 2 Figure 25. Auto-retry Timer Started, INx Went Low During Second Retry − Retry Timer Runs to Completion Status Read Clears SCB, Allows OFF-state Status Update www.onsemi.com 32 NCV7518, NCV7518A 1 INx Don’t Care 0 1 DRNx GATx 0 VBAT VOL VOL VSG FLTREF VSG 0 1 INTERNAL SIGNALS RSTB 0 OFF BLANK STARTED TO ALLOW DRAIN TO SETTLE BLANK 1 TIMER 0 tBL(ON) tBL(OFF ) FILTER 1 TIMER 0 DIAG 1 STATUS 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 1 CSB NO FAULT 110 100 ON or OFF Pulse Req Ignored During tBL(ON|OFF) 0 ON Pulse Req 1 SO ECHO ECHO 0 1 FLTB 0 Pulse 1 Figure 26. Normal ON Pulse Request & Second Request Ignored − INx Remains in Low State at End of Pulse 1 INx BLANKING NOT RE−STARTED 0 1 DRNx GATx 0 VBAT VOL VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 ON BLANK STARTED TO ALLOW DRAIN TO SETTLE BLANK 1 TIMER 0 tBL(ON ) t BL(ON) t BL(OFF ) tBL(ON ) FILTER 1 TIMER 0 DIAG 1 STATUS 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 NO FAULT 110 100 NO SCB FAULT 111 101 1 CSB 0 ON Pulse Req 1 SO ECHO ECHO ON or OFF Pulse Req ON Pulse Req IGNORED ECHO OFF Pulse Req Status Req ECHO 100 0 1 FLTB 0 Pulse 2 Figure 27. Normal ON Pulse Request & Second Request Ignored − INx State Change During First Pulse Execution, Normal OFF Pulse Request www.onsemi.com 33 NCV7518, NCV7518A 1 INx BLANKING NOT RE−STARTED 0 1 GATx 0 DRNx VBAT VOL VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 OFF BLANK STARTED TO ALLOW DRAIN TO SETTLE BLANK 1 TIMER 0 tBL(ON) t BL(ON) tBL(OFF) t BL(ON) FILTER 1 TIMER 0 DIAG 1 STATUS 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 NO FAULT 110 NO SCB FAULT 100 111 101 1 CSB 0 ON Pulse Req 1 SO ECHO ECHO ON or OFF Pulse Req ON Pulse Req IGNORED ECHO ON or OFF Pulse Req IGNORED ECHO Status Req 100 0 1 FLTB 0 Pulse 2a Figure 28. Normal ON Pulse Request & Second Request Ignored, Normal ON Pulse Request, INx State Change During Normal Pulse Executions 1 INx Don’t Care 0 1 DRNx GATx 0 VBAT VOL VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 OFF BLANK NOT STARTED (ON STATE) BLANK 1 TIMER 0 tBL(ON ) t BL(ON) ON BLANK NOT STARTED (OFF STATE) t BL(OFF ) FILTER 1 TIMER 0 DIAG 1 STATUS 0 DIAG NOT COMPLETE NO SCB FAULT 111 101 NO FAULT 110 100 NO SCG/OLF FAULT 111 110 1 CSB 0 ON Pulse Req 1 SO ECHO ECHO ON or OFF Pulse Req IGNORED ON Pulse Req OFF Pulse Req Status Req ECHO ECHO 100 0 1 FLTB 0 Pulse 3 Figure 29. Normal ON Pulse Request & Second Request Ignored, Normal OFF Pulse Request, INx State Change During Normal Pulse Executions and Goes Low During OFF Pulse www.onsemi.com 34 NCV7518, NCV7518A 1 INx 0 1 GATx 0 DRNx VBAT t < tFF(ON) VOL VSG FLTREF VSG FLTREF VSG 0 1 INTERNAL SIGNALS RSTB 0 BLANK 1 TIMER 0 FILTER 1 TIMER 0 DIAG 1 STATUS 0 tBL(ON) tBL(OFF ) t FF(ON) tBL(OFF ) tFF(ON ) PREVIOUS DATA SCB DIAG NOT COMPLETE 111 NO SCG/OLF FAULT 1 CSB 0 1 SO SCB 111 0 1 FLTB 0 ON BLANK & FILTER & SCB Figure 30. Filter Timer Started During Blank Timer Because of Intermittent SCB, Re-started Just Before End of Blank Timer − SCB Latch-off Time Extended 1 INx 0 1 GATx 0 DRNx VBAT OLF OLF SCG VOL FLTREF VSG FLTREF 0 1 INTERNAL SIGNALS RSTB 0 BLANK 1 TIMER 0 FILTER 1 TIMER 0 DIAG 1 STATUS 0 t BL(OFF ) t FF(OFF ) tBL(ON ) tFF(OFF ) tFF(OFF ) PREVIOUS DATA 111 OLF NO SCB FAULT 1 CSB 0 1 SO OLF 0 1 FLTB 0 OFF BLANK & FILTER & FLT Figure 31. Filter Timer Started When Falling Through OLF Threshold During Blank Timer, Re-started When Falling Through SCG Threshold, Re-started When Falling Through OLF Threshold − OFF-State Diagnostic Status Acquisition Time Extended by Filter Timer www.onsemi.com 35 NCV7518, NCV7518A 1 INx 0 DRNx VBAT 0 VLOAD VBAT VLD UV 0 INTERNAL SIGNALS 1 VLDUV 0 BLANK 1 TIMER 0 tBL(ON) t BL(OFF) FILTER 1 TIMER 0 DIAG 1 STATUS 0 VALID ON STATE DATA PREVIOUS DATA 111 VALID ON STATE DATA DIAGNOSTIC NOT COMPLETE 1 CSB 0 Read Status Read Status 1 SO STATUS STATUS 0 1 FLTB 0 VLDUV 1 Figure 32. OFF-State Diagnostic Status is Suppressed While in VLOAD Undervoltage − ON-State Diagnostics Remain Functional 1 INx 0 DRNx VBAT 0 VLOAD VBAT VLD UV 0 INTERNAL SIGNALS 1 VLDUV 0 BLANK 1 TIMER 0 tBL(OFF) tBL(OFF) FILTER 1 TIMER 0 DIAG 1 STATUS 0 PREVIOUS DATA DIAGNOSTIC NOT COMPLETE VALID OFF STATE DIAGNOSTIC 1 CSB 0 Read Status 1 SO STATUS 0 1 FLTB 0 VLDUV 2 Figure 33. OFF-State Diagnostic Starts When Recovery From Undervoltage Occurs FLEXMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC). www.onsemi.com 36 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P (PUNCHED) CASE 485CZ ISSUE A DATE 29 JUL 2013 SCALE 2:1 PIN ONE REFERENCE ÉÉÉ ÉÉÉ ÉÉÉ L A B D L DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L 0.15 C 0.15 C 0.10 C TOP VIEW (A3) DETAIL B A DETAIL B ALTERNATE CONSTRUCTION 0.08 C SIDE VIEW NOTE 4 A1 C 0.10 SEATING PLANE GENERIC MARKING DIAGRAM* C A B M 1 D2 DETAIL A 32X 9 L XXXXXXXX XXXXXXXX AWLYYWWG G 8 E2 1 24 32 32X e e/2 BOTTOM VIEW 0.10 b M 0.10 M C A B 0.05 M C XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) C A B NOTE 3 RECOMMENDED SOLDERING FOOTPRINT 5.30 32X 3.60 0.50 PITCH DOCUMENT NUMBER: DESCRIPTION: *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.62 3.60 PKG OUTLINE (0.15) (0.10) MILLIMETERS MIN MAX 0.80 0.90 −−− 0.05 0.20 REF 0.20 0.30 5.00 BSC 3.20 3.40 5.00 BSC 3.20 3.40 0.50 BSC 0.30 0.50 5.30 32X 0.30 DIMENSIONS: MILLIMETERS 98AON87072E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. QFN32 5x5, 0.5P (PUNCHED) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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