NCV8461DR2G

NCV8461 Self Protected High Side Driver with Temperature Shutdown and Current Limit The NCV8461 is a fully protected High−Side driver that can be used to switch a wide variety of loads, such as bulbs, solenoids and other activators. The device is internally protected from an overload condition by an active current limit and thermal shutdown. A diagnostic output reports OFF state open load conditions as well as thermal shutdown. www.onsemi.com 8 1 SOIC−8 CASE 751 STYLE 11 Features • • • • • • • • • • • • • Short Circuit Protection Thermal Shutdown with Automatic Restart CMOS (3 V / 5 V) Compatible Control Input Off State Open Load Detection Open Drain Diagnostic Output Overvoltage Protection Undervoltage Shutdown Loss of Ground and Loss of VD Protection ESD Protection Reverse Battery Protection (with external resistor) Very Low Standby Current NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This is a Pb−Free Device MARKING DIAGRAM 8 NCV8461 AYWWG G 1 NCV8461 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS Typical Applications • Switch a Variety of Resistive, Inductive and Capacitive Loads • Can Replace Electromechanical Relays and Discrete Circuits • Automotive / Industrial GND 1 VD IN VD OUT VD STAT VD (Top View) FEATURE SUMMARY Overvoltage Protection VOV 41 V RDSon (max) TJ = 25°C RON 350 mW Output Current Limit (typ) Ilim 1.2 A Operating Voltage Range VOP 5 − 34 V ORDERING INFORMATION Device Package Shipping† NCV8461DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017 January, 2017 − Rev. 4 1 Publication Order Number: NCV8461/D NCV8461 VD Undervoltage Detection Short to Vd Detection Regulated Chargepump Output Clamping Input Buffer IN Pre Driver Control Logic Current Limitation STAT Overtemperature Detection ON−State Short Circuit Detection GND Off−State Open Load Detection Figure 1. Block Diagram SO8 PACKAGE PIN DESCRIPTION Pin # Symbol 1 GND 2 IN Description Ground Logic Level Input 3 OUT Output 4 STAT Status Output 5 VD Supply Voltage 6 VD Supply Voltage 7 VD Supply Voltage 8 VD Supply Voltage www.onsemi.com 2 í OUT NCV8461 Table 1. MAXIMUM RATINGS Value Rating DC Supply Voltage (Note 1) Peak Transient Input Voltage (Note 1) (Load Dump 38 V, VD = 14 V, ISO7637−2 pulse5) Symbol Min Max Unit VD −16 40 V 52 V Vpeak Input Voltage Vin −10 16 V Input Current Iin −5 5 mA Iout − Internally Limited A Istatus −5 5 mA Output Current (Note 1) Status Current Power Dissipation Tc = 25°C (Note 1) Ptot Electrostatic Discharge (Note 1) (HBM Model 100 pF / 1500 W) Input All Other Pins 1.5 W DC ±1.5 ±5 Single Pulse Inductive Load Switching Energy (Note 1) VD = 13.5 V; IL = 0.5 A, TJstart = 150°C EAS − 300 mJ TJ −40 +150 °C Tstorage −55 +150 °C Operating Junction Temperature Storage Temperature kV kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Not subjected to production testing Table 2. THERMAL RESISTANCE RATINGS Parameter Symbol Max. Value RthJS RthJA 31 84 Units °C/W Thermal Resistance (Note 2) Junction−to−Soldering Point Junction−to−Ambient (6 cm square pad size, FR−4, 2 oz Cu) 2. Reverse Output current has to be limited by the load to stay within absolute maximum ratings and thermal performance. See spec table and page 6 for further reverse battery information. www.onsemi.com 3 NCV8461 Table 3. ELECTRICAL CHARACTERISTICS (VD = 13.5 V; −40°C < TJ < 150°C unless otherwise specified) Value Symbol Rating Operating Supply Voltage VD Undervoltage Shutdown VUV Undervoltage Restart Conditions Min Typ Max Unit 5 − 34 V 5 V 5.5 V VUV_Res Overvoltage Protection VOV ID = 4 mA On Resistance RON Iout = 0.3 A; 6 V < VD < 40 V, TJ = 25°C Iout = 0.3 A; 6 V < VD < 40 V, TJ = 150°C 250 450 350 700 mW ID Off State, Vin = Vout = 0 V On State; Vin = 5 V, Iout = 0 A 13 1 35 1.7 mA mA IL(off) 12 mA Input Voltage − Low Vin_low 0.8 V Input Voltage − High Vin_high Standby Current Output Leakage Current 41 V INPUT CHARACTERISTICS Input Hysteresis Voltage 2.2 Vhyst V 0.3 V Off State Input Current Iin_OFF Vin = 0.7 V 1 10 mA On State Input Current Iin_ON Vin = 5.0 V 1 10 mA Input Resistance (Note 3) RI Input Clamp Voltage Vin_cl Iin = 1 mA Iin = −1 mA Turn−On Delay Time td_on Turn−Off Delay Time 1.5 3.5 14 −18 16 −16 KW 18 −14 V to 90% Vout, RL = 47 W 140 ms td_off to 10% Vout, RL = 47 W 170 ms Slew Rate On dVout/dton 10% to 30% Vout, RL = 47 W 2 V / ms Slew Rate Off dVout/dtoff 70% to 40% Vout, RL = 47 W 2 V / ms Reverse Battery −VD Requires a 150 W Resistor in GND Connection 32 V Forward Voltage VF TJ = 150°C, IS = 200 mA Vstat_low Istat = 1.6 mA, TJ = −40°C to 25°C Istat = 1.6 mA, TJ = 150°C (Note 3) 0.4 0.6 V Istat_leakage Vstat = 5 V 10 mA 700 ms SWITCHING CHARACTERISTICS REVERSE BATTERY (Note 3) 0.6 V STATUS PIN CHARACTERISTICS Status Output Voltage Low Status Leakage Current Status Invalid Time After Positive Input Slope Td(STAT) Status Clamp Voltage Vstat_cl 300 Istat = 1 mA Istat = −1 mA 10 −1.4 V PROTECTION FUNCTIONS (Note 4) Temperature Shutdown (Note 3) TSD Temperature Shutdown Hysteresis (Note 3) TSD_hyst 150 175 10 200 °C °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Not subjected to production testing 4. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper hardware/software strategy. If the devices operates under abnormal conditions this hardware/software solutions must limit the duration and number of activation cycles. AEC Q100−12 results available upon request. www.onsemi.com 4 NCV8461 Table 3. ELECTRICAL CHARACTERISTICS (VD = 13.5 V; −40°C < TJ < 150°C unless otherwise specified) Value Rating Min Symbol Conditions Ilim TJ = −40°C, VD = 20 V (Note 3) TJ = 25°C TJ = 150°C (Note 3) Typ Max Unit 2 A PROTECTION FUNCTIONS (Note 4) Output Current Limit Initial Peak 1.2 0.7 Repetitive Short Circuit Current Limit Ilim(SC) TJ = TJt (Note 3) Switch Off Output Clamp Voltage Vclamp ID = 4 mA, Vin = 0 V VD − 41 Vin = 0 V 1.5 1 A VD − 47 V DIAGNOSTICS CHARACTERISTICS Short Circuit Detection Voltage VOUT(SC) Openload Off State Detection Threshold VOL Openload Detection Current IL(OL) 2.8 V 3.5 V mA 5 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Not subjected to production testing 4. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper hardware/software strategy. If the devices operates under abnormal conditions this hardware/software solutions must limit the duration and number of activation cycles. AEC Q100−12 results available upon request. Table 4. STATUS PIN TRUTH TABLE Conditions Input Output Status Normal Operation L H L H H H Short Circuit to GND L H L L* H L Short to VD (OFF State) L H H H L H Current Limitation L H L H** H H Overtemperature L H L L H L OFF State Open Load L H H H L H * Output = “L”; VOUT < 2 V typ. ** Output = “H”; VOUT > 2 V typ. www.onsemi.com 5 NCV8461 REVERSE BATTERY PROTECTION The NCV8461 provides reverse battery protection up to 32 V. This protection requires a Resistor in the GND path. The recommended GND resistor is 150 W, but a variety of resistor values can be chosen for this purpose. The graph below shows the considerations and constraints for selection of the GND resistor. Figure 2 shows the power dissipation in the GND resistor during a 32 V reverse battery event on the left axis, while the right axis shows the voltage drop across the GND resistor while in normal operation. The far right side of the graph is grayed out to indicate that the voltage drop across the resistor is too high, and the part will not be able to turn on with a standard 5 V on the input pin. Selection of the optimal GND resistor requires balancing the power dissipation considerations while in a reverse battery event, with the turn on capability of the input signal during normal operation. Figure 2. Reverse Battery Considerations Figure 3. Reverse Battery Protection Circuit www.onsemi.com 6 NCV8461 TYPICAL PERFORMANCE CHARACTERISTICS 1000 ENERGY (mJ) CURRENT (A) 10 TJStart = 25°C 1 TJStart = 150°C 100 TJStart = 25°C TJStart = 150°C 0.1 10 100 1000 1000 INDUCTANCE (mH) Figure 4. Maximum Single Pulse Switch Off Current vs. Inductance Figure 5. Maximum Single Pulse Switch Off Energy vs. Inductance 600 600 550 550 500 500 150°C 450 RDS(on) (mW) 125°C 400 350 300 25°C 250 400 350 300 250 VDS = 13.5 V 200 200 −40°C 150 100 0 10 20 30 150 100 −40 −20 40 0 20 40 60 80 100 120 Vbat (V) TEMPERATURE (°C) Figure 6. RDS(on) Over Temp and Battery Figure 7. RDS(on) vs. Temperature 0.80 0.75 0.75 0.70 0.70 SLEW RATE (V/ms) SLEW RATE (V/ms) 100 INDUCTANCE (mH) 450 RDS(on) (mW) 10 0.65 0.60 0.55 VDS = 13.5 V Rload = 47 W 0.50 0.65 0.60 0.55 0.50 VDS = 13.5 V Rload = 47 W 0.45 0.45 0.40 −40 −20 0 20 40 60 80 100 120 0.40 −40 −20 140 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Slew Rate On vs. Temperature Figure 9. Slew Rate Off vs. Temperature www.onsemi.com 7 140 140 NCV8461 1.0 2.0 0.9 1.8 0.8 1.6 0.7 1.4 CURRENT (A) GROUND CURRENT (mA) TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.5 0.4 1.2 1.0 0.8 0.6 0.3 0.2 VDS = 13.5 V 0.1 0 −40 −20 0 20 40 60 80 100 120 VDS = 13.5 V 0.4 0.2 0 −40 −20 140 40 60 100 80 120 TEMPERATURE (°C) Figure 10. On State Ground Current vs. Temp Figure 11. Current Limit vs. Temperature 140 50 45 1.0 −40°C VD = 9 V TURN ON TIME (ms) 40 25°C 0.8 VSD (V) 20 TEMPERATURE (°C) 1.2 125°C 0.6 150°C 0.4 35 VD = 36 V 30 VD = 13.5 V 25 20 15 10 0.2 Rload = 47 W 5 0 0 0 100 200 300 400 500 −50 600 0 50 100 150 IS (mA) TEMPERATURE (°C) Figure 12. Body Diode Figure 13. Turn On Time vs. Temperature 100 170 90 160 VD = 9 V 80 qJA curve with PCB cu thk 1.0 oz. 150 70 VD = 13.5 V 60 140 qJA (°C/W) TURN OFF TIME (ms) 0 VD = 36 V 50 40 T_ambient 130 120 110 30 100 20 Rload = 47 W 10 0 90 qJA curve with PCB cu thk 2.0 oz. 80 −50 0 50 100 0 150 100 200 300 400 500 600 TEMPERATURE (°C) COPPER HEAT SPREADER AREA (mm2) Figure 14. Turn Off Time vs. Temperature Figure 15. Junction−to−Ambient Thermal Resistance vs. Copper Area www.onsemi.com 8 700 NCV8461 TYPICAL PERFORMANCE CHARACTERISTICS 100 50% Duty Cycle R(t), (°C/W) 20% 10 10% 5% 2% 1 1% 0.1 Single Pulse 0.01 0.001 0.000001 PsiLA(t) 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) 1 10 100 1000 Figure 16. Junction to Ambient Transient Thermal Impedance (600 mm2 Copper Area) ISO 7637-2:2011 (E) PULSE TEST RESULTS ISO 7637−2:2011(E) Test Pulse Test Severity Levels, 13.5 V System III IV Delays and Impedance # of Pulses or Test Time Pulse / Burst Rep. Time 1 −112 −150 2 ms, 10 W 500 pulses 0.5 s 2a +55 +112 0.05 ms, 2 W 500 pulses 0.5 s 3a −165 −220 0.1 ms, 50 W 1h 100 ms 3b +112 +150 0.1 ms, 50 W 1h 100 ms Test Results ISO 7637−2:2011(E) Test Pulse III IV 1 C C 2a C E 3a C C 3b C C Class Functional Status C One or more functions of a device do not perform as designed during exposure but return automatically to normal operation after exposure is removed. E One or more functions of a device do not perform as designed during and after exposure and cannot be returned to proper operation without replacing the device. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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