NCV8501D25G

NCV8501 Series LDO Linear Regulators Micropower, ENABLE, DELAY, RESET, Monitor FLAG http://onsemi.com 150 mA The NCV8501 is a family of precision micropower voltage regulators. Their output current capability is 150 mA. The family has output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V. The output voltage is accurate within ±2.0% with a maximum dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 90 mA with a 100 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY), and a FLAG monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the FLAG monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions. Features • • • • • • • • • • • Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V ±2.0% Output Low 90 mA Quiescent Current Fixed or Adjustable Output Voltage Active RESET ENABLE 150 mA Output Current Capability Fault Protection ♦ +60 V Peak Transient Voltage ♦ −15 V Reverse Voltage ♦ Short Circuit ♦ Thermal Overload Early Warning through FLAG/MON Leads NCV Prefix for Automotive and Other Applications Requiring Site and Change Control These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2009 September, 2019 − Rev. 29 1 SO−8 D SUFFIX CASE 751 8 1 16 1 SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751AG MARKING DIAGRAMS SOW−16 E PAD SO−8 16 8 1 8501x ALYW G 8501x AWLYYWWG 1 x = Voltage Ratings as Indicated Below: A = Adjustable 2 = 2.5 V 3 = 3.3 V 5 = 5.0 V 8 = 8.0 V 0 = 10 V A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: NCV8501/D NCV8501 Series PIN CONNECTIONS, ADJUSTABLE OUTPUT 1 VIN SO−8 8 MON ENABLE VOUT VADJ VOUT NC NC NC NC VIN MON VADJ FLAG NC GND SOW−16 E PAD 1 16 FLAG NC NC GND NC NC NC ENABLE PIN CONNECTIONS, FIXED OUTPUT 1 VIN SO−8 MON ENABLE VOUT FLAG VOUT NC NC NC NC VIN MON FLAG RESET DELAY GND VIN SOW−16 E PAD 1 16 RESET NC NC GND NC NC DELAY ENABLE VOUT VDD 10 mF 10 mF NCV8501 DELAY RFLG 10 k Microprocessor VBAT 8 RRST 10 k MON CDELAY ENABLE FLAG VADJ (Adjustable Output Only) RESET I/O GND Figure 1. Application Diagram http://onsemi.com 2 I/O NCV8501 Series MAXIMUM RATINGS* Rating Value Unit −15 to 45 V Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) 60 V Operating Voltage 45 V VOUT (dc) −0.3 to 16 V Voltage Range (RESET, FLAG) −0.3 to 10 V Input Voltage Range (MON) Input Voltage Range (VAOJ) −0.3 to 10 −0.3 to 16 V −0.3 to 10** V 2.0 kV Junction Temperature, TJ −40 to +150 °C Storage Temperature, TS −55 to 150 °C 45 165 °C/W °C/W 15 56 35 °C/W °C/W °C/W 260 Peak (Note 3) °C VIN (dc) Input Voltage Range (ENABLE) ESD Susceptibility (Human Body Model) Package Thermal Resistance, SO−8: Junction−to−Case, RqJC Junction−to−Ambient, RqJA Package Thermal Resistance, SOW−16 E PAD: Junction−to−Case, RqJC Junction−to−Ambient, RqJA Junction−to−Pin, RqJP (Note 1) Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely. **Reference Figure 15 for switched−battery ENABLE application. 1. Measured to pin 16. 2. 150 second maximum above 217°C. 3. −5°C / +0°C allowable conditions. http://onsemi.com 3 NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit Output Voltage for 2.5 V Option 6.5 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA 5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 2.450 2.425 2.5 2.5 2.550 2.575 V V Output Voltage for 3.3 V Option 7.3 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA 5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 3.234 3.201 3.3 3.3 3.366 3.399 V V Output Voltage for 5.0 V Option 9.0 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA 6.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 4.90 4.85 5.0 5.0 5.10 5.15 V V Output Voltage for 8.0 V Option 9.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 7.76 8.0 8.24 V Output Voltage for 10 V Option 11 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA 9.7 10 10.3 V Output Voltage for Adjustable Option VOUT = VADJ (Unity Gain) 6.5 V < VIN < 16 V, 100 mA < IOUT < 150 mA 5.5 V < VIN < 26 V, 100 mA < IOUT < 150 mA 1.254 1.242 1.280 1.280 1.306 1.318 V V − − 400 100 600 150 mV mV −30 5.0 30 mV − 15 60 mV − − − − − − 90 90 90 100 100 50 125 125 125 150 150 75 mA mA mA mA mA mA Output Stage Dropout Voltage (VIN − VOUT) (5.0 V, 8.0 V, 10 V, and Adj. > 5.0 V Options Only) IOUT = 150 mA IOUT = 1.0 mA Load Regulation VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA Line Regulation [VOUT(Typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA Quiescent Current, Low Load 2.5 V Option 3.3 V Option 5.0 V Option 8.0 V Option 10 V Option Adjustable Option IOUT = 100 mA, VIN = 12 V, MON = VOUT Quiescent Current, Medium Load All Options IOUT = 75 mA, VIN = 14 V, MON = VOUT − 4.0 6.0 mA Quiescent Current, High Load All Options IOUT = 150 mA, VIN = 14 V, MON = VOUT − 12 19 mA Quiescent Current, (IQ) Sleep Mode ENABLE = 0 V, VIN = 12 V − 12 30 mA Current Limit 151 300 − mA Short Circuit Output Current VOUT = 0 V − 40 190 − mA Thermal Shutdown (Guaranteed by Design) 150 180 − °C RESET Threshold for 2.5 V Option HIGH (VRH) LOW (VRL) 5.5 V ≤ VIN ≤ 26 V (Note 5) VOUT Increasing VOUT Decreasing 2.28 2.25 2.350 2.300 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 3.3 V Option HIGH (VRH) LOW (VRL) 5.5 V ≤ VIN ≤ 26 V (Note 5) VOUT Increasing VOUT Decreasing 3.00 2.97 3.102 3.036 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 5.0 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 4.55 4.50 4.70 4.60 0.98 × VOUT 0.97 × VOUT V V RESET Threshold for 8.0 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing 7.05 7.00 7.52 7.36 0.98 × VOUT 0.97 × VOUT V V Reset Function (RESET) 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 4 NCV8501 Series ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = 5.0 V, −40°C ≤ TJ ≤ 150°C; VIN dependent on voltage option (Note 4); unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit 8.60 8.50 9.40 9.20 0.98 × VOUT 0.97 × VOUT V V − 0.1 0.4 V 1.4 1.8 2.2 V − − 0.1 V Reset Function (RESET) RESET Threshold for 10 V Option HIGH (VRH) LOW (VRL) VOUT Increasing VOUT Decreasing Output Voltage Low (VRLO) 1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k DELAY Switching Threshold (VDT) − DELAY Low Voltage VOUT < RESET Threshold Low(min) DELAY Charge Current DELAY = 1.0 V, VOUT > VRH 1.5 2.5 3.5 mA DELAY Discharge Current DELAY = 1.0 V, VOUT = 1.5 V 5.0 − − mA Increasing and Decreasing 1.10 1.20 1.31 V 20 50 100 mV −0.5 0.1 0.5 mA − 0.1 0.4 V VADJ = 1.28 V −0.5 − 0.5 mA Input Threshold Low High − 3.0 − − 0.5 − V V Input Current ENABLE = 5.0 V − 1.0 5.0 mA FLAG/Monitor Monitor Threshold Hysteresis − Input Current MON = 2.0 V Output Saturation Voltage MON = 0 V, IFLAG = 1.0 mA Voltage Adjust (Adjustable Output only) Input Current ENABLE 4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type. 5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation. http://onsemi.com 5 NCV8501 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Package Pin Number SO−8 SOW−16 E PAD Pin Symbol 1 7 VIN 2 8 MON 3 9 ENABLE 4 3−6, 10−12, 14, 15 NC 5 13 GND Ground. All GND leads must be connected to Ground. 6 16 FLAG Open collector output from early warning comparator. 7 1 VADJ Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage. 8 2 VOUT ±2.0%, 150 mA output. Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. No connection. PACKAGE PIN DESCRIPTION, FIXED OUTPUT Package Pin Number SO−8 SOW−16 E PAD Pin Symbol 1 7 VIN 2 8 MON 3 9 ENABLE 4 10 DELAY 5 13 GND 6 16 RESET 7 1 FLAG Open collector output from early warning comparator. 8 2 VOUT ±2.0%, 150 mA output. − 3−6, 11, 12, 14, 15 NC Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT ≥ 1.0 V) No connection. http://onsemi.com 6 NCV8501 Series TYPICAL PERFORMANCE CHARACTERISTICS 3.35 5.01 VOUT = 5.0 V VIN = 14 V IOUT = 5.0 mA VOUT = 3.3 V VIN = 14 V IOUT = 5.0 mA 3.34 3.33 VOUT (V) VOUT (V) 5.00 4.99 3.32 3.31 3.30 3.29 3.28 4.98 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3.27 −40 −25 −10 Figure 2. Output Voltage vs. Temperature 1.2 95 110 125 VIN = 12 V +125°C 10 +25°C 0.6 IQ (mA) IQ (mA) 14 −40°C 0.4 +125°C 8 +25°C 6 −40°C 4 0.2 2 0 5 10 15 IOUT (mA) 20 0 25 0 Figure 4. Quiescent Current vs. Output Current 15 30 45 60 75 90 IOUT (mA) 105 120 135 140 Figure 5. Quiescent Current vs. Output Current 120 7 T = 25°C 6 T = 25°C 100 IOUT = 100 mA 5 3 1 20 IOUT = 10 mA 6 8 10 12 14 16 18 VIN (V) 60 49 IOUT = 50 mA 2 IOUT = 100 mA 80 4 IQ (mA) IQ (mA) 80 12 0.8 0 20 35 50 65 Temperature (°C) Figure 3. Output Voltage vs. Temperature VIN = 12 V 1.0 0 5 20 22 24 0 26 6 Figure 6. Quiescent Current vs. Input Voltage 8 10 12 14 16 18 VIN (V) 20 22 24 Figure 7. Quiescent Current vs. Input Voltage http://onsemi.com 7 26 NCV8501 Series 450 16 400 14 350 300 +125°C 250 +25°C Quiescent Current (mA) Dropout Voltage (mV) TYPICAL PERFORMANCE CHARACTERISTICS −40°C 200 150 100 0 12 10 8 6 4 VOUT = 5.0 V, 8.0 V, or 10 V 50 0 25 50 75 IOUT (mA) 100 125 VIN = 12 V 2 0 −40 −25 −10 150 Figure 8. Dropout Voltage vs. Output Current 5 20 35 50 65 Temperature (°C) 95 110 125 Figure 9. Sleep Mode IQ vs. Temperature 1000 1000 Unstable Region Unstable Region CVout = 10 mF 100 100 CVout = 0.1 mF 10 V 8V 10 2.5 V 3.3 V 10 ESR (W) ESR (W) 80 5V 1.0 1.0 Stable Region Stable Region 0.1 0.1 CVOUT = 10 mF 0.01 10 20 30 40 50 60 70 80 90 0.01 100 0 10 OUTPUT CURRENT (mA) Figure 10. Output Stability with Output Voltage Change 20 30 40 50 60 70 80 OUTPUT CURRENT (mA) 70 Iout = 10 mA 60 Iout = 80 mA 50 40 Iout = 150 mA 30 20 0.1 90 100 110 Figure 11. Output Stability with Output Capacitor Change (dB) 0 1.0 10 (kHz) Figure 12. Audio Frequency Power Supply Rejection Ratio http://onsemi.com 8 100 NCV8501 Series VOUT VIN Current Source (Circuit Bias) ENABLE IBIAS Current Limit Sense + + − IBIAS + − VBG RESET + − VBG 1.8 V Fixed Voltage only Thermal Protection 3.0 mA Delay Error Amplifier IBIAS Bandgap Reference VBG VBG − Figure 13. Block Diagram http://onsemi.com 9 VADJ GND IBIAS + MON 20 k Adjustable Version only FLAG NCV8501 Series CIRCUIT DESCRIPTION REGULATOR CONTROL FUNCTIONS The NCV8501 contains the microprocessor compatible control function RESET (Figure 14). The DELAY lead provides source current (typically 2.5 mA) to the external DELAY capacitor during the following proceedings: 1. During Power Up (once the regulation threshold has been verified). 2. After a reset event has occurred and the device is back in regulation. The DELAY capacitor is discharged when the regulation (RESET threshold) has been violated. This is a latched incident. The capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. VIN RESET Threshold VOUT DELAY Threshold (VDT) DELAY RESET FLAG/Monitor Function Td Td An on−chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the FLAG pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap reference. The actual trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 16). The typical threshold is 1.20 V on the MON pin. Figure 14. Reset and Delay Circuit Wave Forms RESET Function A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 6.0% of the regulated output voltage, or when VOUT drops out of regulation,and is lower than 8.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V. VBAT MON I/O FLAG RESET RESET DELAY GND Figure 16. FLAG/Monitor Function Voltage Adjust Figure 17 shows the device setup for a user configurable output voltage. The feedback to the VADJ pin is taken from a voltage divider referenced to the output voltage. The loop is balanced around the Unity Gain threshold (1.28 V typical). NCV8501 10 k mP COUT RADJ VOUT VIN VCC NCV8501 The part stays in a low IQ sleep mode when the ENABLE pin is held low. The part has an internal pull down if the pin is left floating. This is intended for failure modes only. An external connection (active pulldown, resistor, or switch) for normal operation is recommended. The integrity of the ENABLE pin allows it to be tied directly to the battery line through an external resistor. It will withstand load dump potentials in this configuration. VBAT VOUT VIN ENABLE Function ENABLE GND ≈5.0 V VOUT NCV8501 Figure 15. ENABLE Function VADJ DELAY Function 15 k COUT 1.28 V 5.1 k The reset delay circuit provides a programmable (by external capacitor) delay on the RESET output lead. Figure 17. Adjustable Output Voltage http://onsemi.com 10 NCV8501 Series APPLICATION NOTES VIN CIN* 0.1 mF NCV8501 MJD31C VOUT VIN VBAT C2 0.1 mF R1 294 k NCV8501 RRST COUT** 10 mF RESET 5.0 V >1 Amp VADJ VOUT C1 47 mF *CIN required if regulator is located far from the power supply filter **COUT required for stability. Capacitor must operate at minimum temperature expected R2 100 k Figure 20. Test and Application Circuit Showing Output Compensation Figure 18. Additional Output Current SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation: Adding Capability Figure 18 shows how the adjustable version of parts can be used with an external pass transistor for additional current capability. The setup as shown will provide greater than 1 Amp of output current. tDELAY + FLAG MONITOR Figure 19 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 16. As the output voltage falls (VOUT), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET shutdown signal. ƪCDELAY(Vdt * Reset Delay Low Voltage)ƫ Delay Charge Current Example: Using CDELAY = 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for Vdt = 1.8 V. Use the typical value for Delay Charge Current = 2.5 mA. tDELAY + ƪ33 nF(1.8 * 0)ƫ 2.5 mA + 23.8 ms STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The value for the output capacitor COUT shown in Figure 20 should work for most applications, however it is not necessarily the optimized solution. VOUT MON FLAG Monitor Ref. Voltage RESET FLAG TWARNING Figure 19. FLAG Monitor Circuit Waveform http://onsemi.com 11 NCV8501 Series UNDERSTANDING THE NCV8501 ENABLE PIN INPUT CURRENT CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 22) is: VCC D1 R2 1.2M ~3.85V D2 ENABLE R1 Z1 GND 11V Z2 N1 Z3 (eq. 1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated: D4 Internal power rail D5 D6 7V 5μA (max) ) VIN(max)IQ D3 P1 20K PD(max) + [VIN(max) * VOUT(min)] IOUT(max) Internal reference 1.25V T RQJA + 150° C * A PD Figure 21. NCV8501 Enable Function Equivalent Circuit (eq. 2) The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA’s less than the calculated value in Equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Z1, R1, and Z2 provide ESD and overvoltage protection. Note that, for ENABLE pin voltages in excess of 10 V, an external series resistor is required to limit the current into Z1. For ENABLE pin voltages less than +7 V, the 5 mA (maximum value) current source dominates the input current, as the opposing P1 base current is negligible by comparison. For ENABLE pin voltages between +7 V and +11 V, the input current is given by: 5 mA + ((VENABLE − 7) / 20 kW) For ENABLE pin voltages in excess of 10 V (Z1 breakover voltage can be as low as 10 V), the input current is dominated by the external series resistor. For the case where VENABLE = 12 V; REXT = 10 kW, the input current can be up to (2 V/10 kW), = 200 mA. The ENABLE threshold is that voltage required to achieve ~3.85 V at the base of N1, or approximately (3.85 V − 2 Vbe). At +20°C, this threshold is ~2.55 V. At −40°C, it can be as high as 3 V. If the value of REXT is increased to ~200 kW, to reduce ENABLE input current, then the worst−case drop across REXT must be added to 3 V to determine the effective maximum ENABLE threshold. At VENABLE < 7 V, we only need to consider the 5 mA current sink. Max effective threshold = 3 V + (5 mA * 220 kW) = 3 V + 1.1 V = 4.1 V IOUT IIN SMART REGULATOR® VIN VOUT } Control Features IQ Figure 22. Single Output Regulator with Key Performance Parameters Labeled Thermal Resistance, Junction to Ambient, RqJA, (°C/W) 100 90 80 70 60 50 40 0 200 400 600 Copper Area (mm2) 800 Figure 23. 16 Lead SOW (Exposed Pad), qJA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625, G−10/R−4 http://onsemi.com 12 NCV8501 Series HEATSINKS A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA: RqJA + RqJC ) RqCS ) RqSA where: RqJC = the junction−to−case thermal resistance, RqCS = the case−to−heatsink thermal resistance, and RqSA = the heatsink−to−ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. (eq. 3) http://onsemi.com 13 NCV8501 Series ORDERING INFORMATION Device NCV8501DADJG NCV8501DADJR2G NCV8501PDWADJG NCV8501PDWADJR2G NCV8501D25G NCV8501D25R2G NCV8501PDW25G NCV8501PDW25R2G NCV8501D33G NCV8501D33R2G NCV8501PDW33G NCV8501PDW33R2G NCV8501D50G NCV8501D50R2G NCV8501PDW50G NCV8501PDW50R2G NCV8501D80G NCV8501D80R2G NCV8501PDW80G NCV8501PDW80R2G NCV8501D100G NCV8501D100R2G NCV8501PDW100G NCV8501PDW100R2G Output Voltage Package Shipping† Adjustable SO−8 (Pb−Free) 98 Units/Rail Adjustable SO−8 (Pb−Free) 2500 Tape & Reel Adjustable SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail Adjustable SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel 2.5 V SO−8 (Pb−Free) 98 Units/Rail 2.5 V SO−8 (Pb−Free) 2500 Tape & Reel 2.5 V SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail 2.5 V SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel 3.3 V SO−8 (Pb−Free) 98 Units/Rail 3.3 V SO−8 (Pb−Free) 2500 Tape & Reel 3.3 V SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail 3.3 V SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel 5.0 V SO−8 (Pb−Free) 98 Units/Rail 5.0 V SO−8 (Pb−Free) 2500 Tape & Reel 5.0 V SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail 5.0 V SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel 8.0 V SO−8 (Pb−Free) 98 Units/Rail 8.0 V SO−8 (Pb−Free) 2500 Tape & Reel 8.0 V SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail 8.0 V SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel 10 V SO−8 (Pb−free) 98 Units/Rail 10 V SO−8 (Pb−Free) 2500 Tape & Reel 10 V SOW−16 Exposed Pad (Pb−Free) 47 Units/Rail 10 V SOW−16 Exposed Pad (Pb−Free) 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC. http://onsemi.com 14 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY, EXPOSED PAD CASE 751AG ISSUE B SCALE 1:1 −U− A 0.25 (0.010) M W 9 B 1 M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. M 16 P R x 45_ 8 −W− G 14 TOP VIEW PIN 1 I.D. PL DETAIL E C F −T− 0.10 (0.004) T K D 16 PL 0.25 (0.010) T U M SEATING PLANE W S S J SIDE VIEW DETAIL E 1 DIM A B C D F G H J K L M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.45 3.66 0.25 0.32 0.00 0.10 4.72 4.93 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.136 0.144 0.010 0.012 0.000 0.004 0.186 0.194 0_ 7_ 0.395 0.415 0.010 0.029 GENERIC MARKING DIAGRAM* H EXPOSED PAD DATE 31 MAY 2016 8 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX AWLYYWWG L 16 9 BOTTOM VIEW XXXXX A WL YY WW G SOLDERING FOOTPRINT* 0.350 Exposed Pad 0.175 0.050 CL 0.200 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.188 CL = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 0.376 0.074 0.150 0.024 DIMENSIONS: INCHES *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON21237D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. SOIC−16, WB EXPOSED PAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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