NCV8502 Series
LDO Linear Regulators Micropower, DELAY,
Adjustable RESET, and
Monitor FLAG
150 mA
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The NCV8502 is a family of precision micropower voltage
regulators. Their output current capability is 150 mA. The family has
output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V.
The output voltage is accurate within ±2.0% with a maximum
dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature
drawing only 90 mA with a 100 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET (with
DELAY), and a FLAG monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending RESET
signal. The use of the FLAG monitor allows the microprocessor to
finish any signal processing before the RESET shuts the
microprocessor down.
The active RESET circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of
external resistor divider to RADJ lead.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments. The
device has also been optimized for EMC conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V
±2.0% Output
Low 90 mA Quiescent Current
Fixed or Adjustable Output Voltage
Active RESET
Adjustable Reset
150 mA Output Current Capability
Fault Protection
♦ +60 V Peak Transient Voltage
♦ −15 V Reverse Voltage
♦ Short Circuit
♦ Thermal Overload
Early Warning through FLAG/MON Leads
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
AEC Qualified
PPAP Capable
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2008
September, 2019 − Rev. 31
1
8
1
16
1
SO−8
D SUFFIX
CASE 751
SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751AG
MARKING DIAGRAMS
SO−8
16
SOW−16
E PAD
8
1
8502x
ALYW
G
8502x
AWLYYWWG
1
x
= Voltage Ratings as Indicated Below:
A = Adjustable
2 = 2.5 V
3 = 3.3 V
5 = 5.0 V
8 = 8.0 V
0 = 10 V
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Publication Order Number:
NCV8502/D
NCV8502 Series
PIN CONNECTIONS, ADJUSTABLE OUTPUT
SO−8
VIN
1
8
VOUT
MON
NC
VADJ
VOUT
NC
NC
NC
NC
VIN
MON
VADJ
FLAG
NC
GND
SOW−16 E PAD
1
16
FLAG
NC
NC
GND
NC
NC
NC
NC
PIN CONNECTIONS, FIXED OUTPUT
SO−8
VIN
1
8
MON
RADJ
FLAG
VOUT
NC
NC
NC
NC
VIN
MON
FLAG
RESET
DELAY
GND
VIN
VOUT
VDD
10 mF
10 mF
RADJ
NCV8502
DELAY
RFLG
10 k
Microprocessor
VBAT
VOUT
SOW−16 E PAD
1
16
RESET
NC
NC
GND
NC
NC
DELAY
RADJ
RRST
10 k
MON
CDELAY
VADJ
(Adjustable
Output Only)
FLAG
RESET
I/O
GND
I/O
Figure 1. Application Diagram
MAXIMUM RATINGS*
Rating
Value
Unit
−15 to 48
V
Peak Transient Voltage (46 V Load Dump @ VIN = 14 V)
60
V
Operating Voltage
45
V
VOUT (dc)
−0.3 to 16
V
Voltage Range (RESET, FLAG)
−0.3 to 10
V
VIN (dc)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply.
Thermal dissipation must be observed closely.
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2
NCV8502 Series
MAXIMUM RATINGS* (continued)
Rating
Symbol
Value
Unit
Input Voltage Range (MON, VADJ, RADJ)
−0.3 to 10
V
ESD Susceptibility (Human Body Model)
2.0
kV
Junction Temperature
TJ
−40 to +150
°C
Storage Temperature
TS
−55 to 150
°C
RqJC
RqJA
45
165
°C/W
°C/W
RqJC
RqJA
RqJP
15
56
35
°C/W
°C/W
°C/W
SLD
265 peak
°C
Package Thermal Resistance, SO−8:
Junction−to−Case
Junction−to−Ambient
Package Thermal Resistance, SOW−16 E PAD:
Junction−to−Case
Junction−to−Ambient
Junction−to−Pin (Note 1)
Lead Temperature Soldering: SMD style only, Reflow (Note 2)
Pb−Free Part 60 − 150 sec above 217°C, 40 sec max at peak
1. Measured to pin 16.
2. Per IPC / JEDEC J−STD−020C.
*During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply.
Thermal dissipation must be observed closely.
ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, −40°C ≤ TJ ≤ 150°C; VIN = dependent on voltage option (Note 3); unless
otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage
Output Voltage for 2.5 V Option
6.5 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA
5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
2.450
2.425
2.5
2.5
2.550
2.575
V
V
Output Voltage for 3.3 V Option
7.3 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA
5.5 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
3.234
3.201
3.3
3.3
3.366
3.399
V
V
Output Voltage for 5.0 V Option
9.0 V < VIN < 16 V, 100 mA ≤ IOUT ≤ 150 mA
6.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
4.90
4.85
5.0
5.0
5.10
5.15
V
V
Output Voltage for 8.0 V Option
9.0 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
7.76
8.0
8.24
V
Output Voltage for 10 V Option
11 V < VIN < 26 V, 100 mA ≤ IOUT ≤ 150 mA
9.7
10
10.3
V
V
Output Voltage for Adjustable
Option
VOUT = VADJ (Unity Gain)
6.5 V < VIN < 16 V, 100 mA < IOUT < 150 mA
5.5 V < VIN < 26 V, 100 mA < IOUT < 150 mA
1.254
1.242
1.280
1.280
1.306
1.318
V
V
Dropout Voltage (VIN − VOUT)
(5.0 V, 8.0 V, 10 V and
Adj. > 5.0 V Options Only)
IOUT = 150 mA
IOUT = 1.0 mA
−
−
400
100
600
150
mV
mV
Load Regulation
VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA
−30
5.0
30
mV
Line Regulation
[VOUT(Typ) + 1.0] < VIN < 26 V, IOUT = 1.0 mA
−
15
60
mV
Quiescent Current, Low Load
2.5 V Option
3.3 V Option
5.0 V Option
8.0 V Option
10 V Option
Adjustable Option
IOUT = 100 mA, VIN = 12 V, MON = VOUT
−
−
−
−
−
−
90
90
90
100
100
50
125
125
125
150
150
75
mA
mA
mA
mA
mA
mA
Quiescent Current, Medium Load
All Options
IOUT = 75 mA, VIN = 14 V, MON = VOUT
−
4.0
6.0
mA
Quiescent Current, High Load
All Options
IOUT = 150 mA, VIN = 14 V, MON = VOUT
−
12
19
mA
151
300
−
mA
Current Limit
−
3. Voltage range specified in Output Stage of the Electrical Characteristics in boldface type.
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NCV8502 Series
ELECTRICAL CHARACTERISTICS (continued) (IOUT = 1.0 mA; −40°C ≤ TJ ≤ 150°C; VIN = dependent on voltage option (Note 4);
unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage
Short Circuit Output Current
VOUT = 0 V
40
190
−
mA
Thermal Shutdown
(Guaranteed by Design)
150
180
−
°C
RESET Threshold for 2.5 V Option
HIGH (VRH)
LOW (VRL)
5.5 V ≤ VIN ≤ 26 V (Note 5)
VOUT Increasing
VOUT Decreasing
2.28
2.25
2.350
2.300
0.98 × VOUT
0.97 × VOUT
V
V
RESET Threshold for 3.3 V Option
HIGH (VRH)
LOW (VRL)
5.5 V ≤ VIN ≤ 26 V (Note 5)
VOUT Increasing
VOUT Decreasing
3.00
2.97
3.102
3.036
0.98 × VOUT
0.97 × VOUT
V
V
RESET Threshold for 5.0 V Option
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
4.55
4.50
4.70
4.60
0.98 × VOUT
0.97 × VOUT
V
V
RESET Threshold for 8.0 V Option
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
7.05
7.00
7.52
7.36
0.98 × VOUT
0.97 × VOUT
V
V
RESET Threshold for 10 V Option
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
8.60
8.50
9.40
9.20
0.98 × VOUT
0.97 × VOUT
V
V
Output Voltage
Low (VRLO)
1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k
−
0.1
0.4
V
1.4
1.8
2.2
V
−
−
0.1
V
Reset Function (RESET)
DELAY Switching Threshold (VDT)
−
DELAY Low Voltage
VOUT < RESET Threshold Low(min)
DELAY Charge Current
DELAY = 1.0 V, VOUT > VRH
1.5
2.5
3.5
mA
DELAY Discharge Current
DELAY = 1.0 V, VOUT = 1.5 V
5.0
−
−
mA
1.23
1.31
1.39
V
1.10
1.20
1.31
V
20
50
100
mV
−0.5
0.1
0.5
mA
−
0.1
0.4
V
−0.5
−
0.5
mA
Reset Adjust Switching Voltage
(VR(ADJ))
−
FLAG/Monitor
Monitor Threshold
Increasing and Decreasing
Hysteresis
−
Input Current
MON = 2.0 V
Output Saturation Voltage
MON = 0 V, IFLAG = 1.0 mA
Voltage Adjust (Adjustable Output only)
Input Current
VADJ = 1.28 V
4. Voltage range specified in Output Stage of the Electrical Characteristics in boldface type.
5. For VIN ≤ 5.5 V, a RESET = Low may occur with the output in regulation.
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NCV8502 Series
PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT
Package Pin Number
SO−8
SOW−16
E PAD
Pin Symbol
1
7
VIN
2
8
MON
3, 4
3−6, 9−12,
14, 15
NC
5
13
GND
Ground. All GND leads must be connected to Ground.
6
16
FLAG
Open collector output from early warning comparator.
7
1
VADJ
Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage.
8
2
VOUT
±2.0%, 150 mA output.
Function
Input Voltage.
Monitor. Input for early warning comparator. If not needed connect to VOUT.
No connection.
PACKAGE PIN DESCRIPTION, FIXED OUTPUT
Package Pin Number
SO−8
SOW−16
E PAD
Pin Symbol
1
7
VIN
2
8
MON
Monitor. Input for early warning comparator. If not needed connect to VOUT.
3
9
RADJ
Reset Adjust. If not needed connect to ground.
4
10
DELAY
5
13
GND
6
16
RESET
7
1
FLAG
Open collector output from early warning comparator.
8
2
VOUT
±2.0%, 150 mA output.
−
3−6, 11, 12,
14, 15
NC
Function
Input Voltage.
Timing capacitor for RESET function.
Ground. All GND leads must be connected to Ground.
Active reset (accurate to VOUT ≥ 1.0 V)
No connection.
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NCV8502 Series
TYPICAL PERFORMANCE CHARACTERISTICS
3.35
5.01
VOUT = 5.0 V
VIN = 14 V
IOUT = 5.0 mA
VOUT = 3.3 V
VIN = 14 V
IOUT = 5.0 mA
3.34
3.33
VOUT (V)
VOUT (V)
5.00
4.99
3.32
3.31
3.30
3.29
3.28
4.98
−40 −25 −10
5
20 35 50 65
Temperature (°C)
80
95 110 125
3.27
−40 −25 −10
Figure 2. Output Voltage vs. Temperature
1.2
14
VIN = 12 V
10
+25°C
IQ (mA)
IQ (mA)
95 110 125
+125°C
0.6
−40°C
0.4
+125°C
8
+25°C
6
−40°C
4
0.2
2
0
5
10
15
IOUT (mA)
20
0
25
Figure 4. Quiescent Current vs. Output Current
0
15
30
45
60 75 90
IOUT (mA)
105 120 135 140
Figure 5. Quiescent Current vs. Output Current
120
7
T = 25°C
6
T = 25°C
100
IOUT = 100 mA
5
4
3
1
20
IOUT = 10 mA
6
8
10
12
14
16 18
VIN (V)
60
49
IOUT = 50 mA
2
IOUT = 100 mA
80
IQ (mA)
IQ (mA)
80
12
0.8
0
20 35 50 65
Temperature (°C)
Figure 3. Output Voltage vs. Temperature
VIN = 12 V
1.0
0
5
20
22
24
0
26
Figure 6. Quiescent Current vs. Input Voltage
6
8
10
12
14
16 18
VIN (V)
20
22
24
Figure 7. Quiescent Current vs. Input Voltage
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26
NCV8502 Series
TYPICAL PERFORMANCE CHARACTERISTICS
450
1000
Unstable Region
100
350
+125°C
250
10 V
+25°C
ESR (W)
300
−40°C
200
150
2.5 V 3.3 V
5V
1.0
0.1
VOUT = 5.0 V, 8.0 V, or 10 V
50
0
8V
10
Stable Region
100
0
25
50
75
100
125
CVOUT = 10 mF
0.01
150
0
IOUT (mA)
10
20
30
40
60
70
80
Figure 9. Output Stability with Output
Voltage Change
1000
Unstable Region
CVout = 10 mF
100
CVout = 0.1 mF
10
1.0
Stable Region
0.1
0.01
50
OUTPUT CURRENT (mA)
Figure 8. Dropout Voltage vs. Output Current
ESR (W)
Dropout Voltage (mV)
400
0
10
20
30 40 50 60 70 80
OUTPUT CURRENT (mA)
90 100 110
Figure 10. Output Stability with Output
Capacitor Change
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90
100
NCV8502 Series
VOUT
VIN
Current Source
(Circuit Bias)
IBIAS
Current Limit
Sense
+
+
−
RADJ
IBIAS
+ −
VBG
RESET
+
−
VBG
1.8 V
Fixed Voltage only
Thermal
Protection
3.0 mA
Delay
Error Amplifier
IBIAS
Bandgap
Reference
VBG
VBG
−
Figure 11. Block Diagram
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8
VADJ
GND
IBIAS
+
MON
20 k
Adjustable
Version only
FLAG
NCV8502 Series
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8502 contains the microprocessor compatible
control function RESET (Figure 12).
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
VIN
RESET
Threshold
VOUT
FLAG/Monitor Function
DELAY
Threshold
(VDT)
DELAY
RESET
An on−chip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 14). The typical
threshold is 1.20 V on the MON pin.
Td
Td
Figure 12. Reset and Delay Circuit Wave Forms
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until VOUT is within 6.0% of the regulated output
voltage, or when VOUT drops out of regulation,and is lower
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for VOUT as low
as 1.0 V.
VBAT
MON
RRST
RESET
DELAY
I/O
FLAG
RESET
Figure 14. FLAG/Monitor Function
Voltage Adjust
to mP and
System
Power
VOUT
mP
COUT
RADJ
RESET
DELAY GND
The reset threshold can be made lower by connecting an
external resistor divider to the RADJ lead from the VOUT
lead, as displayed in Figure 13. This lead is grounded to
select the default value of 4.6 V.
NCV8502
VCC
NCV8502
Adjustable Reset Function
RADJ
VOUT
VIN
Figure 15 shows the device setup for a user configurable
output voltage. The feedback to the VADJ pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.28 V
typical).
COUT
≈5.0 V
VOUT
to mP and
RESET
Port
NCV8502
CDELAY
VADJ
15 k
COUT
1.28 V
5.1 k
Figure 13. Adjustable RESET
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically 2.5 mA)
to the external DELAY capacitor during the following
proceedings:
Figure 15. Adjustable Output Voltage
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NCV8502 Series
APPLICATION NOTES
VIN
CIN*
0.1 mF
NCV8502
MJD31C
VOUT
VIN
VBAT
C2
0.1 mF
R1
294 k
NCV8502
RRST
COUT**
10 mF
RESET
5.0 V
>1 Amp
VADJ
VOUT
C1
47 mF
*CIN required if regulator is located far from the power supply filter
**COUT required for stability. Capacitor must operate at minimum
temperature expected
R2
100 k
Figure 18. Test and Application Circuit Showing
Output Compensation
Figure 16. Additional Output Current
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
Adding Capability
Figure 16 shows how the adjustable version of parts can
be used with an external pass transistor for additional current
capability. The setup as shown will provide greater than 1
Amp of output current.
tDELAY +
ƪCDELAY(Vdt * Reset Delay Low Voltage)ƫ
Delay Charge Current
Example:
Using CDELAY = 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for Vdt = 1.8 V.
Use the typical value for Delay Charge Current = 2.5 mA.
FLAG MONITOR
Figure 17 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 14. As the output voltage
falls (VOUT), the Monitor threshold is crossed. This causes
the voltage on the FLAG output to go low sending a warning
signal to the microprocessor that a RESET signal may occur
in a short period of time. TWARNING is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET shutdown signal.
tDELAY +
ƪ33 nF(1.8 * 0)ƫ
2.5 mA
+ 23.8 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start−up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints.
The value for the output capacitor COUT shown in Figure 18
should work for most applications, however it is not
necessarily the optimized solution.
VOUT
MON
FLAG Monitor
Ref. Voltage
RESET
FLAG
TWARNING
Figure 17. FLAG Monitor Circuit Waveform
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NCV8502 Series
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 19) is:
Thermal Resistance,
Junction to Ambient, RqJA, (°C/W)
PD(max) + [VIN(max) * VOUT(min)] IOUT(max)
100
(eq. 1)
) VIN(max)IQ
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
T
RQJA + 150° C * A
PD
VIN
}
70
60
50
0
200
400
600
Copper Area (mm2)
800
Figure 20. 16 Lead SOW (Exposed Pad), qJA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625, G−10/R−4
(eq. 2)
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
IOUT
SMART
REGULATOR®
80
40
The value of RqJA can then be compared with those in the
package section of the data sheet. Those packages with
RqJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
90
VOUT
RqJA + RqJC ) RqCS ) RqSA
(eq. 3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it too is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
Control
Features
IQ
Figure 19. Single Output Regulator with Key
Performance Parameters Labeled
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11
NCV8502 Series
ORDERING INFORMATION
Package
Shipping†
NCV8502DADJG
SO−8
(Pb−Free)
98 Units/Rail
NCV8502DADJR2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
NCV8502D25G
SO−8
(Pb−Free)
98 Units/Rail
NCV8502D25R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
NCV8502D33G
SO−8
(Pb−Free)
98 Units/Rail
NCV8502D33R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
NCV8502D50G
SO−8
(Pb−Free)
98 Units/Rail
NCV8502D50R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
NCV8502D80G
SO−8
(Pb−Free)
98 Units/Rail
NCV8502D80R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
NCV8502D100G
SO−8
(Pb−Free)
98 Units/Rail
NCV8502D100R2G
SO−8
(Pb−Free)
2500 Tape & Reel
SOW−16 Exposed Pad
(Pb−Free)
47 Units/Rail
SOW−16 Exposed Pad
(Pb−Free)
1000 Tape & Reel
Device
NCV8502PDWADJG
Output Voltage
Adjustable
NCV8502PDWADJR2G
NCV8502PDW25G
2.5 V
NCV8502PDW25R2G
NCV8502PDW33G
3.3 V
NCV8502PDW33R2G
NCV8502PDW50G
5.0 V
NCV8502PDW50R2G
NCV8502PDW80G
8.0 V
NCV8502PDW80R2G
NCV8502PDW100G
10 V
NCV8502PDW100R2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
http://onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY, EXPOSED PAD
CASE 751AG
ISSUE B
SCALE 1:1
−U−
A
0.25 (0.010)
M
W
9
B
1
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
M
16
P
R x 45_
8
−W−
G 14
TOP VIEW
PIN 1 I.D.
PL
DETAIL E
C
F
−T−
0.10 (0.004) T
K
D 16 PL
0.25 (0.010)
T U
M
SEATING
PLANE
W
S
S
J
SIDE VIEW
DETAIL E
1
DIM
A
B
C
D
F
G
H
J
K
L
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
3.45
3.66
0.25
0.32
0.00
0.10
4.72
4.93
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.136
0.144
0.010
0.012
0.000
0.004
0.186
0.194
0_
7_
0.395
0.415
0.010
0.029
GENERIC
MARKING DIAGRAM*
H
EXPOSED PAD
DATE 31 MAY 2016
8
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AWLYYWWG
L
16
9
BOTTOM VIEW
XXXXX
A
WL
YY
WW
G
SOLDERING FOOTPRINT*
0.350
Exposed
Pad
0.175
0.050
CL
0.200
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.188
CL
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
0.376
0.074
0.150
0.024
DIMENSIONS: INCHES
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON21237D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SOIC−16, WB EXPOSED PAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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