NCV87706DT50RKG

NCV8770 LDO Regulator - Ultra Low Iq, Reset 350 mA The NCV8770 is 350 mA LDO regulator with integrated reset functions dedicated for microprocessor applications. Its robustness allows NCV8770 to be used in severe automotive environments. Ultra low quiescent current as low as 21 mA typical makes it suitable for applications permanently connected to battery requiring ultra low quiescent current with or without load. This feature is especially critical when modules remain in active mode when ignition is off. The NCV8770 contains protection functions as current limit, thermal shutdown and reverse output current protection. http://onsemi.com MARKING DIAGRAMS DPAK−5 DT SUFFIX CASE 175AA 770yxxG ALYWW D2PAK−5 D5S SUFFIX CASE 936A NC V8770yxx AWLYWWG Features • • • • • • • • • Output Voltage Options: 5 V Output Voltage Accuracy: ±1.5% (TJ = 25°C to 125°C) Output Current up to 350 mA Ultra Low Quiescent Current: typ 21 mA (max 28 mA) Very Wide Range of Cout and ESR Values for Stability Microprocessor Compatible Control Functions: − Reset with Adjustable Power−On Delay Wide Input Voltage Operation Range: up to 40 V Protection Features − Current Limitation − Thermal Shutdown These are Pb−Free Devices y xx A WL, L Y WW G or G Typical Applications • • • • Body Control Module Instruments and Clusters Occupant Protection and Comfort Powertrain VBAT Cin 0.1 mF Vout Vin ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. Vout NCV8770 = Timing and Reset Threshold Option = Voltage Option = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Cout 1 mF VDD Microprocessor DT RO RESET GND Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2013 September, 2019 − Rev. 1 1 Publication Order Number: NCV8770/D NCV8770 Vin Vout Thermal Shutdown RO Driver With Erorr Amplifier Current Reset Comparator Reset Driver Limit Reference Timing DT Circuit * Timer GND * Pull−Down Resistor (typ 150 kW) active only in Reset State Figure 2. Simplified Block Diagram PIN CONNECTIONS PIN Tab, 1. Vin 2. RO 3. GND 4. DT 5. Vout PIN Tab, 1. Vin 2. RO 3. GND 4. DT 5. Vout 1 1 D2PAK−5 DPAK−5 Figure 3. Pin Connections PIN FUNCTION DESCRIPTION Pin No. DPAK−5 D2PAK−5 Pin Name 1 Vin Positive Power Supply Input. Connect 0.1 mF capacitor to ground. 2 RO Reset Output. 30 kW internal Pull−up resistor connected to Vout. RO goes Low when Vout drops by more than 7% (typ) from its nominal value (for NCV8770y devices with y = 1,2,3,...) or more than 10% (typ) from its nominal value (for NCV8770y devices with y = A, B, C,...). 3, TAB GND 4 DT Reset Delay Time Select. Short to GND or connected to Vout to select time. 5 Vout Regulated Output Voltage. Connect 1 mF capacitor with ESR < 100 W to ground. − NC Not Connected − GND Description Power Supply Ground. Exposed Pad is Connected to Ground. http://onsemi.com 2 NCV8770 ABSOLUTE MAXIMUM RATINGS Rating Input Voltage (Note 1) Symbol Min Max Unit Vin −0.3 − 40 45 V DC Transient, t < 100 ms Input Current Iin −5 − mA Output Voltage (Note 2) Vout −0.3 5.5 V Output Current Iout −3 Current Limited mA DT (Reset Delay Time Select) Voltage VDT −0.3 5.5 V DT (Reset Delay Time Select) Current IDT −1 1 mA Reset Output Voltage VRO −0.3 5.5 V Reset Output Current IRO −3 3 mA Junction Temperature TJ −40 150 °C Storage Temperature TSTG −55 150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. 5.5 V or (Vin + 0.3 V) (whichever is lower). ESD CAPABILITY (Note 3) Rating Symbol Min Max Unit ESDHBM −2 2 kV ESD Capability, Machine Model ESDMM −200 200 V ESD Capability, Charged Device Model ESDCDM −1 1 kV Max Unit ESD Capability, Human Body Model 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) ESD Charge Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) LEAD SOLDERING TEMPERATURE AND MSL (Note 4) Rating Moisture Sensitivity Level Symbol DPAK−5 D2PAK−5 Min MSL Lead Temperature Soldering Reflow (SMD Styles Only), Pb−Free Versions TSLD 1 1 − − 265 peak °C 4. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. THERMAL CHARACTERISTICS (Note 5) Rating Symbol Value Thermal Characteristics, DPAK−5 Thermal Resistance, Junction−to−Air (Note 6) Thermal Reference, Junction−to−Case (Note 6) RqJA RYJC 56 8.4 Thermal Characteristics, D2PAK−5 Thermal Resistance, Junction−to−Air (Note 6) Thermal Reference, Junction−to−Case (Note 6) RqJA RYJC 53 8.4 Unit °C/W °C/W 5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 6. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. RECOMMENDED OPERATING RANGE (Note 7) Rating Symbol Min Max Unit Input Voltage (Note 8) Vin 5.5 40 V Junction Temperature TJ −40 150 °C 7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 8. Minimum Vin = 5.5 V or (Vout + VDO), whichever is higher. http://onsemi.com 3 NCV8770 ELECTRICAL CHARACTERISTICS Vin = 13.2 V, Cin = 0.1 mF, Cout = 1 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 9 and 10) Parameter Test Conditions Symbol TJ = 25 °C to 125 °C Vin = 5.575 V to 16 V, Iout = 0.1 mA to 200 mA Vout Min Typ Max 4.925 (−1.5 %) 5.0 5.075 (+1.5%) 4.9 4.9 (−2 %) 5.0 5.0 5.1 5.1 (+2%) 4.9 (−2 %) 5.0 5.1 (+2%) Unit REGULATOR OUTPUT Output Voltage (Accuracy %) Output Voltage (Accuracy %) Vin = 5.6 V to 40 V, Iout = 0.1 mA to 200 mA Vin = 5.975 V to 16 V, Iout = 0.1 mA to 350 mA Vout V Output Voltage (Accuracy %) TJ = −40°C to 125°C Vin = 5.975 V to 28 V, Iout = 0 mA to 350 mA Line Regulation Vin = 6 V to 28 V, Iout = 5 mA Regline −20 0 20 mV Load Regulation Iout = 0.1 mA to 350 mA Regload −35 0 35 mV − − 250 440 500 875 − − 21 − 27 28 Dropout Voltage (Note 11) Vout V VDO Iout = 200 mA Iout = 350 mA V mV QUIESCENT CURRENT Quiescent Current (Iq = Iin − Iout) Iout = 0.1 mA, TJ = 25°C Iout = 0.1 mA to 350 mA, TJ ≤ 125°C Iq mA CURRENT LIMIT PROTECTION Current Limit Vout = 0.96 x Vout_nom ILIM 400 − 1100 mA Short Circuit Current Limit Vout = 0 V ISC 400 − 1100 mA PSRR − 54 − dB − 2.0 − − 0.8 − − − 1.0 PSRR Power Supply Ripple Rejection (Note 12) f = 100 Hz, 0.5 Vpp DT (RESET DELAY TIME SELECT) Vth(DT) DT Threshold Voltage Logic Low Logic High DT Input Current VDT = 5 V IDT V mA 9. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 10. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. 12. Values based on design and/or characterization. 13. See APPLICATION INFORMATION section for Reset Thresholds and Reset Delay Time Options http://onsemi.com 4 NCV8770 ELECTRICAL CHARACTERISTICS Vin = 13.2 V, Cin = 0.1 mF, Cout = 1 mF, for typical values TJ = 25°C, for min/max values TJ = −40°C to 150°C; unless otherwise noted. (Notes 9 and 10) Parameter Test Conditions Symbol Min Typ Max Unit RESET OUTPUT RO Output Voltage Reset Threshold (Note 13) (NCV8770y) where y = 1,2,3,... (NCV8770y) where y = A,B,C,... Vout decreasing, Vin > 5.5 V VRT %Vout 90 87 93 90 96 93 VRH − 2.0 − %Vout IROmax 1.75 − − mA VROL − 0.15 0.25 V Reset Output High Voltage VROH 4.5 − − V Integrated Reset Pull−up Resistor RRO 15 30 50 kW tRD 3.2 102.4 −20% 4.0 128 4.8 153.6 +20% ms tRR 16 25 38 ms Thermal Shutdown Temperature (Note 12) TSD 150 175 195 °C Thermal Shutdown Hysteresis (Note 12) TSH − 25 − °C 5.0 V 5.0 V Reset Hysteresis Maximum Reset Sink Current Vout = 4.5 V, VRO = 0.25 V Reset Output Low Voltage Vout > 1 V, IRO < 200 mA Reset Delay Time (Note 13) Min Available Time, DT connected to GND Max Available Time, DT connected to Vout Reset Reaction Time (see Figure 21) THERMAL SHUTDOWN 9. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 10. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TA [ TJ. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 11. Measured when output voltage falls 100 mV below the regulated voltage at Vin = 13.2 V. 12. Values based on design and/or characterization. 13. See APPLICATION INFORMATION section for Reset Thresholds and Reset Delay Time Options http://onsemi.com 5 NCV8770 TYPICAL CHARACTERISTICS 250 Vin = 13.2 V Iout = 100 mA 27 26 Iq, QUIESCENT CURRENT (mA) Iq, QUIESCENT CURRENT (mA) 28 25 24 23 22 21 20 19 18 −40 −20 0 20 40 60 80 200 150 100 50 0 100 120 140 160 Iout = 0 mA TJ = 25°C 0 5 10 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Quiescent Current vs. Temperature 26 TJ = 150°C 25 24 23 22 TJ = −40°C 21 20 TJ = 25°C 19 18 0 50 100 150 200 250 35 40 300 5.00 4.95 4.90 −40 −20 350 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) IOUT, OUTPUT CURRENT (mA) Figure 7. Output Voltage vs. Temperature 6 800 VDO, DROPOUT VOLTAGE (mV) Iout = 1 mA Vout, OUTPUT VOLTAGE (V) 30 Vin = 13.2 V Iout = 100 mA 5.05 Figure 6. Quiescent Current vs. Output Current 5 4 3 TJ = 25°C 2 TJ = 150°C 1 0 25 5.10 Vin = 13.2 V 27 20 Figure 5. Quiescent Current vs. Input Voltage Vout, OUTPUT VOLTAGE (V) Iq, QUIESCENT CURRENT (mA) 28 15 Vin, INPUT VOLTAGE (V) TJ = −40°C 0 1 2 3 4 5 6 7 700 500 TJ = 25°C 400 300 200 TJ = −40°C 100 0 0 8 TJ = 150°C 600 50 100 150 200 250 300 Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 8. Output Voltage vs. Input Voltage Figure 9. Dropout vs. Output Current http://onsemi.com 6 350 NCV8770 800 800 700 700 ILIM, ISC, CURRENT LIMIT (mA) VDO, DROPOUT VOLTAGE (mV) TYPICAL CHARACTERISTICS 600 Iout = 350 mA 500 400 Iout = 200 mA 300 200 100 0 −40 −20 ISC @ Vout = 0 V 600 ILIM @ Vout = 4.8 V 500 400 300 200 100 0 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) TJ = 25°C 0 Figure 10. Dropout vs. Temperature 700 650 ISC @ Vout = 0 V 600 550 ILIM @ Vout = 4.8 V 500 450 400 −40 −20 0 20 40 60 80 15 20 25 30 Vin, INPUT VOLTAGE (V) 35 40 100 Vin = 13.2 V 750 10 Figure 11. Output Current Limit vs. Input Voltage ESR, STABILITY REGION (W) ILIM, ISC, CURRENT LIMIT (mA) 800 5 10 1 STABLE REGION 0.1 0.01 100 120 140 160 Vin = 13.2 V TJ = −40°C to 150°C Cout = 1 mF − 100 mF 0 50 100 150 200 250 300 350 TJ, JUNCTION TEMPERATURE (°C) Iout, OUTPUT CURRENT (mA) Figure 12. Output Current Limit vs. Temperature Figure 13. Cout ESR Stability Region vs. Output Current TJ = 25°C Iout = 1.0 mA Cout = 10 mF trise/fall = 1 ms (Vin) 12.2 V 14.2 V Vin (1 V/div) 13 V TJ = 25°C Vin = 13.2 V Cout = 10 mF trise/fall = 1 ms (Iout) 0.1 mA 100 mA Iout (50 mA/div) 5.16 V 5.16 V 5V Vout (100 mV/div) Vout (100 mV/div) 5V 4.95 V 4.77 V TIME (1 ms/div) TIME (50 us/div) Figure 14. Line Transients Figure 15. Load Transients http://onsemi.com 7 NCV8770 TYPICAL CHARACTERISTICS TJ = 25°C VEN = Vin Rout = 5 kW 100 TJ = 25°C Vin = 13.2 V $ 0.5 Vpp Cout = 1 mF Iout = 1.0 mA 90 80 Vin (5 V/div) PSRR (dB) 70 Vout (5 V/div) 60 50 40 30 20 10 VRO (5 V/div) 0 10 100 1000 10000 TIME (100 ms/div) f, FREQUENCY (Hz) Figure 16. Power Up/Down Response Figure 17. PSRR vs. Frequency 5000 TJ = 25°C Vin = 13.2 V Cout = 1 mF Iout = 350 mA 4500 NOISE DENSITY (nV/√Hz) 100000 4000 3500 3000 2500 2000 1500 1000 500 0 10 100 1000 10000 100000 f, FREQUENCY (Hz) Figure 18. Noise vs. Frequency 20 Vin = 13.2 V tRD, RESET DELAY TIME (ms) VRT, RESET THRESHOLD (V) 4.80 4.75 4.70 4.65 4.60 −40 −20 0 20 40 60 80 Vin = 13.2 V 19 18 17 16 15 14 13 12 −40 −20 100 120 140 160 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 19. Reset Threshold vs. Temperature Figure 20. Reset Delay Time vs. Temperature http://onsemi.com 8 NCV8770 Vin t Vout < tRR VRT + VRH VRT VRO t tRD tRR VROH VROL t Figure 21. Reset Function and Timing Diagram DEFINITIONS General Current Limit and Short Circuit Current Limit All measurements are performed using short pulse low duty cycle techniques to maintain junction temperature as close as possible to ambient temperature. Current Limit is value of output current by which output voltage drops below 96% of its nominal value. Short Circuit Current Limit is output current value measured with output of the regulator shorted to ground. Output voltage The output voltage parameter is defined for specific temperature, input voltage and output current values or specified over Line, Load and Temperature ranges. PSRR Power Supply Rejection Ratio is defined as ratio of output voltage and input voltage ripple. It is measured in decibels (dB). Line Regulation The change in output voltage for a change in input voltage measured for specific output current over operating ambient temperature range. Line Transient Response Typical output voltage overshoot and undershoot response when the input voltage is excited with a given slope. Load Regulation The change in output voltage for a change in output current measured for specific input voltage over operating ambient temperature range. Load Transient Response Typical output voltage overshoot and undershoot response when the output current is excited with a given slope between low−load and high−load conditions. Dropout Voltage The input to output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. It is measured when the output drops 100 mV below its nominal value. The junction temperature, load current, and minimum input supply requirements affect the dropout level. Thermal Protection Quiescent Current Maximum Package Power Dissipation Quiescent Current (Iq) is the difference between the input current (measured through the LDO input pin) and the output load current. The power dissipation level is maximum allowed power dissipation for particular package or power dissipation at which the junction temperature reaches its maximum operating value, whichever is lower. Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 175°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating. http://onsemi.com 9 NCV8770 APPLICATIONS INFORMATION The NCV8770 regulator is self−protected with internal thermal shutdown and internal current limit. Typical characteristics are shown in Figure 4 to Figure 21. RESET DELAY AND RESET THRESHOLD OPTIONS Input Decoupling (Cin) A ceramic or tantalum 0.1 mF capacitor is recommended and should be connected close to the NCV8770 package. Higher capacitance and lower ESR will improve the overall line and load transient response. If extremely fast input voltage transients are expected then appropriate input filter must be used in order to decrease rising and/or falling edges below 50 V/ms for proper operation. The filter can be composed of several capacitors in parallel. Output Decoupling (Cout) The NCV8770 is a stable component and does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. Stability region of ESR vs Output Current is shown in Figure 13. The minimum output decoupling value is 1 mF and can be augmented to fulfill stringent load transient requirements. The regulator works with ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. DT = GND Reset Time DT = Vout Reset Time Reset Threshold NCV87701 8 ms 128 ms 93% NCV87702 8 ms 32 ms 93% NCV87703 16 ms 64 ms 93% NCV87704 32 ms 128 ms 93% NCV87705 4 ms 8 ms 93% NCV87706 16 ms 128 ms 93% NCV8770A 8 ms 128 ms 90% NCV8770B 8 ms 32 ms 90% NCV8770C 16 ms 64 ms 90% NCV8770D 32 ms 128 ms 90% NCV8770E 4 ms 8 ms 90% NCV8770F 16 ms 128 ms 90% NOTE: The timing values can be selected from the following list: 4, 8, 16, 32, 64, 128 ms. Contact factory for options not included in ORDERING INFORMATION table on following page. Thermal Considerations As power in the NCV8770 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. When the NCV8770 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power applications. The maximum dissipation the NCV8770 can handle is given by: Reset Operation A reset signal is provided on the Reset Output (RO) pin to provide feedback to the microprocessor of an out of regulation condition. The timing diagram of reset function is shown in Figure 21. This is in the form of a logic signal on RO. Output voltage conditions below the RESET threshold cause RO to go low. The RO integrity is maintained down to Vout = 1.0 V. For 5 V voltage option, the Reset Output (RO) circuitry includes internal pull−up (30 kW) connected to the output (Vout) No external pull−up is necessary. Reset Delay Time Select P D(max) + Selection of the NCV8770y devices and the state of the DT pin determines the available Reset Delay times. The part is designed for use with DT tied to ground or Vout, but may be controlled by any logic signal which provides a threshold between 0.8 V and 2 V. The default condition for an open DT pin is the slower Reset time (DT = GND condition). Times are in pairs and are highlighted in the chart below. Consult factory for availability. The Delay Time select (DT) pin is logic level controlled and provides Reset Delay time per the chart. Note the DT pin is sampled only when RO is low, and changes to the DT pin when RO is high will not effect the reset delay time. ƪTJ(max) * TAƫ (eq. 1) R qJA Since TJ is not recommended to exceed 150°C, then the NCV8770 soldered on 645 mm2, 1 oz copper area, FR4 can dissipate up to 2.35 W (for D2PAK−5) when the ambient temperature (TA) is 25°C. See Figure 22 for RqJA versus PCB area. The power dissipated by the NCV8770 can be calculated from the following equations: P D + V inǒI q@I outǓ ) I outǒV in * V outǓ (eq. 2) or V in(max) + NOTE: http://onsemi.com 10 P D(max) ) ǒV out I outǓ I out ) I q Items containing Iq can be neglected if Iout >> Iq. (eq. 3) NCV8770 Hints RqJA, THERMAL RESISTANCE (°C/W) 100 Vin and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCV8770 and make traces as short as possible. 90 80 70 DPAK 1 oz D2PAK 1 oz 60 50 40 0 D2PAK 2 oz DPAK 2 oz 100 200 300 400 500 600 COPPER HEAT SPREADER (mm2) 700 Figure 22. Thermal Resistance vs. PCB Copper Area ORDERING INFORMATION Output Voltage Reset Delay Time (DT = GND/Vout) Reset Threshold Marking Package Shipping† NCV87706DT50RKG 5.0 V 16/128 ms 93% 770650G DPAK−5 (Pb−Free) 2500 / Tape & Reel NCV87706DS50R4G 5.0 V 16/128 ms 93% NC V8770650 D2PAK−5 (Pb−Free) 800 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK−5, CENTER LEAD CROP CASE 175AA ISSUE B DATE 15 MAY 2014 SCALE 1:1 −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R R1 Z A S 12 3 4 5 U K F J L H D G 5 PL 0.13 (0.005) M T 2.2 0.086 0.34 5.36 0.013 0.217 5.8 0.228 10.6 0.417 0.8 0.031 SCALE 4:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON12855D INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.020 0.028 0.018 0.023 0.024 0.032 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.045 BSC 0.170 0.190 0.185 0.210 0.025 0.040 0.020 −−− 0.035 0.050 0.155 0.170 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.51 0.71 0.46 0.58 0.61 0.81 4.56 BSC 0.87 1.01 0.46 0.58 2.60 2.89 1.14 BSC 4.32 4.83 4.70 5.33 0.63 1.01 0.51 −−− 0.89 1.27 3.93 4.32 GENERIC MARKING DIAGRAMS* RECOMMENDED SOLDERING FOOTPRINT* 6.4 0.252 DIM A B C D E F G H J K L R R1 S U V Z XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DPAK−5 CENTER LEAD CROP PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 5−LEAD CASE 936A−02 ISSUE E DATE 28 JUL 2021 SCALE 1:1 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxx A WL Y WW G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASH01006A D2PAK 5−LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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