NE521
High−Speed
Dual−Differential
Comparator/Sense Amp
Features
•
•
•
•
http://onsemi.com
TTL-Compatible Strobes and Outputs
Large Common-Mode Input Voltage Range
Operates from Standard Supply Voltages
Pb−Free Packages are Available
MARKING
DIAGRAMS
14
Applications
• MOS Memory Sense Amp
• A-to-D Conversion
• High-Speed Line Receiver
SOIC−14
D SUFFIX
CASE 751A
1
NE521G
AWLYWW
1
MAXIMUM RATINGS
Rating
Supply Voltage
Positive
Negative
Differential Input Voltage
Symbol
Value
V+
V−
+7.0
−7.0
VIDR
"6.0
Input Voltage
Common Mode
Strobe/Gate
VIN
Maximum Power Dissipation (Note 1)
TA = 25°C (Still−Air)
N Package
D Package
PD
Thermal Resistance, Junction−to−Ambient
N Package
D Package
RqJA
Unit
V
14
PDIP−14
N SUFFIX
CASE 646
1
NE521N
AWLYYWWG
1
V
V
"5.0
+5.25
mW
1420
1040
A
WL
Y, YY
WW
G
PIN CONNECTIONS
°C/W
100
145
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
D, N Packages
Operating Temperature Range
TA
0 to 70
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Operating Junction Temperature
TJ
150
°C
Lead Soldering Temperature (10 sec max)
Tsld
+230
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Derate above 25°C at the following rates:
N package at 10 mW/°C
D package at 6.9 mW/°C.
INPUT 1A
1
14
V+
INPUT 1B
2
13
V−
NC
3
12
INPUT 2A
OUTPUT 1Y
4
11
INPUT 2B
STROBE 1G
5
10
NC
STROBE S
6
9
OUTPUT 2Y
GROUND
7
8
STROBE 2G
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 4
1
Publication Order Number:
NE521/D
NE521
LOGIC FUNCTION TABLE
VID (A+, B)
Strobe S
Strobe G
Output (Y)
VID v −VOS
H
H
L
−VOS < VID < VOS
H
H
Undefined
VID w VOS
H
H
H
X
L
X
H
X
X
L
H
(1)
INPUT 1A
(2)
INPUT 1B
(12)
INPUT 2A
(11)
INPUT 2B
(4)
OUTPUT 1Y
(5)
STROBE 1G
STROBE S
(6)
(9)
(8)
OUTPUT 3Y
STROBE 2G
Figure 1. Block Diagram
14
V+
R2
R17
R1
1
−
Q2
Q8
R5
V−
R24
4
6
5
Q13
R3
R14
Q11
R15
R23
R22
D1
D2
Q27
R6
7
R8
R7
R10
Q18
Q16
11
Q7
Q5
Q6
Q28
Q10
R4
12
Q29
Q26
+
Q9
13
R25
Q30
R16
D6
D7
Q1
R21
Q25
Q3
Q4
2
R20
Q17
R9
Q36
Q19
D3
R28
R29
+
−
Q35
Q15
Q14
D4
Q20
R12
R11
D5
Q22
Q23
8
Q24
R18
Q21
R19
Q32
Q31
Figure 2. Equivalent Schematic
http://onsemi.com
2
Q34
Q32
R26
V+
9
R30
R27
R34
NE521
DC ELECTRICAL CHARACTERISTICS (V+ = +5.0 V; V− = −5.0 V, TA = 0°C to +70°C, unless otherwise noted.)
Limits
Test Conditions
Symbol
Input Offset Voltage
At 25°C
Overtemperature Range
V+ = +4.75 V; V− = −4.75 V
VOS
Input Bias Current
At 25°C
Overtemperature Range
V+ = +5.25 V; V− = −5.25 V
IBIAS
Input Offset Current
At 25°C
Overtemperature Range
V+ = +5.25 V; V− = −5.25 V
IOS
Common-Mode Voltage Range
V+ = +4.75 V; V− = −4.75 V
VCM
Input Current
High
V+ = +5.25 V; V− = −5.25 V
VIH = 2.7 V
1G or 2G Strobe
Common Strobe S
IIH
Characteristic
Input Current
Low
Output Voltage
High
Low
VIL = 0.5 V
1G or 2G Strobe
Common Strobe S
IIL
VI(S) = 2.0 V
V+ = +4.75 V; V− = −4.75 V;
ILOAD = −1.0 mA
V+ = +5.25 V; V− = −5.25 V;
ILOAD = 20 mA
Supply Voltage
Positive
Negative
−
Supply Current
Positive
Negative
V+ = +5.25 V; V− = −5.25 V;
TA = 25°C
Short−Circuit Output Current
−
VOH
Min
Typ
Max
−
−
6.0
−
7.5
10
−
−
7.5
−
20
40
−
−
1.0
−
5.0
12
−3.0
−
+3.0
Unit
mV
mA
mA
V
mA
−
−
−
−
50
100
−
−
−
−
−2.0
−4.0
2.7
3.4
VOL
mA
V
0.5
V
V+
V−
4.75
−4.75
5.0
−5.0
5.25
−5.25
ICC+
ICC−
−
−
27
−15
35
−28
ISC
−40
−
−100
mA
mA
AC ELECTRICAL CHARACTERISTICS (TA = 25°C; RL = 280 W; CL = 15 pF, V+ = 5.0 V; V− = 5.0 V, guaranteed by characterization)
Limits
Characteristic
From Input
To Output
Symbol
Min
Typ
Max
Amp
Amp
Strobe
Strobe
Output
Output
Output
Output
tPLH(D)
tPHL(D)
tPLH(S)
tPHL(S)
−
−
−
−
9.6
8.2
4.8
3.9
12
9.0
10
6.0
−
−
fMAX
40
55
−
Unit
Large−Signal Switching Speed
Propagation Delay
Low to High (Note 2)
High to Low (Note 2)
Low to High (Note 3)
High to Low (Note 3)
Max. Operating Frequency
ns
2. Response time measured from 0 V point of "100 mVP-P 10 MHz square wave to the 1.5 V point of the output.
3. Response time measured from 1.5 V point of input to 1.5 V point of the output.
http://onsemi.com
3
MHz
NE521
3
100mV
2
5mV
20mV
1
10mV
0
100
50
0
0
5
10
15
20
25
TA = 25oC
VS = +5V
4
3
2
50mV
5mV
1
100mV
10mV
12
TESPONSE TIME (ns)
OUTPUT VOLTAGE (V)
VS = +5V
TA = 25oC
4
INPUT VOLTAGE (mV)
INPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
TYPICAL PERFORMANCE CHARACTERISTICS
0
100
30
0
5
10
4
15
20
25
60
30
20
Figure 4. Response Time for
Various Input Overdrives
PROPAGATION DELAY (ns)
8
TPD (HL)
6
16
14
12
10
TPD (LH)
8
TPD (HL)
6
3.0
2.0
1.0
VOL
2
20
30
40
50
60
70
100
1000
11
1.0
INPUT OFSET CURRENT ( μ A)
INPT BIAS CURRENT ( μ A)
1.1
10
9
8
7
6
+25
o
Figure 8. Output Voltage vs.
Ambient Temperature
0.9
0.8
0.7
0.6
0.5
−25
+25
+75
AMBIENT TEMPERATURE (oC)
+125
−75
−25
+25
+75
AMBIENT TEMPERATURES (oC)
Figure 9. Input Bias Current
vs. Ambient Temperature
Figure 10. Input Offset
Current vs. Ambient
Temperature
http://onsemi.com
4
+75
AMBIENT TEMPERATURE ( C)
Figure 7. Propagation Delay
for Various Input Voltages
12
−75
−25
−75
INPUT VOLTAGE (m Vp−p)
INPUT VOLTAGE (mVp−p)
Figure 6. Propagation Delay
for Various Input Voltages
+140
VOH
4
10
+100
4.0
VS = +5V
10MHz SQUARE
WAVE INPUT
TA = 25oC
18
TPD (LH)
+60
Figure 5. Response Time
vs. Temperature
OUTPUT VOLTAGE (V)
VS = +5V
10MHz SQUARE
WAVE INPUT
TA = 25oC
−20
AMBIENT TEMPERATURE (oC)
TIME — nS
20
PROPAGATION DELAY (ns)
TPD (HL)
6
2
0
Figure 3. Response Time for
Various Input Overdrives
10
TPD (LH)
8
50
TIME — nS
12
10
+125
+125
NE521
ORDERING INFORMATION
Device
Temperature Range
Package
NE521D
SOIC−14
NE521DG
SOIC−14
(Pb−Free)
NE521DR2
NE521DR2G
Shipping†
55 Units/Rail
SOIC−14
0 to +70°C
SOIC−14
(Pb−Free)
NE521N
PDIP−14
NE521NG
PDIP−14
(Pb−Free)
2500/Tape & Reel
25 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE S
1
SCALE 1:1
D
A
14
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
D1
e
M
eB
END VIEW
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
DATE 22 APR 2015
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2
1
XXXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
STYLE 1:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO
CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO
CONNECTION
12. EMITTER
13. BASE
14. COLLECTOR
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. DRAIN
2. SOURCE
3. GATE
4. NO
CONNECTION
5. GATE
6. SOURCE
7. DRAIN
8. DRAIN
9. SOURCE
10. GATE
11. NO
CONNECTION
12. GATE
13. SOURCE
14. DRAIN
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. NO CONNECTION
5. SOURCE
6. DRAIN
7. GATE
8. GATE
9. DRAIN
10. SOURCE
11. NO CONNECTION
12. SOURCE
13. DRAIN
14. GATE
STYLE 6:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 7:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON
CATHODE
STYLE 8:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 9:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
STYLE 10:
PIN 1. COMMON
CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON
CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 11:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 12:
PIN 1. COMMON CATHODE
2. COMMON ANODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. COMMON ANODE
7. COMMON CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. ANODE/CATHODE
14. ANODE/CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42428B
PDIP−14
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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