NIS5420MT8TXG

+12 Volt Electronic Fuse NIS5420 Series The NIS5420 eFuse is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. It also includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue operation. Features • • • • • • • • • • Integrated Power Device Power Device Thermally Protected No External Current Shunt Required 8 V to 18 V Input Range 39 mW Typical Internal Charge Pump Internal Undervoltage Lockout Circuit Internal Overvoltage Clamp ESD Ratings: Human Body Model (HBM); 2000 V These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Hard Drives • Mother Board Power Management • Fan Drives www.onsemi.com 4.6 AMP, 12 VOLT ELECTRONIC FUSE MARKING DIAGRAM XXXXX XXXXX ALYWG G WDFN10 CASE 522AA XXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS GND dV/dt En/Flt VCC ILIM NC/ISENSE Src Src Src Src Src WDFN10 (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information in the ordering information section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2018 March, 2021 − Rev. 2 1 Publication Order Number: NIS5420/D NIS5420 Series VCC ENABLE/ FAULT Enable Charge Pump SOURCE Current Limit Thermal Shutdown UVLO Voltage Clamp ILIMIT dv/dt dv/dt Control GND Figure 1. Block Diagram (NIS5420MT3, NIS5420MT4, NIS5420MT5) VCC ENABLE/ FAULT Enable Charge Pump SOURCE Current Limit Thermal Shutdown ILIMIT Current Monitor UVLO Voltage Clamp ISENSE dv/dt dv/dt Control GND Figure 2. Block Diagram (NIS5420MT1, NIS5420MT2, NIS5420MT6, NIS5420MT7, NIS5420MT8 www.onsemi.com 2 NIS5420 Series Table 1. FUNCTIONAL PIN DESCRIPTION Pin Function Description 1 Ground 2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional time delay is not required, this pin should be left open. 3 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be pulled to ground with external open−drain or open collector device to shutdown the eFuse. It can also be used as a status indicator; if the voltage level is intermediate around 1.4 V − the eFuse is in the thermal shutdown, if the voltage level is high around 3 V − the eFuse is operating normally. Do not actively drive this pin to any voltage. Do not connect a capacitor to this pin. 4 ILimit A resistor between this pin and the source pin sets the overload and short circuit current limit levels. 5 NC For NIS5420MT3, NIS5420MT4 and NIS5420MT5 Negative input voltage to the device. This is used as the internal reference for the IC. ISENSE For NIS5420MT1, NIS5420MT2, NIS5420MT6, NIS5420MT7 and NIS5420MT8 load current monitor allows the system to monitor the load current in real time. Connect RSENSE to GND. 6−10 Source This pin is the source of the internal power FET and the output terminal of the fuse. 11 (belly pad) VCC Positive input voltage to the device. MAXIMUM RATINGS Rating Input Voltage, operating, steady−state (VCC to GND, Note 1) Transient (100 ms) Symbol Value Unit VIN −0.6 to 18 −0.6 to 25 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package. Table 2. THERMAL RATINGS Symbol Value Unit Thermal Resistance, Junction−to−Air (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) Rating qJA 90 °C/W Thermal Characterization Parameter, Junction−to−Lead (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−L 27.5 °C/W Thermal Characterization Parameter, Junction−to−Board (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−B 27.5 °C/W Thermal Characterization Parameter, Junction−to−Case Top (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) YJ−T 7.6 °C/W Total Power Dissipation @ TA = 25°C (4 layer High−K JEDEC JESD51−7 PCB, 100 mm2, 2 oz. Cu) Derate above 25°C Pmax 1.39 11.1 W mW/°C TA −40 to 125 °C Operating Ambient Temperature Range Operating Junction Temperature Range Non−operating Temperature Range Lead Temperature, Soldering (10 Sec) www.onsemi.com 3 TJ −40 to 150 °C TSTG −55 to 155 °C TL 260 °C NIS5420 Series Table 3. ELECTRICAL CHARACTERISTICS (VCC = 12 V, CL = 100 mF, dv/dt pin open, RLIMIT = 20 W, Tj = 25°C unless otherwise noted.) Symbol Characteristics Min Typ Max Unit POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) Kelvin ON Resistance (Note 2) TJ = 140°C (Note 3) Off State Output Voltage (VCC = 18 Vdc, VGS = 0 Vdc, RL = R) Tdly − 220 − ms RDSon 30 − 39 60 50 − mW Voff − − 50 mV ID ID − − − − 4.6 3.5 A TSD 150 175 200 °C Continuous Current (TA = 25°C, 100 mm2 copper) (Note 3) (TA = 80°C, minimum copper) THERMAL LATCH Shutdown Temperature (Note 3) Thermal Hysteresis (Auto−retry part only) THyst − 45 − °C TSDRes 10 15 20 ms Output Clamping Voltage (NIS5420MT2, NIS5420MT7) VClamp1 12.5 − 14.5 V Output Clamping Voltage (NIS5420MT1, NIS5420MT4, NIS5420MT5, NIS5420MT6) VClamp2 13.6 − 16 V Thermal Shutdown Response Time UNDER/OVERVOLTAGE PROTECTION Output Clamping Response Time TClamp_Res − − 10 ms Undervoltage Lockout (NIS5420MT1, NIS5420MT3, NIS5420MT4, NIS5420MT5, NIS5420MT6) VUVLO1 7.8 8.5 9.2 V Undervoltage Lockout (NIS5420MT2, NIS5420MT6, NIS5420MT8) VUVLO2 6 6.5 7 V VHyst − 0.80 − V Kelvin Short Circuit Current Limit (RLimit = 20 W, Note 4) ILim−SS 1.76 2.1 2.64 A Kelvin Overload Current Limit (RLimit = 20 W, Note 4) ILim−OL − 4.2 − A Output Voltage Ramp Time (Enable to VOUT = 11.7 V and 10% to 90% − VOUT = 1.2 V to 10.8 V with 12W Load) tslew − 2.0 − ms Maximum Capacitor Voltage Vmax − − VCC V Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V Logic Level High (Output Enabled) Vin−high 1.96 2.6 3.0 V High State Maximum Voltage UVLO Hysteresis CURRENT LIMIT dv/dt CIRCUIT ENABLE/FAULT Vin−max 2.51 4.6 5 V Logic Low Sink Current (Venable = 0 V) Iin−low − −15 −25 mA Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak − − 1.0 mA Fan − − 3.0 Units Bias Current (Operational) IBias − − 450 mA Bias Current (Shutdown) IBias − − 150 mA Minimum Operating Voltage (Notes 3 and 5) Vmin − − 7.7 V ISENSE − 1 − mA/A IACC −10 − 10 % Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) TOTAL DEVICE LOAD CURRENT MONITOR Current Monitor Sense (RSENSE = 1 kW) Current Monitor Sense Accuracy Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse test: Pulse width 300 ms, duty cycle 2%. 3. Verified by design. 4. Refer to explanation of short circuit and overload conditions in application note AND9441. 5. Device will shut down prior to reaching this level based on actual UVLO trip point. 6. For output slew rate calculation with external capacitor, please refer to ”Output Slew Rate (dv/dt)” in the ”Application Information ” section www.onsemi.com 4 NIS5420 Series 100 −40_C TIME (ms) 25_C 10 85_C 1 0 10 30 20 40 50 70 60 80 POWER (W) Figure 3. Thermal Trip Time vs. Power Dissipation +12 V 11 V CC SOURCE NIS5420MT3/ NIS5420MT4/ NIS5420MT5 3 4 RS ENABLE/ FAULT GND dv/dt 1 ENABLE ILIMIT 10 9 8 7 6 LOAD 2 GND Figure 4. Application Circuit with Direct Current Sensing +12 V 11 VCC SOURCE NIS5420MT1/ NIS5420MT2/ NIS5420MT6/ NIS5420MT7/ NIS5420MT8 ILIMIT 3 ENABLE 4 RS ISENSE GND ENABLE 10 9 8 7 6 dv/dt 1 RSENSE 2 GND Figure 5. Application Circuit with Direct Current Sensing www.onsemi.com 5 LOAD NIS5420 Series 24 V 12 V VCC VCC SOURCE SOURCE RS NIS4461 ILIMIT LOAD dv/dt NIS5420 ENABLE/ FAULT ILIMIT ENABLE/ FAULT GND GND ENABLE Figure 6. Common Thermal Shutdown www.onsemi.com 6 dv/dt LOAD NIS5420 Series 2.5 5 2.0 4 VISENSE (V) VISENSE AT 2 A (V) TYPICAL CHARACTERISTICS 1.5 1.0 3 2 1 0.5 0 −60 −40 −20 0 20 40 60 80 100 0 120 0 2 1 4 3 5 6 LOAD CURRENT (A) TA, AMBIENT TEMPERATURE (°C) Figure 8. VISENSE vs. Load Current Figure 7. VISENSE vs. Ambient Temperature 18 17 Vclamp (V) 16 15 14 13 12 11 10 −50 −30 −10 10 30 50 70 90 TJ, JUNCTION TEMPERATURE (°C) Figure 9. Vclamp vs. Junction Temperature Figure 10. Vclamp Test 60 100 90 ID = 1 A 50 80 RDS(on) (mW) RDS(on) (mW) 70 60 50 40 30 20 40 30 20 10 10 0 9 10 11 12 13 14 0 −60 −40 −20 0 20 40 60 80 100 TA, AMBIENT TEMPERATURE (°C) VCC (V) Figure 11. RDS(on) vs. VCC Figure 12. RDS(on) vs. Ambient Temperature www.onsemi.com 7 120 NIS5420 Series TYPICAL CHARACTERISTICS 10 9 Kelvin ILIM_OL @ RLIM = 10 W 6 Kelvin ILIM_OL @ RLIM = 15 W Kelvin ILIM_SC @ RLIM = 10 W CURRENT LIMIT (A) 7 5 Kelvin ILIM_OL @ RLIM = 20 W 4 3 Kelvin ILIM_SC @ RLIM = 15 W 2 1 0 −50 Kelvin ILIM_SC @ RLIM = 20 W −30 −10 10 30 50 70 90 IOL ISC 5 10 15 20 25 TA, AMBIENT TEMPERATURE (°C) 30 35 40 45 50 55 60 RLIM (W) Figure 13. ILIM vs. RLIM over Ambient Temperature Figure 14. ILIM vs. RLIM OUTPUT VOLTAGE RAMP TIME (ms) CURRENT LIMIT (A) 8 13 12 11 10 9 8 7 6 5 4 3 2 1 0 40 35 30 25 20 15 10 5 0 0 100 200 300 400 500 CAPACITANCE FROM dvdt PIN TO GND (pF) Figure 15. Slew Rate Control Figure 16. Tslew vs. dvdt Capacitance www.onsemi.com 8 600 NIS5420 Series APPLICATION INFORMATION Basic Operation therefore any bond wire resistance and external impedance on the board have no effect on the current limit levels. In this configuration the on resistance is slightly increased relative to the direct sense method since only four of the source pins are used for power. This device is a self−protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The dv/dt of the output voltage will be controlled by the internal dv/dt circuit. The output voltage will slew from 0 V to the rated output voltage in 1.4 ms, unless additional capacitance is added to the dv/dt pin. The device will remain on as long as the temperature does not exceed the 175°C limit that is programmed into the chip. The current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage to 13.5/15 V in the event that the input exceeds that level. An internal charge pump provides bias for the gate voltage of the internal n−channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground. Overvoltage Clamp The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds the overvoltage value, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device. Undervoltage Lockout The undervoltage lockout circuit uses a comparator with hysteresis to monitor the input voltage. If the input voltage drops below the specified level, the output switch will be switched to a high impedance state. Output Slew Rate dv/dt Current Limit The dv/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. An internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. The default ramp time is approximately 2 ms. This can be modified by adding an external capacitor at the dv/dt pin. Since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. Aluminum electrolytic capacitors are not recommended for this circuit. The ramp time from 0 to the nominal output voltage can be determined by the following equation, where t is in seconds: The current limit circuit uses a SENSEFET along with a reference and amplifier to control the peak current in the device. The SENSEFET allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor as well as increasing the value and decreasing the power rating of the sense resistor. Sense resistors are typically in the tens of ohms range with power ratings of several milliwatts making them very inexpensive chip resistors. The current limit circuit has two limiting values, one for short circuit events which are defined as the mode of operation in which the gate is high and the FET is fully enhanced. The overload mode of operation occurs when the device is actively limiting the current and the gate is at an intermediate level. For a more detailed description of this circuit please refer to application note AND9441. There are two methods of biasing the current limit circuit for this device. They are shown in the two application figures. Direct current sensing connects the sense resistor between the current limit pin and the load. This method includes the bond wire resistance in the current limit circuit. This resistance has an impact on the current limit levels for a given resistor and may vary slightly depending on the impedance between the sense resistor and the source pins. The on resistance of the device will be slightly lower in this configuration since all five source pins are connected in parallel and therefore, the effective bond wire resistance is one fifth of the resistance for any given pin. The other method is Kelvin sensing. This method uses one of the source pins as the connection for the current sense resistor. This connection senses the voltage on the die and t 1.2−10.8 + 6E7 @ ǒ20 pF ) C extǓ ) 0.0008 C ext + t 1.2−10.8 * 0.0008 6E7 * 20 pF Where: C is in Farads t is in seconds Any time that the unit shuts down due to a fault, enable shut−down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on. Enable/Fault The Enable/Fault pin is a multi−function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip. When this pin is low, the output of the fuse will be turned off. When this pin is high the output of the fuse will be www.onsemi.com 9 NIS5420 Series both devices will restart as soon as the die temperature of the device in shutdown has been reduced to the lower thermal limit. turned−on. If a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its tri−state operation, it should not be connected to any type of logic with an internal pullup device. If the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. This signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. If this pin is tied to another device in this family, a thermal shutdown of one device will cause both devices to disable their outputs. Both devices will turn on once the fault is removed for the auto−retry devices. For the latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with an external switch and then allowed to go high or after the input power has been recycled. For the auto retry devices, Thermal Protection The NIS542x includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175°C, the device will shut down, and remove power from the load. Output power can be restored by either recycling the input power or toggling the enable pin for thermally latching devices. Power will automatically be reapplied to the load for auto−retry devices once the die temperature has been reduced by 45°C. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. It is not recommended to operate this device above 150°C for extended periods of time. 3.3 V 1.95 V 0.81 V Gnd Figure 17. Fault/Enable Signal Levels www.onsemi.com 10 NIS5420 Series Startup Blanking 12 mA 2.64 V Enable/Fault 1.4 V − + 0.58 V SD Enable SD + − Thermal Reset Thermal Shutdown Thermal SD Figure 18. Enable/Fault Simplified Circuit ORDERING INFORMATION Device Marking Features UVLO VCLAMP ISENSE NIS5420MT1TXG 20T1 Thermal Latching 8.5 15 Yes NIS5420MT2TXG 20T2 Thermal Latching 6.5 13.5 Yes NIS5420MT3TXG 20T3 Thermal Latching 8.5 NA No NIS5420MT4TXG 20T4 Thermal Latching 8.5 15 No NIS5420MT5TXG 20T5 Auto−Retry 8.5 15 No NIS5420MT6TXG 20T6 Auto−Retry 8.5 15 Yes NIS5420MT7TXG 20T7 Auto−Retry 6.5 13.5 Yes NIS5420MT8TXG 20T8 Auto−Retry 6.5 NA Yes Package Shipping† WDFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN10, 3x3, 0.5P CASE 522AA−01 ISSUE A DATE 02 JUL 2007 SCALE 2:1 D PIN ONE REFERENCE 0.15 C 2X 2X ÍÍÍ ÍÍÍ ÍÍÍ 0.15 C E TOP VIEW DIM A A1 A3 b D D2 E E2 e K L A3 0.10 C 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B A A 0.08 C A1 SIDE VIEW C SEATING PLANE L 1 e 5 K 10 6 b 10X 0.10 C A BOTTOM VIEW 2.45 1.75 0.35 GENERIC MARKING DIAGRAM* A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) E2 10X 0.18 MILLIMETERS NOM MAX 0.75 0.80 0.03 0.05 0.20 REF 0.24 0.30 3.00 BSC 2.50 2.55 3.00 BSC 1.80 1.85 0.50 BSC 0.19 TYP 0.40 0.45 XXXXX XXXXX ALYWG G D2 10X MIN 0.70 0.00 0.05 C *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. B NOTE 3 SOLDERING FOOTPRINT* 2.6016 1.8508 3.3048 2.1746 10X 0.5651 10X 0.5000 PITCH 0.3008 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON22331D WDFN10 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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