NLAS4684
Analog Switch, Dual SPDT,
Ultra-Low Resistance
The NLAS4684 is an advanced CMOS analog switch fabricated in
Sub−micron silicon gate CMOS technology. The device is a dual
Independent Single Pole Double Throw (SPDT) switch featuring
Ultra−Low RON of 0.5 , for the Normally Closed (NC) switch, and
0.8 for the Normally Opened switch (NO) at 2.7 V.
The part also features guaranteed Break Before Make switching,
assuring the switches never short the driver.
The NLAS4684 is available in a 2.0 x 1.5 mm bumped die array.
The pitch of the solder bumps is 0.5 mm for easy handling.
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MARKING
DIAGRAMS
Features
• Ultra−Low RON, t0.5 at 2.7 V
• Threshold Adjusted to Function with 1.8 V Control at
•
•
•
•
•
•
•
•
•
•
•
•
A1
Microbump−10
CASE 489AA
VCC = 2.7−3.3 V
Single Supply Operation from 1.8−5.5 V
Tiny 2 x 1.5 mm Bumped Die
Low Crosstalk, t 83 dB at 100 kHz
Full 0−VCC Signal Handling Capability
High Isolation, −65 dB at 100 kHz
Low Standby Current, t50 nA
Low Distortion, t0.14% THD
RON Flatness of 0.15
Pin for Pin Replacement for MAX4684
High Continuous Current Capability
$300 mA Through Each Switch
Large Current Clamping Diodes at Analog Inputs
$300 mA Continuous Current Capability
Pb−Free Packages are Available
1
1
DFN10
CASE 485C
NLAS
4684
ALYWG
G
1
Micro10
CASE 846B
4684
AYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
WW, W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Applications
•
•
•
•
•
A1
4684
AYWWG
G
Cell Phone
Speaker Switching
Power Switching
Modems
Automotive
FUNCTION TABLE
IN 1, 2
NO 1, 2
NC 1, 2
0
1
OFF
ON
ON
OFF
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 20
1
Publication Order Number:
NLAS4684/D
NLAS4684
GND
6
5 NC1
NC2
7
4 IN1
IN2
8
3 COM1
COM2
9
2 NO1
NO2 10
1 VCC
(Top View)
Figure 1. Pin Connections and Logic Diagram
(DFN10 and Micro10)
GND
B1
A1
NC2
C2
A2
IN2
COM1
C3
A3
COM2
NO1
C4
A4
NO2
NC1
C1
IN1
B4
VCC
(Top View)
Figure 2. Pin Connections and Logic Diagram
(Microbump−10)
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2
NLAS4684
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 v VIS v VCC )0.5
V
*0.5 v VI v)7.0
V
VCC
Positive DC Supply Voltage
VIS
Analog Input Voltage (VNO, VNC, or VCOM)
VIN
Digital Select Input Voltage
Ianl1
Continuous DC Current from COM to NC/NO
$300
mA
Ianl−pk 1
Peak Current from COM to NC/NO, 10 duty cycle (Note 1)
$500
mA
Iclmp
Continuous DC Current into COM/NO/NC
$300
mA
Iclmp 1
Peak Current into Input Clamp Diodes at COM/NC/NO
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Defined as 10% ON, 90% off duty cycle.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
1.8
5.5
V
VCC
DC Supply Voltage
VIN
Digital Select Input Voltage
GND
5.5
V
VIS
Analog Input Voltage (NC, NO, COM)
GND
VCC
V
TA
Operating Temperature Range
*55
)125
°C
tr, tf
Input Rise or Fall Time, SELECT
0
0
100
20
ns/V
ESD
Human Body Model − All Pins
5
kV
VCC = 3.3 V $ 0.3 V
VCC = 5.0 V $ 0.5 V
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Condition
VCC $10%
*555C to 255C
t855C
t1255C
Unit
VIH
Minimum High−Level Input
Voltage, Select Inputs
(Figure 9)
2.0
2.5
3.0
5.0
1.4
1.4
1.4
2.0
1.4
1.4
1.4
2.0
1.4
1.4
1.4
2.0
V
VIL
Maximum Low−Level Input
Voltage, Select Inputs
(Figure 9)
2.0
2.5
3.0
5.0
0.5
0.5
0.5
0.8
0.5
0.5
0.5
0.8
0.5
0.5
0.5
0.8
V
IIN
Maximum Input Leakage
Current, Select Inputs
VIN = 5.5 V or GND
5.5
$ 1.0
$ 1.0
$ 1.0
A
IOFF
Power Off Leakage Current
VIN = 5.5 V or GND
0
$10
$10
$10
A
ICC
Maximum Quiescent Supply
Current (Note 2)
Select and VIS = VCC or GND
5.5
$ 180
$ 200
$ 200
nA
2. Guaranteed by design.
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3
NLAS4684
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Maximum Limit
−555C to 255C
Symbol
Parameter
Condition
VCC $10%
Min
Max
t855C
Min
Max
t1255C
Min
Max
Unit
RON (NC)
NC “ON” Resistance
(Note 3)
VIN v VIL
VIS = GND to VCC
IINI v 100 mA
2.5
3.0
5.0
0.6
0.5
0.4
0.7
0.5
0.4
0.8
0.5
0.5
RON (NO)
NO “ON” Resistance
(Note 3)
VIN w VIH
VIS = GND to VCC
IINI v 100 mA
2.5
3.0
5.0
1.0
0.8
0.8
1.0
0.8
0.8
1.0
1.0
0.9
RFLAT (NC)
NC_On−Resistance
Flatness (Notes 3, 5)
ICOM = 100 mA
VIS = 0 to VCC
2.5
3.0
5.0
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.15
RFLAT (NO)
NO_On−Resistance
Flatness (Notes 3, 5)
ICOM = 100 mA
VIS = 0 to VCC
2.5
3.0
5.0
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
RON
On−Resistance Match
Between Channels
(Notes 3 and 4)
VIS = 1.3 V;
ICOM = 100 mA
VIS = 1.5 V;
ICOM = 100 mA
VIS = 2.8 V;
ICOM = 100 mA
2.5
0.18
0.18
0.18
3.0
0.06
0.06
0.06
5.0
0.06
0.06
0.06
INC(OFF)
INO(OFF)
NC or NO Off
Leakage Current
(Figure 13) (Note 3)
VIN = VIL or VIH
VNO or VNC = 1.0
VCOM = 4.5 V
5.5
−1
1
−10
10
−100
100
nA
ICOM(ON)
COM ON
Leakage Current
(Figure 13) (Note 3)
VIN = VIL or VIH
VNO 1.0 V or 4.5 V with
VNC floating or
VNC 1.0 V or 4.5 V with
VNO floating
VCOM = 1.0 V or 4.5 V
5.5
−2
2
−20
20
−200
200
nA
3. Guaranteed by design. Resistance measurements do not include test circuit or package resistance.
4. RON = RON(MAX) − RON(MIN) between NC1 and NC2 or between NO1 and NO2.
5. Flatness is defined as the difference between the maximum and minimum value of on−resistance as measured over the specified analog
signal ranges.
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4
NLAS4684
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) (Typical characteristics are at 25°C)
Guaranteed Maximum Limit
Symbol
Parameter
Test Conditions
VCC
(V)
VIS
(V)
*555C to 255C
Min
Typ
Max
t855C
Min
Max
t1255C
Min
Max
Unit
tON
Turn−On Time
RL = 50 CL = 35 pF
(Figures 4 and 5)
2.5
3.0
5.0
1.3
1.5
2.8
60
50
30
70
60
35
70
60
35
ns
tOFF
Turn−Off Time
RL = 50 CL = 35 pF
(Figures 4 and 5)
2.5
3.0
5.0
1.3
1.5
2.8
50
40
30
55
50
35
55
50
35
ns
tBBM
Minimum Break−Before−Make
Time (Note 6)
VIS = 3.0
RL = 300 CL = 35 pF
(Figure 3)
3.0
1.5
2
ns
15
Typical @ 25, VCC = 5.0 V
CNC Off
CNO Off
CNC On
CNO On
NC Off Capacitance, f = 1 MHz
NO Off Capacitance, f = 1 MHz
NC On Capacitance, f = 1 MHz
NO On Capacitance, f = 1 MHz
102
104
322
330
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
BW
VONL
VISO
Parameter
Condition
Maximum On−Channel −3dB
Bandwidth or Minimum Frequency
Response
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 6)
Maximum Feed−through On Loss
Off−Channel Isolation (Note 7)
VCC
V
Typical
255C
Unit
MHz
NC
3.0
6.5
NO
3.0
9.5
VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND (Figure 6)
3.0
−0.05
f = 100 kHz; VIS = 1 V RMS; CL = 5 nF
VIN centered between VCC and GND(Figure 6)
3.0
−65
dB
dB
Q
Charge Injection Select Input to
Common I/O (Figures 10 and 11)
VIN = VCC to GND, RIS = 0 , CL = 1 nF
Q = CL − VOUT (Figure 7)
3.0
15
pC
THD
Total Harmonic Distortion THD +
Noise (Figure 9)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 , CL = 50 pF
VIS = 1 V RMS
3.0
0.14
%
VCT
Channel−to−Channel Crosstalk
f = 100 kHz; VIS = 1 V RMS, CL = 5 pF, RL = 50
VIN centered between VCC and GND (Figure 6)
3.0
−83
dB
6. −55°C specifications are guaranteed by design.
7. Off−Channel Isolation = 20log10 (Vcom/Vno) (See Figure 6).
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5
NLAS4684
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
50
tBMM
35 pF
90%
90% of VOH
Output
Switch Select Pin
GND
Figure 3. tBBM (Time Break−Before−Make)
VCC
Input
DUT
VCC
0.1 F
50%
Output
VOUT
Open
50%
0V
50
VOH
90%
35 pF
90%
Output
VOL
Input
tON
tOFF
Figure 4. tON/tOFF
VCC
VCC
Input
DUT
Output
50%
0V
50
VOUT
Open
50%
VOH
35 pF
Output
Input
tOFF
Figure 5. tON/tOFF
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6
10%
10%
VOL
tON
NLAS4684
50
DUT
Reference
Transmitted
Input
Output
50 Generator
50
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
ǒVVOUT
Ǔ for VIN at 100 kHz
IN
VOUT
Ǔ for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log ǒ
VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50
Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
On
VIN
Figure 7. Charge Injection: (Q)
10
THD (%)
1
NC1
0.1
NO1
0.01
1
10
100
1000
10000
100000
FREQUENCY (Hz)
Figure 8. Total Harmonic Distortion Plus Noise Versus Frequency
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7
Off
VOUT
NLAS4684
200
CHARGE INJECTION “Q” (pC)
THRESHOLD VOLTAGE (V)
1.6
1.4
Threshold Rising
1.2
1
Threshold Falling
0.8
0.6
0.4
0.2
0
0
2
4
NO, VCC = 5 V
0
NC, VCC = 5 V
−200
−400
−600
−800
0
6
2
VCC (V)
Figure 10. Charge Injection versus Vis
70
100
90
60
80
T−on 2.5 V
50
T−on / T−off (ns)
T−on / T−off (ns)
6
Vin (V)
Figure 9. Voltage in Threshold on Logic Pins
T−off 2.5 V
40
T−on 3.0 V
30
T−off 3.0 V
20
T−on 5.0 V
T−off 5.0 V
70
T−on
60
50
40
T−off
30
20
10
10
0
−55
−30
−5
20
45
70
95
0
1.8
120
TEMPERATURE (°C)
2.8
3.8
4.8
VCC TEMPERATURE (°C)
Figure 11. T−on / T−off Time versus
Temperature
Figure 12. T−on / T−off Time versus Temperature
1000
ICC CURRENT LEAKAGE (nA)
1000
NO/NC CURRENT LEAKAGE (nA)
4
100
Comm / Closed Switch
10
1
0.1
Open Switch
0.01
0.001
−55
−5
45
100
10
1
0.1
0.01
0.001
−55
95
−5
45
95
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. ICC Current Leakage versus
Temperature VCC = 5.5 V
Figure 13. NO/NC Current Leakage Off and On,
VCC = 5 V
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8
NLAS4684
3
1.8 V
2.5
2.5 V
1.5
2.3 V
1
2.7 V
0.5
0.0
1.0
2.5
2.5 V
3.0 V
5.0 V
0.5
2.0
3.0
4.0
0
0.0
5.0
1.0
2.0
4.0
5.0
Figure 16. NO On−Resistance versus
COM Voltage
1.3
0.45
VCC = 2.5 V
ICOM = 100 mA
+85°C
0.4
1.1
+25°C
VCC = 2.5 V
ICOM = 100 mA
+85°C
+25°C
0.9
0.3
RON ()
RON ()
3.0
VCOM (V)
Figure 15. NC On−Resistance versus
COM Voltage
0.25
0.7
−40°C
0.5
0.2
−40°C
0.3
0.15
0.1
0.0
5.0 V
1
VCOM (V)
0.35
2.7 V
2.3 V
2
1.5
3.0 V
TA = +25°C
ICOM = 100 mA
2.0 V
3
2.0 V
RON ()
RON ()
1.8 V
4
3.5
2
0
4.5
TA = +25°C
ICOM = 100 mA
0.5
1.0
1.5
2.0
0.1
2.5
0.0
1.0
2.0
VCOM (V)
3.0
4.0
5.0
VCOM (V)
Figure 17. NC On−Resistance versus
COM Voltage
Figure 18. NO On−Resistance versus
COM Voltage
0.35
0.9
+85°C +25°C
0.8
+85°C
AVERAGE RON ()
AVERAGE RON ()
0.3
+25°C
0.25
−40°C
0.2
0.15
0.1
0.0
VCC = 3 V
ICOM = 100 mA
0.7
0.5
0.4
0.3
0.2
1.0
2.0
0.1
0.0
3.0
−40°C
0.6
VCOM (V)
VCC = 3 V
ICOM = 100 mA
1.0
2.0
VCOM (V)
Figure 19. NC On−Resistance versus
COM Voltage
Figure 20. NC On−Resistance versus
COM Voltage
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9
3.0
0.26
0.9
0.24
0.8
−40°C
0.22
0.2
AVERAGE RON ()
+25°C
0.18
0.16
+85°C
0.14
0.12
VCC = 5 V
ICOM = 100 mA
+25°C
0.7
0.6
−40°C
0.5
0.4
0.3
VCC = 5 V
ICOM = 100 mA
0.2
0.1
0.0
0.1
0.0
+85°C
1.0
2.0
3.0
4.0
5.0
1.0
2.0
VCOM (V)
3.0
4.0
5.0
VCOM (V)
Figure 21. NC On−Resistance versus
COM Voltage
Figure 22. NO On−Resistance versus
COM Voltage
0
Bandwidth (On − Loss)
BANDWIDTH (dB/Div)
−1
PHASE (Degrees)
BANDWIDTH (dB/Div)
0
Bandwidth (On − Loss)
−1
10
0
Phase Shift
(Degrees)
−10
0.001
0.01
10
0
Phase Shift
(Degrees)
−10
VCC = 3.0 V
TA = 25°C
−10
VCC = 3.0 V
TA = 25°C
0.1
1.0
10
100
−10
0.001
0.01
FREQUENCY (MHz)
0.1
0
−10
−10
NC Off−Isolation
0.1
1.0
10
100
Figure 24. NO Bandwidth and Phase Shift
versus Frequency
0
0.01
1.0
FREQUENCY (MHz)
Figure 23. NC Bandwidth and Phase Shift
versus Frequency
−100
0.001
PHASE (Degrees)
AVERAGE RON ()
NLAS4684
NO Off−Isolation
Crosstalk
Crosstalk
VCC = 3.0 V
TA = 25°C
VCC = 3.0 V
TA = 25°C
10
−100
0.001
100
FREQUENCY (MHz)
0.01
0.1
1.0
10
FREQUENCY (MHz)
Figure 25. NC Off Isolation and Crosstalk
Figure 26. NO Off Isolation and Crosstalk
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10
100
NLAS4684
ORDERING INFORMATION
Device
Package
Shipping†
NLAS4684FCT1
Microbump−10
3000 / Tape & Reel
NLAS4684FCT1G
Microbump−10
(Pb−Free)
3000 / Tape & Reel
NLAS4684FCTCG
Microbump−10
(Pb−Free)
3000 / Tape & Reel
DFN10
3000 / Tape & Reel
DFN10
(Pb−Free)
3000 / Tape & Reel
Micro10
4000 / Tape & Reel
Micro10
(Pb−Free)
4000 / Tape & Reel
NLAS4684MNR2
NLAS4684MNR2G
NLAS4684MR2
NLAS4684MR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE F
SCALE 2:1
DATE 16 DEC 2021
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
*This information is generic. Please refer to
Y
= Year
device data sheet for actual part marking.
W
= Work Week
Pb−Free indicator, “G” or microdot “G”, may
G
= Pb−Free Package
or may not be present. Some products may
(Note: Microdot may be in either location) not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03161D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN10, 3X3 MM, 0.5 MM PITCH
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
10 PIN FLIP−CHIP
CASE 489AA−01
ISSUE A
DATE 04 MAY 2004
1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION:
MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
SCALE 4:1
D
4X
A
B
0.10 C
MILLIMETERS
DIM MIN
MAX
A
−−− 0.650
A1 0.210 0.270
A2 0.280 0.380
D
1.965 BSC
E
1.465 BSC
b
0.250 0.350
e
0.500 BSC
D1
1.500 BSC
1.000 BSC
E1
E
PIN ONE
CORNER
A1
0.10 C
A2
GENERIC
MARKING DIAGRAM*
A
0.075 C
C
SEATING
PLANE
xxxx
YYWW
D1
A1
e
10 X
b
0.15 C A B
0.05 C
C
E1
B
xxxx
YY
WW
= Specific Device Code
= Year
= Work Week
A
DOCUMENT NUMBER:
DESCRIPTION:
1
2
3
4
e
98AON12946D
10 PIN FLIP−CHIP
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
Micro10
CASE 846B−03
ISSUE D
DATE 07 DEC 2004
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−A−
−B−
K
D 8 PL
0.08 (0.003)
PIN 1 ID
G
0.038 (0.0015)
−T−
M
T B
S
A
C
SEATING
PLANE
H
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.95
1.10
0.20
0.30
0.50 BSC
0.05
0.15
0.10
0.21
4.75
5.05
0.40
0.70
DIM
A
B
C
D
G
H
J
K
L
S
L
J
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
10X
1.04
0.041
0.32
0.0126
3.20
0.126
8X
xxxx
AYW
10X
4.24
0.167
0.50
0.0196
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.037
0.043
0.008
0.012
0.020 BSC
0.002
0.006
0.004
0.008
0.187
0.199
0.016
0.028
SCALE 8:1
5.28
0.208
xxxx
A
Y
W
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ ”,
may or may not be present.
mm
inches
Micro10
DOCUMENT NUMBER:
98AON03799D
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
Semiconductor Components Industries, LLC, 2002
Case Outline Number:
http://onsemi.com
Micro10
DESCRIPTION:
October, 2002
− Rev. 0
PAGE 1 OFXXX
2
1
DOCUMENT NUMBER:
98AON03799D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION. REQ BY J. HOSKINS.
09 NOV 2000
A
DIM “D” WAS 0.25−0.4MM/0.10−0.016IN. ADDED NOTE 5.
USED ON: WAS 10 LEAD TSSOP, PITCH 0.65 REQ BY J. HOSKINS.
13 NOV 2000
B
CHANGED “USED ON” WAS: 10 LEAD TSSOP, PITCH 0.50MM. REQ BY A. HAMID.
11 JUL 2001
C
CHANGED “D” DIMENSION MAX FROM 0.35 TO 0.30MM AND 0.014 TO 0.012IN.
REQ BY D. TRUHITTE.
31 JUL 2003
D
ADDED FOOTPRINT INFORMATION. REQ. BY K. OPPEN.
07 DEC 2004
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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 03D
Case Outline Number:
846B
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