NLSX4378
4-Bit 24 Mb/s Dual-Supply
Level Translator
The NLSX4378 is a 4−bit configurable dual−supply bidirectional
auto sensing translator that does not require a directional control pin.
The VCC I/O and VL I/O ports are designed to track two different
power supply rails, VCC and VL respectively. The VCC supply rail is
configurable from 1.65 V to 5.5 V while VL supply rail is
configurable to 1.65 V to 5.5 V. This allows voltage logic signals on
the VL side to be translated into lower, higher or equal value voltage
logic signals on the VCC side, and vice−versa.
The NLSX4378 translator has open−drain outputs with integrated
10 kW pullup resistors on the I/O lines. The integrated pullup
resistors are used to pullup the I/O lines to either VL or VCC. The
NLSX4378 is an excellent match for open−drain applications such as
the I2C communication bus.
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MARKING
DIAGRAM
mBump12
FC SUFFIX
CASE 499AU
x
= F − Standard
B − Backcoated
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
Features
• VL can be Less than, Greater than or Equal to VCC
• Wide VCC Operating Range: 1.65 V to 5.5 V
•
•
•
•
•
•
•
Wide VL Operating Range: 1.65 V to 5.5 V
High−Speed with 24 Mb/s Guaranteed Date Rate
Low Bit−to−Bit Skew
Enable Input and I/O Lines have Overvoltage Tolerant (OVT) to
5.5 V
Nonpreferential Powerup Sequencing
Integrated 10 kW Pullup Resistors
Small Space Saving Package − 2.02 x 1.54 mm mBump12
This is a Pb−Free Device
Typical Applications
• I2C, SMBus, PMBus
• Low Voltage ASIC Level Translation
• Mobile Phones, PDAs, Cameras
S4378x
AYWW
G
LOGIC DIAGRAM
EN
VL
VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. 4
1
Publication Order Number:
NLSX4378/D
NLSX4378
VL
VCC
One−Shot
Block
PU1
One−Shot
Block
Gate
Bias
RPullup
10 kW
PU2
RPullup
10 kW
EN
EN
I/O VL
I/O VCC
N
Figure 1. Block Diagram (1 I/O Line)
PIN ASSIGNMENT
PIN LOCATION
Pins
Description
Pin
Pin Name
VCC
VCC Input Voltage
A1
I/O VL1
VL
VL Input Voltage
A2
I/O VL2
GND
Ground
A3
I/O VL3
EN
Output Enable
A4
I/O VL4
I/O VCCn
VCC I/O Port, Referenced to VCC
B1
VCC
I/O VLn
VL I/O Port, Referenced to VL
B2
VL
B3
EN
FUNCTION TABLE
EN
Operating Mode
B4
GND
L
Hi−Z
C1
I/O VCC1
H
I/O Buses Connected
C2
I/O VCC2
C3
I/O VCC3
C4
I/O VCC4
mBump12
(2.02 x 1.54 mm)
A
B
C
I/O VL1
VCC
I/O VCC1
I/O VL2
VL
I/O VCC2
I/O VL3
EN
I/O VCC3
I/O VL4
GND
I/O VCC4
1
2
3
4
(Bottom View)
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2
NLSX4378
MAXIMUM RATINGS
Symbol
Parameter
Condition
Value
Unit
VCC
DC Supply Voltage
−0.3 to +7.0
V
VL
DC Supply Voltage
−0.3 to +7.0
V
I/O VCC
VCC−Referenced DC Input/Output Voltage
−0.3 to (VCC + 0.3)
V
I/O VL
VL−Referenced DC Input/Output Voltage
−0.3 to (VL + 0.3)
V
VEN
Enable Control Pin DC Input Voltage
−0.3 to +7.0
V
II/O_SC
Short−Circuit Duration (I/O VL and I/O VCC to GND)
40
mA
TSTG
Storage Temperature
−65 to +150
°C
Continuous
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
1.65
5.5
V
VL
DC Supply Voltage
1.65
5.5
V
VEN
Enable Control Pin Voltage
GND
5.5
V
VIO
Enable Control Pin Voltage
GND
5.5
V
TA
Operating Temperature Range
−40
+85
°C
DC ELECTRICAL CHARACTERISTICS (VCC = 1.65 V to 5.5 V and VL = 1.65 V to 5.5 V, unless otherwise specified)
−405C to +855C
Symbol
Parameter
Test Conditions
Min
Typ
(Notes 1, 2)
Max
Unit
VIHC
I/O VCC Input HIGH Voltage
VCC − 0.4
−
−
V
VILC
I/O VCC Input LOW Voltage
−
−
0.15
V
VIHL
I/O VL Input HIGH Voltage
VL − 0.4
−
−
V
VILL
I/O VL Input LOW Voltage
−
−
0.15
V
VIH
Control Pin Input HIGH Voltage
0.65 * VL
−
−
V
VIL
Control Pin Input LOW Voltage
−
−
0.35 * VL
V
VOHC
I/O VCC Output HIGH Voltage
I/O VCC Source Current = 20 mA
0.8 * VCC
−
−
V
VOLC
I/O VCC Output LOW Voltage
I/O VCC Sink Current = 1.0 mA
I/O_VL ≤ 0.15 V
−
−
0.4
V
VOHL
I/O VL Output HIGH Voltage
I/O VL Source Current = 20 mA
0.8 * VL
−
−
V
VOLL
I/O VL Output LOW Voltage
I/O VL Sink Current = 1.0 mA
I/O_VCC ≤ 0.15 V
−
−
0.4
V
IQVCC
VCC Supply Current
I/O VCC and I/O VL Unconnected,
VEN = VL
−
0.5
2.0
mA
VL Supply Current
I/O VCC and I/O VL Unconnected,
VEN = VL
−
0.3
1.0
mA
VCC Tristate Output Mode Supply Current
I/O VCC and I/O VL Unconnected,
VEN = GND
−
0.1
1.0
mA
VL Tristate Output Mode Supply Current
I/O VCC and I/O VL Unconnected,
VEN = GND
−
0.1
1.0
mA
IQVL
ITS−VCC
ITS−VL
IOZ
I/O Tristate Output Mode Leakage Current
TA = +25°C
−
0.1
1.0
mA
RPU
Pullup Resistor I/O VL and VCC
TA = +25°C
−
10
−
kW
1. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C.
2. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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3
NLSX4378
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Note 3)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 1.65 V, VCC = 5.5 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
20
ns
tRVL
I/O VL Risetime
30
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
20
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
20
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
Mb/s
VL = 1.8 V, VCC = 2.8 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
15
ns
tRVL
I/O VL Risetime
25
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
Mb/s
VL = 2.5 V, VCC = 3.6 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
10
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
Mb/s
VL = 2.8 V, VCC = 1.8 V
tRVCC
I/O VCC Risetime
25
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
20
ns
tFVL
I/O VL Falltime
15
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
3. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
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4
Mb/s
NLSX4378
TIMING CHARACTERISTICS − RAIL−TO−RAIL DRIVING CONFIGURATIONS
(I/O test circuit of Figures 2 and 3, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Note 3)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VL = 3.6 V, VCC = 2.5 V
tRVCC
I/O VCC Risetime
15
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
15
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
15
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
15
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
Mb/s
VL = 5.5 V, VCC = 1.65 V
tRVCC
I/O VCC Risetime
30
ns
tFVCC
I/O VCC Falltime
10
ns
tRVL
I/O VL Risetime
15
ns
tFVL
I/O VL Falltime
20
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
20
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
20
ns
Part−to−Part Skew
5
nS
tPPSKEW
MDR
Maximum Data Rate
24
Mb/s
3. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
TIMING CHARACTERISTICS − OPEN DRAIN DRIVING CONFIGURATIONS
(I/O test circuit of Figures 4 and 5, CLOAD = 15 pF, driver output impedance v 50 W, RLOAD = 1 MW)
−405C to +855C
(Note 4)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
+1.65 v VL, VCC v +5.5 V
tRVCC
I/O VCC Risetime
400
ns
tFVCC
I/O VCC Falltime
50
ns
tRVL
I/O VL Risetime
400
ns
tFVL
I/O VL Falltime
60
ns
tPDVL−VCC
Propagation Delay (Driving I/O VL)
1000
ns
tPDVCC−VL
Propagation Delay (Driving I/O VCC)
1000
ns
50
nS
tPPSKEW
MDR
Part−to−Part Skew
Maximum Data Rate
2
Mb/s
4. All units are production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. Limits over the operating
temperature range are guaranteed by design.
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5
NLSX4378
TEST SETUPS
NLSX4378
VL
VCC
NLSX4378
VL
EN
Source
I/O VL
I/O VCC
I/O VL
I/O VCC
CLOAD
CLOAD
RLOAD
NLSX4378
Figure 3. Rail−to−Rail Driving I/O VCC
I/O VCC
I/O VL
CLOAD
I/O VCC
VCC
CLOAD
RLOAD
Figure 4. Open−Drain Driving I/O VL
Figure 5. Open−Drain Driving I/O VCC
tRISE/FALL v
3 ns
tPD_VL−VCC
I/O VCC
VCC
EN
RLOAD
I/O VL
NLSX4378
VL
VCC
EN
90%
50%
10%
Source
RLOAD
Figure 2. Rail−to−Rail Driving I/O VL
VL
VCC
EN
I/O VCC
tRISE/FALL v 3 ns
90%
50%
10%
tPD_VCC−VL
I/O VL
tPD_VL−VCC
90%
50%
10%
tPD_VCC−VL
90%
50%
10%
tF−VCC
tR−VCC
tF−VL
Figure 6. Definition of Timing Specification Parameters
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6
tR−VL
NLSX4378
VCC
PULSE
GENERATOR
2xVCC
OPEN
R1
DUT
RT
CL
Test
RL
Switch
tPZH, tPHZ
Open
tPZL, tPLZ
2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 50 kW or equivalent
RT = ZOUT of pulse generator (typically 50 W)
Figure 7. Test Circuit for Enable/Disable Time Measurement
tR
tF
Input
tPLH
Output
90%
50%
10%
tR
EN
VCC
90%
50%
10%
tPHL
GND
VL
50%
tPZL
Output
50%
tPZH
tF
Output
50%
GND
tPLZ
tPHZ
HIGH
IMPEDANCE
10%
VOL
90%
VOH
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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7
HIGH
IMPEDANCE
NLSX4378
APPLICATIONS INFORMATION
Level Translator Architecture
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 W.
The NLSX4378 auto sense translator provides
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two
supply voltages, VL and VCC, which set the logic levels on
the input and output sides of the translator. When used to
transfer data from the VL to the VCC ports, input signals
referenced to the VL supply are translated to output signals
with a logic level matched to VCC. In a similar manner, the
VCC to VL translation shifts input signals with a logic level
compatible to VCC to an output signal matched to VL.
The NLSX4378 consists of two bi−directional channels
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits
are used to detect the rising input signals. In addition, the
one shots decrease the rise time of the output signal for
low−to−high transitions.
Each input/output channel has an internal 10 kW pull.
The magnitude of the pullup resistors can be reduced by
connecting external resistors in parallel to the internal
10 kW resistors.
Enable Input (EN)
The NLSX4378 has an Enable pin (EN) that provides
tri−state operation at the I/O pins. Driving the Enable pin
to a low logic level minimizes the power consumption of
the device and drives the I/O VCC and I/O VL pins to a high
impedance state. Normal translation operation occurs
when the EN pin is equal to a logic high signal. The EN pin
is referenced to the VL supply and has Overvoltage
Tolerant (OVT) protection.
Power Supply Guidelines
During normal operation, supply voltage VL can be
greater than, less than or equal to VCC. The sequencing of
the power supplies will not damage the device during the
power up operation.
For optimal performance, 0.01 mF to 0.1 mF decoupling
capacitors should be used on the VL and VCC power supply
pins. Ceramic capacitors are a good design choice to filter
and bypass any noise signals on the voltage lines to the
ground plane of the PCB. The noise immunity will be
maximized by placing the capacitors as close as possible to
the supply and ground pins, along with minimizing the
PCB connection traces.
Input Driver Requirements
The rise (tR) and fall (tF) timing parameters of the open
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (tPD), skew
(tPSKEW) and maximum data rate depend on the impedance
of the device that is connected to the translator. The timing
ORDERING INFORMATION
Device
NLSX4378FCT1G
NLSX4378BFCT1G
Package
Shipping†
mBump12
(Pb−Free)
3000 / Tape & Reel
mBump12
(Backside Laminate Coating)
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NLSX4378
PACKAGE DIMENSIONS
mBump12, 2.02x1.54, 0.5P
CASE 499AU
ISSUE O
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
PIN A1
REFERENCE
E
2X
0.10 C
2X
0.10 C
TOP VIEW
A
0.10 C
A2
0.05 C
12X
A1
C
SIDE VIEW
NOTE 3
DIM
A
A1
A2
b
D
D1
E
E1
e
MILLIMETERS
MIN
MAX
0.66
−−−
0.21
0.27
0.33
0.39
0.29
0.34
2.02 BSC
1.50 BSC
1.54 BSC
1.00 BSC
0.50 BSC
SEATING
PLANE
D1
e/2
12X
e
b
0.05 C A B
C
0.03 C
B
E1
A
1
2
3
4
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf . SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall
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fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws
and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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