NTB60N06L

NTP60N06L, NTB60N06L Power MOSFET 60 Amps, 60 Volts, Logic Level N−Channel TO−220 and D2PAK http://onsemi.com Designed for low voltage, high speed switching applications in power supplies, converters, power motor controls and bridge circuits. Features 60 AMPERES, 60 VOLTS RDS(on) = 16 mW N−Channel D • Pb−Free Packages are Available Typical Applications • • • • Power Supplies Converters Power Motor Controls Bridge Circuits G S 4 Value 60 60 "15 "20 60 42.3 180 150 1.0 2.4 −55 to 175 454 Adc Apk W W/°C W °C mJ NTx 60N06LG AYWW Unit Vdc Vdc Vdc VGS VGS ID ID IDM PD 1 TO−220AB CASE 221A STYLE 5 3 1 2 3 D2PAK CASE 418B STYLE 2 4 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Drain−to−Gate Voltage (RGS = 10 MW) Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA 100°C − Single Pulse (tpv10 ms) Symbol VDSS VDGR 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 75 Vdc, VGS = 5.0 Vdc, L = 0.3 mH, IL(pk) = 55 A,VDS = 60 Vdc) Thermal Resistance, − Junction−to−Case − Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TJ, Tstg EAS NTx60N06LG AYWW 1 Gate 2 Drain NTx60N06L x A Y WW G 3 Source 1 Gate °C/W RqJC RqJA TL 1.0 62.5 260 °C 2 Drain 3 Source Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). = Device Code = B or P = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2005 1 August, 2005 − Rev. 3 Publication Order Number: NTP60N06L/D NTP60N06L, NTB60N06L ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ =150°C) Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 2) (VGS = 5.0 Vdc, ID = 30 Adc) Static Drain−to−Source On−Voltage (Note 2) (VGS = 5.0 Vdc, ID = 60 Adc) (VGS = 5.0 Vdc, ID = 30 Adc, TJ = 150°C) Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 60 Adc, VGS = 5.0 Vdc) (Note 2) SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage Reverse Recovery Time (IS = 60 Adc, VGS = 0 Vdc, dlS/dt = 100 A/ms) (Note 2) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. (IS = 60 Adc, VGS = 0 Vdc) (Note 2) (IS = 60 Adc, VGS = 0 Vdc, TJ = 150°C) VSD trr ta tb QRR − − − − − − 0.98 0.86 81.9 42.1 39.8 0.172 1.05 − − − − − mC Vdc ns (VDD = 48 Vdc, ID = 60 Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 2) td(on) tr td(off) tf QT Q1 Q2 − − − − − − − 50.4 576 100 237 43.2 6.4 29 100 1160 200 480 65 − − nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss − − − 2195 675 188 3075 945 380 pF VGS(th) 1.0 − RDS(on) − VDS(on) − − gFS − 0.793 0.861 48 1.17 − − mhos 12.4 16 Vdc 1.58 5.4 2.0 − Vdc mV/°C mW V(BR)DSS 60 − IDSS − − IGSS − − − − 1.0 10 ± 100 nAdc 72.8 75.2 − − Vdc mV/°C mAdc Symbol Min Typ Max Unit ORDERING INFORMATION Device NTP60N06L NTP60N06LG NTB60N06L NTB60N06LG NTB60N06LT4 NTB60N06LT4G Package TO−220AB TO−220AB (Pb−Free) D2PAK D2PAK (Pb−Free) D2PAK D2PAK (Pb−Free) 800 Units / Tape & Reel 800 Units / Tape & Reel Shipping † 50 Units / Rail 50 Units / Rail 50 Units / Rail 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTP60N06L, NTB60N06L 120 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 8V 100 80 60 40 20 0 3.5 V 6V 5V VGS = 10 V 4V 4.5 V 100 80 60 40 TJ = 25°C 20 0 TJ = 100°C 1 TJ = −55°C 6 120 VDS ≥ 10 V 3V 0 1 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 5 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.03 VGS = 5 V 0.026 0.022 0.018 TJ = 25°C 0.014 0.01 0.006 TJ = −55°C TJ = 100°C 0.03 VDS = 5 0 V GS 1 V 0.026 0.022 0.018 0.014 TJ = 25°C 0.01 TJ = −55°C 0 20 40 60 80 100 ID, DRAIN CURRENT (AMPS) 120 TJ = 100°C 0 20 60 40 80 100 ID, DRAIN CURRENT (AMPS) 120 0.006 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 1.8 1.6 1.4 1.2 1 0.8 0.6 −50 ID = 30 A VGS = 5 V 10,000 VGS = 0 V TJ = 150°C IDSS, LEAKAGE (nA) 1000 TJ = 125°C 100 TJ = 100°C 10 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTP60N06L, NTB60N06L POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 8000 VDS = 0 V 6000 VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) Ciss 4000 Crss Ciss 2000 Coss Crss 0 10 5 VGS 0 5 VDS 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 NTP60N06L, NTB60N06L VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 6 5 4 3 2 1 0 0 Q1 QT VGS t, TIME (ns) 1000 tr Q2 tf 100 td(off) td(on) ID = 60 A TJ = 25°C 10 20 30 40 QG, TOTAL GATE CHARGE (nC) 50 10 1 VDS = 30 V ID = 60 A VGS = 5 V 10 RG, GATE RESISTANCE (W) 100 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 60 IS, SOURCE CURRENT (AMPS) 50 40 30 TJ = 150°C 20 TJ = 25°C 10 0 0.3 VGS = 0 V TJ = 25°C 0.38 0.46 0.54 0.62 0.7 0.78 0.86 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown http://onsemi.com 5 NTP60N06L, NTB60N06L in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. SAFE OPERATING AREA ID, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 1000 10 ms 500 ID = 55 A 400 100 300 100 ms 10 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 10 ms dc 200 100 0 25 1 1 100 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 175 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 t1 t2 DUTY CYCLE, D = t1/t2 0.01 t, TIME (ms) 0.1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0 10 Figure 13. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 NTP60N06L, NTB60N06L PACKAGE DIMENSIONS D2PAK CASE 418B−04 ISSUE J C E −B− 4 V W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. DIM A B C D E F G H J K L M N P R S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 A 1 2 3 S −T− SEATING PLANE K G D 3 PL 0.13 (0.005) H M W J TB M VARIABLE CONFIGURATION ZONE L M R N U L P L M STYLE 2: PIN 1. 2. 3. 4. M F VIEW W−W 1 F VIEW W−W 2 F VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 10.66 0.42 1.016 0.04 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTP60N06L, NTB60N06L PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA −T− B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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