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NTD4809NHT4G

NTD4809NHT4G

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOT428

  • 描述:

    MOSFET N-CH 30V 9A DPAK

  • 数据手册
  • 价格&库存
NTD4809NHT4G 数据手册
NTD4809NH Power MOSFET 30 V, 58 A, Single N−Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS 30 V RDS(on) MAX 9.0 mW @ 10 V 12.5 mW @ 4.5 V D ID MAX 58 A Applications • CPU Power Delivery • DC−DC Converters • Low Side Switching MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (RqJA) (Note 1) Power Dissipation (RqJA) (Note 1) Continuous Drain Current (RqJA) (Note 2) Power Dissipation (RqJA) (Note 2) Continuous Drain Current (RqJC) (Note 1) Power Dissipation (RqJC) (Note 1) Pulsed Drain Current tp=10ms Current Limited by Package TA = 25°C TA = 85°C TA = 25°C TA = 25°C Steady State TA = 85°C TA = 25°C TC = 25°C TC = 85°C TC = 25°C TA = 25°C TA = 25°C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 30 "20 11.5 9.0 2.0 9.0 7.0 1.3 58 45 52 130 45 −55 to 175 43 6.0 112.5 W A A °C A V/ns mJ W A W A Unit V V A N−Channel G S 4 4 12 3 DPAK CASE 369C (Bent Lead) STYLE 2 2 3 3 IPAK IPAK CASE 369AD CASE 369D (Straight Lead) (Straight Lead DPAK) 1 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain YWW 48 09NHG 4 Drain YWW 48 09NHG 4 Drain YWW 48 09NHG Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 15 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C 2 1 23 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y = Year WW = Work Week 4809NH= Device Code G = Pb−Free Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2007 1 March, 2007 − Rev. 3 Publication Order Number: NTD4809NH/D NTD4809NH THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Case (Drain) Junction−to−TAB (Drain) Junction−to−Ambient − Steady State (Note 1) Junction−to−Ambient − Steady State (Note 2) 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJC−TAB RqJA RqJA Value 2.9 3.5 74 116 Unit °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, VDS = 24 V TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 30 25 1.0 10 "100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS(TH)/TJ RDS(on) VGS = VDS, ID = 250 mA 1.5 5.7 2.5 V mV/°C VGS = 10 to 11.5 V VGS = 4.5 V ID = 30 A ID = 15 A ID = 30 A ID = 15 A 7.0 7.0 10.45 9.95 9.0 9.0 mW 12.5 Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time gFS VDS = 15 V, ID = 15 A S Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 11.5 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A VGS = 0 V, f = 1.0 MHz, VDS = 12 V 1596 331 190 12.5 2.4 5.3 5.1 29.3 15 pF nC nC td(on) tr td(off) tf td(on) tr td(off) tf VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 12.0 20 14 5.0 7.0 18 22 3.0 ns ns 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD4809NH ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 30 A TJ = 25°C TJ = 125°C 0.95 0.83 15.6 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A 10.6 5.0 7.5 nC ns 1.2 V Symbol Test Condition Min Typ Max Unit Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance Drain Inductance, DPAK Drain Inductance, IPAK Gate Inductance Gate Resistance tRR ta tb QRR LS LD LD LG RG TA = 25°C 2.49 0.0164 1.88 3.46 0.75 nH W http://onsemi.com 3 NTD4809NH TYPICAL PERFORMANCE CURVES 100 ID, DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4V 3.8 V 3.6 V 3.4 V 3.2 V 3V 80 VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 1 2 3 TJ = 125°C TJ = 25°C TJ = −55°C 4 5 5.5 V to 10 V 4.5 V TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.015 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 ID = 30 A TJ = 25°C 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.002 0 10 15 20 25 30 35 40 45 50 55 60 VGS = 11.5 V VGS = 4.5 V TJ = 25°C VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 −50 −25 10000 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V 1000 TJ = 150°C TJ = 125°C 100 10 1 TJ = 25°C 0.1 0 25 50 75 100 125 150 175 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 NTD4809NH TYPICAL PERFORMANCE CURVES 2000 Ciss 1500 12 10 VGS 8 6 4 2 0 0 5 10 15 20 25 Qg, TOTAL GATE CHARGE (nC) 30 Qgs Qgd VDD = 15 V 0 V ≤ VGS ≤ 11.5 V ID = 30 A TJ = 25°C VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C QT C, CAPACITANCE (pF) 1000 500 Coss Crss 0 5 10 15 20 25 30 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 30 IS, SOURCE CURRENT (AMPS) VGS = 0 V 25 20 15 10 5 0 0.5 TJ = 25°C 100 t, TIME (ns) tr td(off) 10 td(on) tf VDD = 15 V ID = 30 A VGS = 11.5 V 100 1 1 10 RG, GATE RESISTANCE (OHMS) 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 9. Resistive Switching Time Variation vs. Gate Resistance EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25°C 100 10 ms 120 Figure 10. Diode Forward Voltage vs. Current ID = 15 A 100 80 60 40 20 0 25 100 ms 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 1 ms 10 ms dc 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 175 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTD4809NH TYPICAL PERFORMANCE CURVES 100 I D, DRAIN CURRENT (AMPS) 25°C 100°C 10 125°C 1 1 10 100 PULSE WIDTH (ms) 1000 Figure 13. Avalanche Characteristics r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.0E−05 t1 t2 DUTY CYCLE, D = t1/t2 1.0E−03 1.0E−02 t, TIME (ms) P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E−04 1.0E−01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Device NTD4809NHT4G NTD4809NH−1G NTD4809NH−35G Package DPAK (Pb−Free) IPAK (Pb−Free) IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) Shipping † 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4809NH PACKAGE DIMENSIONS IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B B V R 4 C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− Z A 3 S −T− SEATING PLANE 1 2 K F D G 3 PL J H 0.13 (0.005) M DIM A B C D E F G H J K R S V Z T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN E L2 E3 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O A A1 E2 D2 L1 D NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 T SEATING PLANE L b1 2X A1 A2 3X e b 0.13 M E2 T D2 OPTIONAL CONSTRUCTION http://onsemi.com 7 NTD4809NH PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C−01 ISSUE O −T− B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− C E A S 1 2 3 Z U K F L D 2 PL G 0.13 (0.005) M J H T DIM A B C D E F G H J K L R S U V Z SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 8 NTD4809NH/D
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