NTD4857N-35G

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Other names and brands may be claimed as the property of others. NTD4857N Power MOSFET 25 V, 78 A, Single N--Channel, DPAK/IPAK Features Trench Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb--Free Devices http://onsemi.com V(BR)DSS RDS(ON) MAX 5.7 mΩ @ 10 V 25 V Applications D MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Symbol G Value Unit Drain--to--Source Voltage VDSS 25 V Gate--to--Source Voltage VGS ±20 V ID 15 A Continuous Drain Current RθJA (Note 1) TA = 25°C Power Dissipation RθJA (Note 1) TA = 25°C PD 2.1 W Continuous Drain Current RθJA (Note 2) TA = 25°C ID 12 A TA = 85°C TA = 85°C 9.3 PD 1.31 W Continuous Drain Current RθJC (Note 1) TC = 25°C ID 78 A Power Dissipation RθJC (Note 1) TC = 25°C PD 56.6 W TA = 25°C IDM 156 A tp=10ms Current Limited by Package TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) 1 2 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AC CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK) 61 IDmaxPkg 45 A TJ, TSTG --55 to +175 °C IS 47 A Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain--to--Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, IL = 17 Apk, L = 1.0 mH, RG = 25 Ω) EAS 144.5 mJ TL 260 °C Lead Temperature for Soldering Purposes (1/8” from case for 10 s) 4 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW 48 57NG TC = 85°C 4 4 11.7 TA = 25°C Pulsed Drain Current S N--CHANNEL MOSFET YWW 48 57NG Parameter Power Dissipation RθJA (Note 2) 78 A 8.0 mΩ @ 4.5 V • VCORE Applications • DC--DC Converters • Low Side Switching Steady State ID MAX 4 Drain YWW 48 57NG • • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4857N G = Year = Work Week = Device Code = Pb--Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2010 June, 2010 -- Rev. 1 1 Publication Order Number: NTD4857N/D NTD4857N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction--to--Case (Drain) Parameter RθJC 2.65 °C/W Junction--to--TAB (Drain) RθJC--TAB 3.5 Junction--to--Ambient – Steady State (Note 1) RθJA 72 Junction--to--Ambient – Steady State (Note 2) RθJA 114.5 1. Surface--mounted on FR4 board using 1 sq--in pad, 1 oz Cu. 2. Surface--mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Symbol Test Condition Min Drain--to--Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain--to--Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate--to--Source Leakage Current IDSS V 20 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain--to--Source On Resistance RDS(on) Forward Transconductance gFS 1.45 5.3 mV/°C VGS = 10 V ID = 30 A 4.6 5.7 VGS = 4.5 V ID = 30 A 6.3 8.0 VDS = 1.5 V, ID = 15 A 77 mΩ S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 265 Total Gate Charge QG(TOT) 16 Threshold Gate Charge QG(TH) Gate--to--Source Charge QGS Gate--to--Drain Charge Total Gate Charge 1960 VGS = 0 V, f = 1.0 MHz, VDS = 12 V VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 495 1.5 5.7 pF 24 nC 6.6 VGS = 10 V, VDS = 15 V, ID = 30 A 32 nC SWITCHING CHARACTERISTICS (Note 4) Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time td(ON) tr td(OFF) 13.9 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω 20.6 18.6 tf 6.8 td(ON) 8.7 tr td(OFF) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω tf 18.7 26 3.6 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns ns NTD4857N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max TJ = 25°C 0.88 1.2 TJ = 125°C 0.74 Unit DRAIN--SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = 30 A tRR ta tb V 11.7 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 7.2 ns 4.5 QRR 3.2 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD PACKAGE PARASITIC VALUES TA = 25°C 1.88 Gate Inductance LG 3.46 Gate Resistance RG 0.6 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 Ω NTD4857N TYPICAL PERFORMANCE CURVES 3.6 V 70 60 3.4 V 50 40 3.2 V 30 20 3.0 V 10 2.8 V 0 0.5 1 2 1.5 3 2.5 3.5 4 50 40 30 TJ = 125°C 20 TJ = 25°C 10 TJ = --55°C 1 2 3 4 5 Figure 2. Transfer Characteristics 0.030 0.025 0.020 0.015 0.010 0.005 3 4 5 6 7 8 9 11 10 0.008 TJ = 25°C 0.007 VGS = 4.5 V 0.006 0.005 VGS = 11.5 V 0.004 0.003 0.002 20 30 40 50 60 70 80 90 100 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On--Resistance vs. Gate--to--Source Voltage Figure 4. On--Resistance vs. Drain Current and Gate Voltage 1.8 10000 VGS = 0 V ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN--TO--SOURCE RESISTANCE (NORMALIZED) 60 Figure 1. On--Region Characteristics 0.035 1.6 70 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) ID = 30 A TJ = 25°C 2 80 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) 0.040 0 VDS ≥ 10 V 90 0 5 4.5 RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) ID, DRAIN CURRENT (AMPS) 3.8 V TJ = 25°C 80 0 RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) 100 4V 10 V 90 ID, DRAIN CURRENT (AMPS) 100 1.4 1.2 1.0 TJ = 150°C 1000 TJ = 125°C 100 10 TJ = 25°C 0.8 0.6 --50 --25 0 25 50 75 100 125 150 175 1 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) Figure 5. On--Resistance Variation with Temperature Figure 6. Drain--to--Source Leakage Current vs. Drain Voltage http://onsemi.com 4 25 NTD4857N 3000 2800 2600 2400 2200 Ciss 2000 1800 1600 1400 1200 1000 Coss 800 600 400 200 Crss 0 0 5 VGS , GATE--TO--SOURCE VOLTAGE (VOLTS) C, CAPACITANCE (pF) TYPICAL PERFORMANCE CURVES VGS = 0 V TJ = 25°C 10 15 20 25 DRAIN--TO--SOURCE VOLTAGE (VOLTS) 12 8 Q1 4 IS, SOURCE CURRENT (AMPS) td(off) tf 100 tr td(on) 10 0 0 10 RG, GATE RESISTANCE (OHMS) 8 12 16 20 24 28 32 36 VGS = 0 V 25 20 15 10 5 100 ms 1 ms VGS = 20 V SINGLE PULSE TC = 25°C 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.8 Figure 10. Diode Forward Voltage vs. Current 10 ms 10 0.7 0.6 VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS) 10 100 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN--TO--SOURCE AVALANCHE ENERGY (mJ) 100 TJ = 25°C 0 0.5 100 1000 I D, DRAIN CURRENT (AMPS) 4 QG, TOTAL GATE CHARGE (nC) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 0.1 0.1 ID = 30 A VDD = 15 V TJ = 25°C 2 30 VDD = 15 V ID = 30 A VGS = 11.5 V 1 Q2 Figure 8. Gate--To--Source and Drain--To--Source Voltage vs. Total Charge 1000 t, TIME (ns) VGS 6 Figure 7. Capacitance Variation 1 1 QT 10 160 ID = 15 A 140 120 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4857N ORDERING INFORMATION Package Shipping† NTD4857NT4G DPAK (Pb--Free) 2500 / Tape & Reel NTD4857N--1G IPAK (Pb--Free) 75 Units / Rail NTD4857N--35G IPAK Trimmed Lead (3.5  0.15 mm) (Pb--Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4857N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA--01 ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M C H L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 90° CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 ------ 0.040 0.155 ------ 6.17 0.243 SCALE 3:1 mm  inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 -----1.01 3.93 ------ NTD4857N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC--01 ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK (STRAIGHT LEAD DPAK) CASE 369D--01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 --T-SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 ------ MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ------ STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800--282--9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81--3--5773--3850 http://onsemi.com 8 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD4857N/D