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NTD4979NT4G

NTD4979NT4G

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOT428

  • 描述:

    MOSFET N-CH 30V 9.4A DPAK-3

  • 数据手册
  • 价格&库存
NTD4979NT4G 数据手册
NTD4979N Power MOSFET 30 V, 41 A, Single N−Channel, DPAK/IPAK Features • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Three Package Variations for Design Flexibility These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications http://onsemi.com V(BR)DSS RDS(ON) MAX ID MAX 9.0 mW @ 10 V 30 V 41 A 19 mW @ 4.5 V • CPU Power Delivery • DC−DC Converters D MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Continuous Drain Current RqJA (Note 1) TA = 25°C Unit VDSS 30 V VGS ±20 V ID 12.7 A TA = 100°C TA = 25°C PD 2.56 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 9.4 A Power Dissipation RqJA (Note 2) Continuous Drain Current RqJC (Note 1) TA = 100°C 6.6 PD 1.38 W TC = 25°C ID 41 A 29 TC = 25°C PD 26.3 W TA = 25°C IDM 150 A TA = 25°C IDmaxPkg 40 A TJ, TSTG −55 to +175 °C IS 24 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V, IL = 19 Apk, L = 0.1 mH, RG = 25 W) EAS 18 mJ TL 260 °C Pulsed Drain Current tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8” from case for 10 s) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. 4 4 4 1 2 TA = 25°C TC = 100°C Power Dissipation RqJC (Note 1) S N−CHANNEL MOSFET 9.0 Power Dissipation RqJA (Note 1) Steady State G 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AC CASE 369D 3 IPAK IPAK (Straight Lead) (Straight Lead DPAK) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 49 79NG Gate−to−Source Voltage Value YWW 49 79NG Drain−to−Source Voltage Symbol YWW 49 79NG Parameter 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4979N G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 0 1 Publication Order Number: NTD4979N/D NTD4979N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 5.7 °C/W Junction−to−TAB (Drain) RqJC−TAB 4.3 Junction−to−Ambient – Steady State (Note 3) RqJA 58.6 Junction−to−Ambient – Steady State (Note 4) RqJA 108.6 3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 4. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 17 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) VGS = 10 V gFS 1.8 4.5 VGS = 4.5 V Forward Transconductance 1.5 ID = 30 A 6.9 ID = 15 A 6.9 ID = 30 A 13.6 ID = 15 A 13.2 VDS = 1.5 V, ID = 30 A 36 mV/°C 9.0 19 mW S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 180 Total Gate Charge QG(TOT) 9.0 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) 837 VGS = 0 V, f = 1.0 MHz, VDS = 15 V VGS = 4.5 V, VDS = 15 V, ID = 30 A 347 1.42 2.8 pF nC 4.8 VGS = 10 V, VDS = 15 V, ID = 30 A 16.5 nC SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) 10 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 27 13.3 6.4 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. http://onsemi.com 2 ns NTD4979N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 6) td(ON) Turn−On Delay Time Rise Time 6.5 tr Turn−Off Delay Time td(OFF) Fall Time 20.2 VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W ns 17.2 tf 4.2 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.91 TJ = 125°C 0.82 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 30 A 1.1 V 20.8 9.8 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A ns 11 QRR 8.0 nC Source Inductance (Note 7) LS 2.85 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK (Note 7) LD Gate Inductance (Note 7) LG 4.9 Gate Resistance RG 1.0 PACKAGE PARASITIC VALUES 1.88 TA = 25°C 2.2 W 5. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. 7. Assume terminal length of 110 mils. ORDERING INFORMATION Package Shipping† NTD4979NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4979N−1G IPAK (Pb−Free) 75 Units / Rail NTD4979N−35G IPAK Trimmed Lead (Pb−Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 NTD4979N TYPICAL PERFORMANCE CURVES 70 10 V thru 4.5 V VGS = 4.2 V TJ = 25°C 50 3.8 V 40 3.4 V 30 20 3.0 V 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) 1 2 3 4 40 30 0 5 TJ = 125°C 1 TJ = −55°C 2 3 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VGS, GATE−TO−SOURCE VOLTAGE (V) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 TJ = 25°C VGS = 4.5 V VGS = 10 V 10 20 30 40 50 ID, DRAIN CURRENT (A) IDSS, LEAKAGE (nA) TJ = 150°C 1.2 1.1 1.0 0.9 1000 TJ = 125°C 100 TJ = 85°C 0.8 0.7 0 70 10000 1.7 ID = 30 A VGS = 10 V 1.6 1.5 1.4 1.3 −25 60 Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.8 0.6 −50 5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = 25°C 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.019 0.018 0.017 0.016 0.015 0.014 0.013 0.012 0.011 0.010 0.009 0.008 0.007 0.006 0.005 3.0 50 10 2.6 V 0 0 VDS = 10 V 60 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) ID, DRAIN CURRENT (A) 60 ID, DRAIN CURRENT (A) 70 25 50 75 100 125 150 175 10 VGS = 0 V 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 30 NTD4979N TYPICAL PERFORMANCE CURVES TJ = 25°C VGS = 0 V 1100 1000 C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V) 1200 Ciss 900 800 700 600 500 400 Coss 300 200 Crss 100 0 0 5 10 15 20 25 30 6 5 Qgs 4 Qgd 3 ID = 30 A TJ = 25°C VDD = 15 V VGS = 10 A 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 30 IS, SOURCE CURRENT (A) VGS = 0 V tf td(off) tr 100 10 td(on) 1 10 15 10 5 0.5 0.6 0.7 0.8 0.9 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 10 ms 100 ms 10 1 ms 0.01 0.01 TJ = 25°C VSD, SOURCE−TO−DRAIN VOLTAGE (V) 100 0.1 TJ = 125°C 20 RG, GATE RESISTANCE (W) 1000 1 25 0 0.4 100 10 ms 0 V < VGS < 10 V Single Pulse TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) 8 7 QG, TOTAL GATE CHARGE (nC) VDD = 15 V ID = 15 A VGS = 10 V I D, DRAIN CURRENT (A) QT 9 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 1 10 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (V) ID = 19 A 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 1.0 175 NTD4979N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M H C L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 905 CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− 3.00 0.118 1.60 0.063 6.17 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− NTD4979N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK CASE 369D ISSUE C C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD4979N/D
NTD4979NT4G 价格&库存

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