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or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NTD60N02R
Power MOSFET
62 A, 25 V, N−Channel, DPAK
Features
•
•
•
•
•
•
Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
Pb−Free Packages are Available
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V(BR)DSS
RDS(on) TYP
ID MAX
25 V
8.4 mW @ 10 V
62 A
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
Vdc
Gate−to−Source Voltage − Continuous
VGS
±20
Vdc
RqJC
PD
2.6
58
°C/W
W
ID
ID
ID
62
50
32
A
A
A
S
Thermal Resistance
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
80
1.87
10.5
C/W
W
A
Thermal Resistance
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
120
1.25
8.5
°C/W
W
A
TJ, and
Tstg
−55 to
175
°C
EAS
60
mJ
Operating and Storage Temperature
Single Pulse Drain−to−Source Avalanche Energy
− Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10.0 Vdc,
IL = 11 Apk, L = 1.0 mH, RG = 25 W)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
4
1 2
3
1
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
1
2 3
CASE 369AA
CASE 369AC
DPAK
3 IPAK
(Surface Mount) (Straight Lead)
STYLE 2
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
Drain
4
Drain
TL
4
4
YWW
T60
N02RG
Thermal Resistance
Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
Continuous @ TC = 25°C, Chip
Continuous @ TC = 25°C, Limited by Package
Continuous @ TA = 25°C, Limited by Wires
G
YWW
T60
N02RG
Rating
2
1
3
Drain
Gate
Source
Y
WW
T60N02R
G
1 2 3
Gate Drain Source
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
1
Publication Order Number:
NTD60N02R/D
NTD60N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
25
−
27.5
25.5
−
−
−
−
−
−
1.5
10
−
−
±100
1.0
−
1.5
4.1
2.0
−
−
−
−
11.2
8.4
8.2
12.5
10.5
−
gFS
−
27
−
Mhos
pF
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 4.5 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 31 Adc)
RDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 15 Adc) (Note 3)
Vdc
mV/°C
mW
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 20 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
Ciss
−
1000
1330
Coss
−
480
640
Crss
−
180
225
td(on)
−
7.0
−
tr
−
33
−
td(off)
−
19
−
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 31 Adc, RG = 3.0 W)
Fall Time
Gate Charge
(VGS = 4.5 Vdc, ID = 31 Adc,
VDS = 10 Vdc) (Note 3)
ns
tf
−
9.0
−
QT
−
9.5
14
QGS
−
2.2
−
QGD
−
5.0
−
VSD
−
−
−
0.88
1.15
0.80
1.2
−
−
Vdc
trr
−
29.1
−
ns
ta
−
13.6
−
tb
−
15.5
−
Qrr
−
0.02
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 31 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 31 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
mC
NTD60N02R
TYPICAL CHARACTERISTICS
VGS = 10 V
120
TJ = 25°C
120
100
4.5 V
4.2 V
4.0 V
80
3.8 V
3.6 V
3.4 V
3.2 V
3.0 V
2.8 V
60
40
20
2.6 V
0
2.4 V
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
5.0 V
8.0 V
6.0 V
2
4
6
8
10
80
60
40
TJ = 175°C
TJ = 25°C
20
TJ = −55°C
0
2
Figure 2. Transfer Characteristics
0.03
0.02
0.01
4
2
6
8
10
0.05
TJ = 25°C
0.04
0.03
0.02
VGS = 4.5 V
VGS = 10 V
0.01
0
20
40
VGS, GATE−TO−SOURCE VOLTAGE (V)
60
80
100
120
140
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100000
2.0
ID = 31 A
VGS = 10 V
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
8
Figure 1. On−Region Characteristics
0.04
10000
1.6
1.4
1.2
1.0
TJ = 175°C
1000
100
TJ = 100°C
0.8
0.6
−50
6
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 62 A
TJ = 25°C
1.8
4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.05
0
VDS w 10 V
100
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
140
−25
0
25
50
75
100
125
150
175
10
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
6
12
18
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
24
NTD60N02R
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
Ciss
1500
VGS = 0 V
VDS = 0 V
Ciss
1000
Crss
Coss
500
Crss
0
10
5
VGS
0
5
VDS
10
15
20
5
20
QT
4
QGS
16
VGS
QDS
3
12
VDS
2
8
1
0
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
2000
4
ID = 31 A
TJ = 25°C
0
2
4
6
8
0
10
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
1000
80
tr
tf
td(off)
10
td(on)
VGS = 0 V
TJ = 25°C
70
60
50
40
30
20
10
1
1
10
100
0
0.2
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
0.4
0.6
0.8
1.0
10 ms
SINGLE PULSE
TC = 25°C
100 ms
10
1 ms
10 ms
RDS(ON) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.4
1.6
Figure 10. Diode Forward Voltage versus
Current
VGS = 20 V
1
1.2
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
RG, GATE RESISTANCE (W)
ID, DRAIN CURRENT (A)
t, TIME (ns)
100
IS, SOURCE CURRENT (A)
VDD = 10 V
ID = 31 A
VGS = 10 V
dc
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
http://onsemi.com
4
1.8
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
NTD60N02R
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
0.00001
0.0001
t1
t2
DUTY CYCLE, D = t1/t2
0.001
0.01
t, TIME (s)
0.1
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1
10
Figure 12. Thermal Response
ORDERING INFORMATION
Order Number
NTD60N02R
Package
Shipping †
DPAK−3
75 Units / Rail
NTD60N02RG
DPAK−3
(Pb−Free)
75 Units / Rail
NTD60N02RT4
DPAK−3
2500 / Tape & Reel
DPAK−3
(Pb−Free)
2500 / Tape & Reel
NTD60N02R−1
DPAK−3 Straight Lead
75 Units / Rail
NTD60N02R−1G
DPAK−3 Straight Lead
(Pb−Free)
75 Units / Rail
NTD60N02R−35
DPAK−3 Straight Lead
(3.5 ± 0.15 mm)
75 Units / Rail
NTD60N02R−35G
DPAK−3 Straight Lead
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units / Rail
NTD60N02RT4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369AA−01
ISSUE A
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
4
Z
A
S
1
2
INCHES
DIM MIN
MAX
A 0.235 0.245
B 0.250 0.265
C 0.086 0.094
D 0.025 0.035
E 0.018 0.024
F 0.030 0.045
H 0.386 0.410
J
0.018 0.023
L
0.090 BSC
R 0.180 0.215
S 0.024 0.040
U 0.020
−−−
V 0.035 0.050
Z 0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
E
R
H
3
U
F
J
L
D
2 PL
0.13 (0.005)
M
T
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.63
0.89
0.46
0.61
0.77
1.14
9.80 10.40
0.46
0.58
2.29 BSC
4.57
5.45
0.60
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD60N02R
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC−01
ISSUE O
B
V
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
H
D
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
3 PL
0.13 (0.005) W
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7
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
NTD60N02R
PACKAGE DIMENSIONS
DPAK
CASE 369D−01
ISSUE B
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD60N02R/D