NTD65N03R
Power MOSFET
25 V, 65 A, Single N−Channel, DPAK
Features
•
•
•
•
Low RDS(on)
Ultra Low Gate Charge
Low Reverse Recovery Charge
Pb−Free Packages are Available
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V(BR)DSS
RDS(on) TYP
Applications
• Desktop CPU Power
• DC−DC Converters
• High and Low Side Switch
ID MAX
6.5 mW @ 10 V
25 V
65 A
9.7 mW @ 4.5 V
N−Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
V
Gate−to−Source Voltage
VGS
"20
V
ID
65
A
Continuous Drain
Current (RqJC) Limited
by Wire
TC = 25°C
TC = 85°C
Steady
State
Power Dissipation
(RqJC)
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
TC = 25°C
ID
32
A
TC = 25°C
PD
50
W
TA = 25°C
Steady
State
Steady
State
Pulsed Drain Current
ID
TA = 85°C
PD
1.88
W
TA = 25°C
ID
9.5
A
tp = 10 ms
Operating Junction and Storage
Temperature
Drain−to−Source (dv/dt)
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V, IL = 12 A,
L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
1 2
1
CASE 369AA
DPAK
(Bend Lead)
STYLE 2
7.4
PD
1.3
W
IDM
130
A
TJ, Tstg
−55 to
175
°C
dv/dt
2.0
V/ns
IS
2.1
A
EAS
71.7
mJ
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.15 in sq) [1 oz] including traces.
4
4
A
11.4
8.9
TA = 85°C
4
3
TA = 25°C
TA = 25°C
S
45
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
2 3
CASE 369AC
3 IPAK
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
YWW
65
N03G
Continuous Drain
Current (RqJC) Limited
by Die
G
YWW
65
N03G
Parameter
1
Gate
2
Drain
3
Source
Y
WW
65N03
G
1
Gate
3
Source
2
Drain
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 3
1
Publication Order Number:
NTD65N03R/D
NTD65N03R
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
2.5
°C/W
Junction−to−Ambient − Steady State (Note 3)
RqJA
80
Junction−to−Ambient − Steady State (Note 4)
RqJA
115
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
25
29.5
V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
19.2
mV/°C
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
VGS = 0 V,
VDS = 20 V
TJ = 25°C
1.5
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = "20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
"100
nA
2.0
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
gFS
1.0
1.74
4.8
mV/°C
VGS = 10 V, ID = 30 A
6.5
8.4
VGS = 4.5 V, ID = 30 A
9.7
14.6
VDS = 15 V, ID = 15 A
27
mW
mHos
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
1177
VGS = 0 V, f = 1.0 MHz,
VDS = 20 V
pF
16
nC
218
Total Gate Charge
QG(TOT)
12.2
Threshold Gate Charge
QG(TH)
1.5
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
6.08
td(on)
6.3
VGS = 5.0 V, VDS = 10 V,
ID = 30 A
1400
555
2.95
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(off)
VGS = 10 V, VDS = 25 V,
ID = 30 A, RG = 3.0 W
tf
ns
18.6
20.3
8.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.85
TJ = 125°C
0.72
tRR
28.8
Charge Time
ta
12.8
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 20 A
1.1
V
ns
16
QRR
20
LS
2.49
nC
PACKAGE PARASITIC VALUES
Source Inductance
3.
4.
5.
6.
Drain Inductance
LD
Gate Inductance
LG
Gate Resistance
RG
TA= 25°C
0.02
1.75
Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.15 in sq [1 oz] including traces).
Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
nH
3.46
W
NTD65N03R
140
10 V
7V
6V
120
TJ = 25°C
4.5 V
5.5 V
100
VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
140
5V
4.2 V
4V
3.8 V
3.6 V
3.4 V
3.2 V
3V
2.8 V
80
60
40
20
0
2
4
6
8
80
60
40
TJ = 125°C
TJ = 25°C
20
10
TJ = −55°C
2
3
4
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
0.026
0.022
0.018
0.014
TJ = 150°C
0.01
TJ = 125°C
0.006
TJ = 25°C
0.002
TJ = −55°C
20
40
60
80
100
120
140
6
0.03
VGS = 4.5 V
0.026
0.022
0.018
TJ = 150°C
0.014
TJ = 125°C
0.01
TJ = 25°C
0.006
TJ = −55°C
0.002
0
20
40
60
80
100
120
140
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
1.6
10000
VGS = 0 V
ID = 30 A
VGS = 10 V
IDSS, LEAKAGE (nA)
1.4
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.03
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
100
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
120
1.2
TJ = 150°C
1000
1.0
0.8
0.6
−50
TJ = 125°C
100
−25
0
25
50
75
100
125
150
0
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
http://onsemi.com
3
20
NTD65N03R
VGS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (V)
2400
TJ = 25°C
C, CAPACITANCE (pF)
2000
1600
Ciss
1200
800
Coss
400
Crss
0
0
4
8
12
16
20
8
VGS
6
QT
4
Q1
Q2
2
ID = 30 A
TJ = 25°C
0
0
4
12
16
Qg, TOTAL GATE CHARGE (nC)
DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
IS, SOURCE CURRENT (AMPS)
70
VDS = 10 V
ID = 35 A
VGS = 10 V
tf
td(off)
tr
100
td(on)
10
VGS = 0 V
60
50
40
30
20
TJ = 150°C
10
TJ = 25°C
0
1
1
10
100
0
0.2
0.4
0.6
0.8
1
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
100
I D, DRAIN CURRENT (AMPS)
t, TIME (ns)
8
10 ms
100 ms
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.1
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
4
100
NTD65N03R
ORDERING INFORMATION
Package
Shipping †
DPAK−3
75 Units / Rail
NTD65N03RG
DPAK−3
(Pb−Free)
75 Units / Rail
NTD65N03RT4
DPAK−3
2500 / Tape & Reel
DPAK−3
(Pb−Free)
2500 / Tape & Reel
NTD65N03R−1
DPAK−3 Straight Lead
75 Units / Rail
NTD65N03R−1G
DPAK−3 Straight Lead
(Pb−Free)
75 Units / Rail
NTD65N03R−35
DPAK Straight Lead Trimmed
(3.5 ± 0.15 mm)
75 Units / Rail
NTD65N03R−35G
DPAK Straight Lead Trimmed
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units / Rail
Order Number
NTD65N03R
NTD65N03RT4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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