NTLJS2103P

NTLJS2103P Power MOSFET Features −12 V, −7.7 A, mCoolt Single P−Channel, 2x2 mm, WDFN Package • WDFN Package Provides Exposed Drain Pad for Excellent Thermal • • • • • http://onsemi.com V(BR)DSS RDS(on) TYP 25 mW @ −4.5 V 35 mW @ −2.5 V −12 V 45 mW @ −1.8 V 60 mW @ −1.5 V 95 mW @ −1.2 V S ID MAX (Note 1) −5.9 A −5.3 A −2.0 A −1.0 A −0.2 A Conduction 2x2 mm Footprint Same as SC−88 Package Lowest RDS(on) Solution in 2x2 mm Package 1.2 V RDS(on) Rating for Operation at Low Voltage Logic Level Gate Drive Low Profile (< 0.8 mm) for Easy Fit in Thin Environments This is a Pb−Free Device Applications • High Side Load Switch • DC−DC Converters (Buck and Boost Circuits) • Optimized for Battery and Load Management Applications in • Portable Equipment Li−Ion Battery Linear Mode Charging G P−CHANNEL MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Steady State t≤5s Power Dissipation (Note 1) Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current Steady State t≤5s TA = 25°C Steady State TA = 85°C TA = 25°C PD IDM TJ, TSTG IS TL ID TA = 25°C TA = 85°C TA = 25°C PD TA = 25°C 3.3 −3.5 −2.5 0.7 −24 −55 to 150 −2.7 260 W A °C A °C A Symbol VDSS VGS ID Value −12 ±8.0 −5.9 −4.2 −7.7 1.9 W Unit V V A D S D WDFN6 CASE 506AP MARKING DIAGRAM 1 2 J7MG G 3 6 5 4 Pin 1 J7 = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS D D G 1 2 3 S (Top View) D 6 5 4 D D S tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) (Note 2) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) ORDERING INFORMATION Device NTLJS2103PTAG NTLJS2103PTBG Package WDFN6 (Pb−Free) WDFN6 (Pb−Free) Shipping† 3000/Tape & Reel 3000/Tape & Reel Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size, (30 mm2, 2 oz Cu). †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTLJS2103P/D © Semiconductor Components Industries, LLC, 2009 July, 2009 − Rev. 2 1 NTLJS2103P THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient – Steady State (Note 3) Junction−to−Ambient – t ≤ 5 s (Note 3) Junction−to−Ambient – Steady State Min Pad (Note 4) Symbol RqJA RqJA RqJA Max 65 38 180 °C/W Unit 3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu). MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Gate Threshold Temperature Coefficient Drain−to−Source On−Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = −4.5, ID = −5.9 A VGS = −4.5, ID = −3.0 A VGS = −2.5, ID = −5.3 A VGS = −2.5, ID = −3.0 A VGS = −1.8, ID = −2.0 A VGS = −1.5, ID = −1.0 A VGS = −1.2, ID = −200 mA Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Gate Resistance SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Forward Recovery Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time td(ON) tr td(OFF) tf VSD tRR ta tb QRR VGS = 0 V, dISD/dt = 100 A/ms, IS = −1.0 A TJ = 25°C TJ = 85°C VGS = −4.5 V, VDD = −8.0 V, ID = −5.9 A, RG = 2.0 W 8.0 27 74 88 0.62 0.56 27 10 17 14 nC 50 ns 1.0 ns gFS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD RG VGS = −4.5 V, VDS = −9.6 V, ID = −5.9 A VDS = −6.0 V, ID = −2.0 A CHARGES, CAPACITANCES AND GATE RESISTANCE VGS = 0 V, f = 1.0 MHz, VDS = −6.0 V 1157 300 200 12.8 0.4 1.6 3.6 15.7 W 15 nC pF VGS = VDS, ID = −250 mA −0.3 2.6 25 25 35 35 45 60 95 8.8 40 40 50 50 75 100 400 S −0.8 V mV/°C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, ID = −250 mA ID = −250 mA, Ref to 25°C VDS = −12 V, VGS = 0 V TJ = 25°C TJ = 85°C −12 −8.0 −1.0 −5.0 ±0.1 mA V mV/°C mA Symbol Test Conditions Min Typ Max Unit VDS = 0 V, VGS = ±8.0 V DRAIN−SOURCE DIODE CHARACTERISTICS VGS = 0 V, IS = −1.0 A V 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTLJS2103P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 20 −ID, DRAIN CURRENT (AMPS) 16 12 8 4 0 −1.0 V −1.1 V −1.5 V VGS = −4.5 V −2.5 V TJ = 25°C −2 V −1.8 V −ID, DRAIN CURRENT (AMPS) 20 18 16 14 12 10 8 6 4 2 0 0.5 TJ = 25°C TJ = 125°C 0.75 1.0 TJ = −55°C 1.25 1.5 1.75 2.0 2.25 2.5 VDS = −5 V −1.2 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ID = −0.2 A ID = −5.9 A TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0 2 Figure 2. Transfer Characteristics TJ = 25°C −1.2 V VGS = −1.5 V VGS = −1.8 V VGS = −2.5 V VGS = −4.5 V 4 6 8 10 12 14 16 18 20 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) −ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 −50 −25 0 25 50 75 100 125 150 1000 VGS = −4.5 V ID = −5.9 A −IDSS, LEAKAGE (nA) 100000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C 10000 TJ = 125°C 2 4 6 8 10 12 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NTLJS2103P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) -V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1800 1600 C, CAPACITANCE (pF) 1400 1200 1000 800 600 400 200 0 0 Coss Crss 2 4 6 8 10 12 Ciss VGS = 0 V TJ = 25°C f = 1 MHz 5 4 -VDS 3 6 2 QGS 1 QGD 4 VDS = −9.6 V ID = −5.9 A TJ = 25°C 0 2 4 6 8 10 12 14 2 0 -VGS QT 12 10 8 -V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 100 td(off) tf tr −IS, SOURCE CURRENT (AMPS) 10000 VGS = −4.5 V VDD = −8.0 V ID = −5.9 A t, TIME (ns) 100 VGS = 0 V 10 10 td(on) TJ = 150°C TJ = 25°C 1 1 10 RG, GATE RESISTANCE (OHMS) 100 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance 0.8 0.7 0.6 POWER (WATTS) −VGS(th) (V) 0.5 0.4 0.3 0.2 0.1 0 −50 −25 0 25 50 75 100 125 150 40 30 20 10 ID = −250 mA 50 60 Figure 10. Diode Forward Voltage vs. Current 0 0.001 0.01 0.1 1 10 100 1000 TJ, JUNCTION TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power Dissipation http://onsemi.com 4 NTLJS2103P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 100 −ID, DRAIN CURRENT (A) 10 1 ms 10 ms 1 VGS = −8 V SINGLE PULSE dc 0.1 TC = 25°C RDS(on) LIMIT Package Limit Thermal Limit 0.01 0.1 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 Figure 13. Maximum Rated Forward Biased Safe Operating Area R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE NORMALIZED (°C/W) 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 P(pk) Test Type = 1 sq in 2 oz RqJA = 1 sq in 2 oz t1 Single Pulse 0.001 0.01 0.1 PULSE TIME (s) 1 t2 DUTY CYCLE, D = t1/t2 10 0.01 0.0001 100 1000 Figure 14. FET Thermal Response http://onsemi.com 5 NTLJS2103P PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AP−01 ISSUE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4. 6. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG. DIM A A1 A3 b b1 D D2 E E2 e K L L2 J J1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 0.51 0.61 2.00 BSC 1.00 1.20 2.00 BSC 1.10 1.30 0.65 BSC 0.15 REF 0.20 0.30 0.20 0.30 0.27 REF 0.65 REF D A B 2X 0.10 C 2X 0.10 C 0.10 C 7X 0.08 C D2 6X L E2 NOTE 5 K mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÍÍ ÍÍ A3 A A1 C 4X SEATING PLANE 1 3 PIN ONE REFERENCE E STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN e L2 b1 6X SOLDERMASK DEFINED MOUNTING FOOTPRINT 2.30 1.10 6X 0.10 C A 0.05 C B 6X 0.43 1 1.25 0.35 6 4 b 0.60 0.35 6X J J1 BOTTOM VIEW 0.10 C A 0.05 C B 0.34 0.65 PITCH 0.66 NOTE 3 DIMENSIONS: MILLIMETERS http://onsemi.com 6 NTLJS2103P/D